WISC_SP22_5_Stage_Pipelined_Processor

A 5 stage pipelined multi-cycle processor that has both an I-Cache and D-Cache that is designed to work with the WISC SP22 Instruction Set Architecture. It was a 3 month project which started with the schematics of the processor and its implementation as a single cycle processor. It was then slowly upgraded by adding pipeline stages and then a cache and finally the addition of forwarding and register file bypassing in order to improve the CPI.