WISC-SP22-5-Stage-Pipelined-Processor / verilog / cache.vcheck.out
cache.vcheck.out
Raw 
Warning: Line 39 shifting by a constant value (ok except for HW2)
Warning: Line 40 shifting by a constant value (ok except for HW2)
Warning: Line 41 shifting by a constant value (ok except for HW2)
Warning: Line 42 shifting by a constant value (ok except for HW2)
Warning: Line 43 shifting by a constant value (ok except for HW2)
Warning: Line 44 shifting by a constant value (ok except for HW2)
End of file /u/s/a/sahas/private/ECE552/project/demo3/verilog/cache.v. Hash = -1421868021
Powered by GitFront