WISC-SP22-5-Stage-Pipelined-Processor / verilog / clkrst.vcheck.out
clkrst.vcheck.out
Raw
Line 20: Bad keyword integer
Line 22: Bad keyword initial
Line 23: begin without always/case
Line 30: Expected '@' after 'always'
Line 32: Bad keyword if
Line 30: Always without case(x)
Line 37: Bad keyword posedge
Line 39: Bad keyword if
Line 37: Always without case(x)
End of file /u/s/a/sahas/private/ECE552/project/demo3/verilog/clkrst.v. Hash = -1591555750