/*
   CS/ECE 552 Spring '20
  
   Filename        : decode.v
   Description     : This is the module for the overall decode stage of the processor.
*/
module decode (clk, rst, PCinc, instruction, writeData, readData1, readData2, err, writeEn_in, rd_in, writeEn_out, rs, rt, rd_out, extOutput, ALUSrc, Branch, MemWrite, MemtoReg, MemRead, JorIJump, BorJ, R7Sel, BTR, ALUOp, halt, Set, LBI, SLBI, ld, jp, nop, possibleJ);

    input clk, rst;
    input [15:0] PCinc;
    input [15:0] instruction;
    input [15:0] writeData;
    output [15:0] readData1;
    output [15:0] readData2;
    input writeEn_in;
    input [2:0] rd_in;
    output err;
    output writeEn_out;
    output [15:0] extOutput;
    output ALUSrc, Branch, MemWrite, MemtoReg, MemRead, JorIJump, BorJ, R7Sel, BTR, halt, Set, LBI, SLBI, ld, jp, nop;
    output [2:0] ALUOp;
    output [2:0] rs;
    output [2:0] rt;
    output [2:0] rd_out;
    output [15:0] possibleJ;
    
    wire [2:0] readReg1;
    wire [2:0] readReg2;
    wire [2:0] writeReg;
    wire [7:0] extInput;
    wire [2:0] rd_out;
    wire ExtSel, bigOrSmall;
    wire [1:0] RegDst;
    wire [15:0] instrJ;
    wire carry_temp;
    wire err1, err2;
    
    assign readReg1 = instruction[10:8];
    assign readReg2 = instruction[7:5];
    assign writeReg = instruction[4:2];
    assign extInput = instruction[7:0];
    assign rs = readReg1;
    assign rt = readReg2;
    assign rd_out = RegDst[1] ? (RegDst[0] ? (3'b111) : (readReg1)) : (RegDst[0] ? (writeReg) : (readReg2));
    
    control_unit cntrl(.instruction(instruction), .rst(rst), .bigOrSmall(bigOrSmall), .ExtSel(ExtSel), .ALUSrc(ALUSrc), .Branch(Branch), .MemWrite(MemWrite), .MemtoReg(MemtoReg), .MemRead(MemRead), .JorIJump(JorIJump), .BorJ(BorJ), .R7Sel(R7Sel), .writeEn(writeEn_out), .BTR(BTR), .RegDst(RegDst), .ALUOp(ALUOp), .halt(halt), .err(err1), .Set(Set), .LBI(LBI), .SLBI(SLBI), .ld(ld), .jp(jp), .nop(nop));
    
    regFile_bypass iREGISTERS(.clk(clk), .rst(rst), .err(err), .read1Data(readData1), .read2Data(readData2), .read1RegSel(rs), .read2RegSel(rt), .writeRegSel(rd_in), .writeData(writeData), .writeEn(writeEn_in));
    
    extension_unit iEXT(.In(extInput), .ext_out(extOutput), .bigOrSmall(bigOrSmall), .ExtSel(ExtSel));
    
    assign instrJ = {{5{instruction[10]}}, instruction[10:0]};
    
    cla_16b iCLA1(.S(possibleJ), .C_out(carry_temp2), .A(instrJ), .B(PCinc), .C_in(1'b0), .err(err2));
    
    assign err = err1 | err2;
   
endmodule