WISC-SP22-5-Stage-Pipelined-Processor / verilog / dff.vcheck.out
dff.vcheck.out
Raw
Line 17: Bad keyword posedge
Line 17: Always without case(x)
End of file /u/s/a/sahas/private/ECE552/project/demo3/verilog/dff.v. Hash = -892621943