WISC-SP22-5-Stage-Pipelined-Processor / verilog / diff.ptrace
diff.ptrace
Raw
INST:    1100 0001 0001 1000 lbi r1, 24
ARCH:    REG: 1 VALUE: 0x0018  
VERILOG: REG: 1 VALUE: 0x0018
INST:    0101 0001 0100 0111 xori r2, r1, 7
ARCH:    REG: 2 VALUE: 0x001f  
VERILOG: REG: 2 VALUE: 0x001f
INST:    0000 0000 0000 0000 halt
SUCCESS: No differences