/*
   CS/ECE 552 Spring '20
  
   Filename        : execute.v
   Description     : This is the overall module for the execute stage of the processor.
*/
module execute (In1, In2, Imm, ALUSrc, ALUOp, Branch, BTR, Set, ALUResult, zero, lt, gt, lte, LBI, SLBI, err, PCinc, ImmAddPCinc);

    input [15:0] In1;
    input [15:0] In2;
    input [15:0] Imm;
    input ALUSrc;
    input BTR;
    input Set;
    input [2:0] ALUOp;
    input LBI, SLBI;
    input [15:0] PCinc;
    output [15:0] ALUResult;
    output Branch;
    output zero;
    output gt;
    output lt;
    output lte;
    output err;
    output [15:0] ImmAddPCinc;
    
    wire [15:0] InA;
    wire [15:0] InB;
    wire invA;
    wire invB;
    wire [15:0] btr_out;
    wire [15:0] alu_out;
    wire zero_alu;
    wire lt_alu;
    wire lte_alu;
    wire [15:0] ALUResult_temp;
    wire [15:0] ALUResult_temp2;
    wire [15:0] ALUResult_temp3;
    wire [15:0] slbi_temp;
    wire Ofl;
    wire setCalc;
    wire gt_sig;
    wire [15:0] setResult;
    wire [2:0] setORop;
    wire [2:0] addORsub;
    wire carry_temp;
    wire carry_temp2;
    wire err1, err2;
    
    alu_control iALUCntrl(.In1(In1), .In2(In2), .Imm(Imm), .ALUOp(setORop), .ALUSrc(ALUSrc), .Cin(Cin), .Set(Set), .InA(InA), .InB(InB), .invA(invA), .invB(invB), .gt(gt_sig));
    
    alu iALU(.InA(InA), .InB(InB), .Cin(Cin), .Oper(setORop), .invA(invA), .invB(invB), .sign(1'b1), .Out(alu_out), .Zero(zero_alu), .Ofl(Ofl), .Lt(lt_alu), .Lte(lte_alu), .SLBI(SLBI), .carry_temp(carry_temp), .err(err1));
    
    btr iBTR(.InA(In1), .Out(btr_out));
    
    assign ALUResult_temp = BTR ? btr_out : alu_out;
    
    assign ALUResult_temp2 = Set ? setResult : ALUResult_temp;
    
    assign setCalc = (~ALUOp[1] & ~ALUOp[0] & zero_alu) | (~ALUOp[1] & ALUOp[0] & lt_alu) | (ALUOp[1] & ~ALUOp[0] & lte_alu) | (ALUOp[1] & ALUOp[0] & carry_temp);
    
    assign setResult = setCalc ? 16'h0001 : 16'h0000;
    
    assign zero = ~|In1;
    
    assign lt = InA[15];
    
    assign gt = ~InA[15];
    
    assign lte = InA[15] | zero;
    
    assign addORsub = ALUOp[1] ? (ALUOp[0] ? (3'b100) : (3'b101)) : (ALUOp[0] ? (3'b101) : (3'b101));
    
    assign setORop = Set ? addORsub : ALUOp;
    
    assign gt_sig = (ALUOp[1] & ALUOp[0]);
    
    assign Branch = (~ALUOp[1] & ~ALUOp[0] & zero) | (~ALUOp[1] & ALUOp[0] & ~zero) | (ALUOp[1] & ~ALUOp[0] & lt) | (ALUOp[1] & ALUOp[0] & gt);
    
    assign ALUResult_temp3 = LBI ? Imm : ALUResult_temp2;
    
    assign slbi_temp = alu_out | Imm;
    
    assign ALUResult = SLBI ? slbi_temp : ALUResult_temp3;
    
    cla_16b iCLA2(.S(ImmAddPCinc), .C_out(carry_temp2), .A(Imm), .B(PCinc), .C_in(1'b0), .err(err2)); 
    
    assign err = err1 | err2;
    
    /*ALUOp's: 000: rotate_left
               001: shift_left
               010: rotate_right
               011: shift_right
               100: add
               101: sub
               110: xor
               111: andn
               */
    
    
    
endmodule