/*
   CS/ECE 552 Spring '20
  
   Filename        : fetch.v
   Description     : This is the module for the overall fetch stage of the processor.
*/
module fetch (halt, Branch, JorIJump, BorJ, clk, rst, possibleJ, ImmAddPCinc, ALUResult, PCinc, instruction, err, err_mem, hazard_sig, stall_I_mem);

    input halt, Branch, JorIJump, BorJ, clk, rst;
    input [15:0] ALUResult;
    input [15:0] possibleJ;
    input [15:0] ImmAddPCinc;
    input hazard_sig;
    output [15:0] instruction;
    output [15:0] PCinc;
    output err;
    output err_mem;
    output stall_I_mem;
    
    wire stall;
    wire CacheHit;
    wire Done;
    wire branch_mux;
    wire [15:0] PCinc_temp;
    wire [15:0] nextPC;
    wire [15:0] PCchng;
    wire [15:0] instrAdd;
    wire [15:0] BranchOrNot;
    wire [15:0] ALUorJ;
    wire carry_temp;
    wire [15:0] hazard_check;
    wire b_resolving;
    wire [15:0] instruction_temp;
    wire halt_or_not;
    
    //assign branch_mux = Branch & branch_calc;
    
    assign branch_mux = Branch;
    
    //assign hazard_check = hazard_sig ? instrAdd : nextPC;
    
    assign halt_or_not = ~(Branch | BorJ) & halt ;
    
    assign PCchng = halt_or_not ? instrAdd : nextPC;
    
    register PC(.clk(clk), .rst(rst), .read(instrAdd), .write(PCchng));
    
    //assign instruction = b_resolving ? 16'h0800 : instruction_temp;
    
    //assign b_resolving = BorJ | branch_mux;
    
    mem_system iINSTRMEM(.DataOut(instruction), .DataIn(16'h0000), .Addr(instrAdd), .Wr(1'b0), .Rd(1'b1), .createdump(1'b0), .clk(clk), .rst(rst), .err(err_mem), .Stall(stall), .Done(Done), .CacheHit(CacheHit));
    
    assign stall_I_mem = stall & ~Done;
    
    cla_16b iCLA0(.S(PCinc_temp), .C_out(carry_temp), .A(instrAdd), .B(16'h0002), .C_in(1'b0), .err(err));
    
    assign PCinc = PCinc_temp;
    
    //These go to Decode (send PCinc to Decode and output possibleJ from decode)
    
    //assign instrJ = {{5{instruction[10]}}, instruction[10:0]};
    
    //cla_16b iCLA1(.S(possibleJ), .C_out(carry_temp), .A(instrJ), .B(PCinc_temp), .C_in(1'b0), .err(err2));
    
    assign ALUorJ = JorIJump ? possibleJ : ALUResult;
    
    //These go to Execute (Send PCinc_temp to execute and output ImmAddPCinc back to Fetch)
    
    //cla_16b iCLA2(.S(ImmAddPCinc), .C_out(carry_temp), .A(Imm), .B(PCinc_temp), .C_in(1'b0), .err(err3)); 
    
    assign hazard_check = hazard_sig ? instrAdd : PCinc_temp;
    
    assign BranchOrNot = branch_mux ? ImmAddPCinc : hazard_check;
    
    assign nextPC = BorJ ? ALUorJ : BranchOrNot;
    
    
endmodule