WISC-SP22-5-Stage-Pipelined-Processor / verilog / memc.syn.vcheck.out
memc.syn.vcheck.out
Raw
Line 20: Bad keyword integer
Line 21: Bad keyword integer
Line 25: Bad keyword posedge
Line 27: Bad keyword if
Line 35: Bad keyword if
Line 35: Bad keyword &&
Line 25: Always without case(x)
End of file /u/s/a/sahas/private/ECE552/project/demo3/verilog/memc.syn.v. Hash = 1816494331