WISC-SP22-5-Stage-Pipelined-Processor / verilog / memc.vcheck.out
memc.vcheck.out
Raw
Line 19: Bad keyword integer
Line 20: Bad keyword integer
Line 24: Bad keyword posedge
Line 26: Bad keyword if
Line 27: Bad keyword for
Line 32: Bad keyword if
Line 32: Bad keyword &&
Line 33: Bad keyword if
Line 33: Bad keyword &&
Line 64: Bad keyword for
Line 65: begin without always/case
End of file /u/s/a/sahas/private/ECE552/project/demo3/verilog/memc.v. Hash = 709983769