WISC-SP22-5-Stage-Pipelined-Processor / verilog / memv.syn.vcheck.out
memv.syn.vcheck.out
Raw
Line 19: Bad keyword integer
Line 20: Bad keyword integer
Line 24: Bad keyword posedge
Line 25: Bad keyword if
Line 32: Bad keyword if
Line 32: Bad keyword &&
Line 24: Always without case(x)
End of file /u/s/a/sahas/private/ECE552/project/demo3/verilog/memv.syn.v. Hash = 1467997613