WISC-SP22-5-Stage-Pipelined-Processor / verilog / memv.vcheck.out
memv.vcheck.out
Raw
Line 18: Bad keyword integer
Line 19: Bad keyword integer
Line 23: Bad keyword posedge
Line 24: Bad keyword if
Line 25: Bad keyword for
Line 29: Bad keyword if
Line 29: Bad keyword &&
Line 30: Bad keyword if
Line 30: Bad keyword &&
Line 38: Bad keyword for
Line 39: begin without always/case
End of file /u/s/a/sahas/private/ECE552/project/demo3/verilog/memv.v. Hash = -1694256263