/* $Author: sinclair $ */ /* $LastChangedDate: 2020-02-09 17:03:45 -0600 (Sun, 09 Feb 2020) $ */ /* $Rev: 46 $ */ module proc (/*AUTOARG*/ // Outputs err, // Inputs clk, rst ); input clk; input rst; output err; // None of the above lines can be modified // OR all the err ouputs for every sub-module and assign it as this // err output // As desribed in the homeworks, use the err signal to trap corner // cases that you think are illegal in your statemachines /* your code here -- should include instantiations of fetch, decode, execute, mem and wb modules */ wire ALUSrc, Branch, MemWrite, MemtoReg, MemRead, JorIJump, BorJ, R7Sel, BTR, halt, err_decode, err_fetch, err_execute, branch_mux, lt, gt, zero, lte, Set, SLBI, LBI; wire ALUSrc_in, MemWrite_in, MemWrite_in2, MemtoReg_in, MemtoReg_in2, MemRead_in, MemRead_in2, R7Sel_in, R7Sel_in2, R7Sel_in3, BTR_in, halt_in, halt_in2, halt_in3, Set_in, SLBI_in, LBI_in, Branch_in, BorJ_in, JorIJump_in; wire [2:0] ALUOp; wire [2:0] ALUOp_in; wire [15:0] instruction_in; wire [15:0] instruction; wire [15:0] PCinc_in4; wire [15:0] PCinc_in3; wire [15:0] PCinc_in2; wire [15:0] PCinc_in; wire [15:0] PCinc; wire [15:0] readData1_in; wire [15:0] readData1; wire [15:0] readData2_in2; wire [15:0] readData2_in; wire [15:0] readData2; wire[15:0] immediate_in; wire [15:0] immediate; wire [15:0] memreadData; wire [15:0] memreadData_in; wire branch_calc; wire [15:0] writeData; wire [15:0] ALUResult_in; wire [15:0] ALUResult; wire writeEn, writeEn_in, writeEn_in2, writeEn_in3; wire [2:0] rs_in; wire [2:0] rs; wire [2:0] rt_in; wire [2:0] rt ; wire [2:0] rd; wire [2:0] rd_in; wire [2:0] rd_in2; wire [2:0] rd_in3; wire [15:0] ImmAddPCinc; wire [15:0] possibleJ; wire [15:0] possibleJ_in; wire rst_out; wire [15:0] outData_in; wire [15:0] outData; wire error_I_mem; wire error_D_mem; wire stall_I_mem; wire stall_D_mem; wire stall_fetch; wire stall_IF_ID; wire flush_IF_ID; wire stall_ID_EX; wire stall_EX_MEM; wire flush_MEM_WB; //forwarding wires wire [15:0] In1; wire [15:0] In2; wire ld, ld_in, ld_in2; wire [1:0] readData1_sig; wire [1:0] readData2_sig; //hazard wires wire hazard_sig; wire load_hazard_sig; wire control_hazard_sig; wire [15:0] instruction_temp; wire jp, jp_in, jp_in2; wire nop, nop_in1, nop_in2, nop_in3; fetch FETCH(.halt(halt_in), .Branch(branch_mux), .JorIJump(JorIJump), .BorJ(BorJ), .ImmAddPCinc(ImmAddPCinc), .possibleJ(possibleJ), .clk(clk), .rst(rst), .ALUResult(ALUResult_in), .PCinc(PCinc_in), .instruction(instruction_in), .err(err_fetch), .err_mem(error_I_mem), .hazard_sig(stall_fetch), .stall_I_mem(stall_I_mem)); //PCinc propogates to MEM_WB pipeline IF_ID_pipeline_reg IF_ID_REG(.clk(clk), .rst(rst), .rst_out(rst_out), .instruction_in(instruction_in), .PCinc_in(PCinc_in), .instruction_out(instruction), .PCinc(PCinc_in2), .stall_sig(stall_IF_ID), .flush_sig(flush_IF_ID), .err_mem_sig(error_I_mem)); //TODO: Change decode signals to send to pipeline register //assign instruction_temp = hazard_sig ? 16'h0800 : instruction; decode DECODE(.clk(clk), .rst(rst_out), .PCinc(PCinc_in2), .instruction(instruction), .writeData(writeData), .readData1(readData1_in), .readData2(readData2_in), .err(err_decode), .writeEn_in(writeEn), .rd_in(rd), .writeEn_out(writeEn_in), .rs(rs_in), .rt(rt_in), .rd_out(rd_in), .extOutput(immediate_in), .ALUSrc(ALUSrc_in), .Branch(Branch_in), .MemWrite(MemWrite_in), .MemtoReg(MemtoReg_in), .MemRead(MemRead_in), .JorIJump(JorIJump_in), .BorJ(BorJ_in), .R7Sel(R7Sel_in), .BTR(BTR_in), .ALUOp(ALUOp_in), .halt(halt_in), .Set(Set_in), .LBI(LBI_in), .SLBI(SLBI_in), .ld(ld_in), .jp(jp_in), .nop(nop_in), .possibleJ(possibleJ_in)); // memRead, memWrite, halt, readData2 propogate to EX_MEM pipeline // PCinc, MemtoReg, R7Sel propogate to MEM_WB pipeline ID_EX_pipeline_reg ID_EX_REG(.clk(clk), .rst(rst), .InA(readData1_in), .InB(readData2_in), .Imm_in(immediate_in), .ALUSrc_in(ALUSrc_in), .BTR_in(BTR_in), .Set_in(Set_in), .ALUOp_in(ALUOp_in), .LBI_in(LBI_in), .SLBI_in(SLBI_in), .memRead_in(MemRead_in), .memWrite_in(MemWrite_in), .halt_in(halt_in), .PCinc_in(PCinc_in2), .MemtoReg_in(MemtoReg_in), .R7Sel_in(R7Sel_in), .writeEn_in(writeEn_in), .rs_in(rs_in), .rt_in(rt_in), .rd_in(rd_in), .possibleJ_in(possibleJ_in), .Branch_in(Branch_in), .BorJ_in(BorJ_in), .JorIJump_in(JorIJump_in), .ld_in(ld_in), .jp_in(jp_in), .nop_in(nop_in), .In1(readData1), .In2(readData2_in2), .Imm(immediate), .ALUSrc(ALUSrc), .BTR(BTR), .Set(Set), .ALUOp(ALUOp), .LBI(LBI), .SLBI(SLBI), .memRead(MemRead_in2), .memWrite(MemWrite_in2), .halt(halt_in2), .PCinc(PCinc_in3), .MemtoReg(MemtoReg_in2), .R7Sel(R7Sel_in2), .writeEn(writeEn_in2), .rs(rs), .rt(rt), .rd(rd_in2), .possibleJ(possibleJ), .Branch(Branch), .BorJ(BorJ), .JorIJump(JorIJump), .ld(ld_in2), .jp(jp_in2), .nop(nop_in2), .flush_sig(hazard_sig), .stall_sig(stall_ID_EX)); hazard_detection HAZARD(.IF_ID_rs(rs_in), .IF_ID_rt(rt_in), .ID_EX_rd(rd_in2), .load_to_use_hazard(load_hazard_sig), .control_hazard(control_hazard_sig), .ld(ld_in2), .branch(branch_mux), .jump(jp_in2)); assign stall_fetch = load_hazard_sig | stall_I_mem | stall_D_mem; assign stall_IF_ID = load_hazard_sig | stall_D_mem; assign flush_IF_ID = control_hazard_sig | stall_I_mem; assign stall_ID_EX = stall_D_mem; assign stall_EX_MEM = stall_D_mem; assign flush_MEM_WB = stall_D_mem; assign hazard_sig = load_hazard_sig | control_hazard_sig; assign branch_mux = Branch & branch_calc; forwarding_detection FORWARD(.ID_EX_rs(rs), .ID_EX_rt(rt), .EX_MEM_rd(rd_in3), .MEM_WB_rd(rd), .readData1_sig(readData1_sig), .readData2_sig(readData2_sig), .ld(ld), .jp(jp), .nop_EX(nop_in3), .nop_MEM(nop), .write_en_ex(writeEn_in3), .write_en_mem(writeEn)); assign In1 = readData1_sig[1] ? (readData1_sig[0] ? ALUResult : outData) : (readData1_sig[0] ? readData1 : readData1); assign In2 = readData2_sig[1] ? (readData2_sig[0] ? ALUResult : outData) : (readData2_sig[0] ? readData2_in2 : readData2_in2); execute EXECUTE(.In1(In1), .In2(In2), .Imm(immediate), .ALUSrc(ALUSrc), .ALUOp(ALUOp), .Branch(branch_calc), .BTR(BTR), .Set(Set), .ALUResult(ALUResult_in), .zero(zero), .lt(lt), .gt(gt), .lte(lte), .LBI(LBI), .SLBI(SLBI), .err(err_execute), .PCinc(PCinc_in3), .ImmAddPCinc(ImmAddPCinc)); //MemtoReg, R7Sel, ALUResult and PCinc propogate to the MEM_WB pipeline EX_MEM_pipeline_reg EX_MEM_REG(.clk(clk), .rst(rst), .ALUResult_in(ALUResult_in), .InB(In2), .memWrite_in(MemWrite_in2), .memRead_in(MemRead_in2), .halt_in(halt_in2), .PCinc_in(PCinc_in3), .MemtoReg_in(MemtoReg_in2), .R7Sel_in(R7Sel_in2), .writeEn_in(writeEn_in2), .rd_in(rd_in2), .ld_in(ld_in2), .jp_in(jp_in2), .nop_in(nop_in2), .ALUResult(ALUResult), .In2(readData2), .memWrite(MemWrite), .memRead(MemRead), .halt(halt_in3), .PCinc(PCinc_in4), .MemtoReg(MemtoReg), .R7Sel(R7Sel_in3), .writeEn(writeEn_in3), .rd(rd_in3), .ld(ld), .jp(jp), .nop(nop_in3), .flush_sig(1'b0), .stall_sig(stall_EX_MEM)); memory MEMORY(.address(ALUResult), .writeData(readData2), .outData(outData_in), .memRead(MemRead), .memWrite(MemWrite), .halt(halt_in3), .clk(clk), .rst(rst), .MemtoReg(MemtoReg), .err_mem(error_D_mem), .stall_D_mem(stall_D_mem)); assign halt = halt_in3 | error_D_mem; MEM_WB_pipeline_reg MEM_WB_REG(.clk(clk), .rst(rst), .readData_in(memreadData_in), .R7Sel_in(R7Sel_in3), .PCinc_in(PCinc_in4), .writeEn_in(writeEn_in3), .rd_in(rd_in3), .OutData_in(outData_in), .nop_in(nop_in3), .readData(memreadData), .R7Sel(R7Sel), .PCinc(PCinc), .writeEn(writeEn), .rd(rd), .OutData(outData), .nop(nop), .flush_sig(flush_MEM_WB), .stall_sig(1'b0)); wb WRITEB(.R7Sel(R7Sel), .OutData(outData), .PCinc(PCinc), .REGWriteData(writeData)); assign err = err_decode | err_execute | err_fetch; endmodule // proc // DUMMY LINE FOR REV CONTROL :0: