/*
   CS/ECE 552, Spring '22
   Homework #3, Problem #1
  
   This module creates a 16-bit register.  It has 1 write port, 2 read
   ports, 3 register select inputs, a write enable, a reset, and a clock
   input.  All register state changes occur on the rising edge of the
   clock. 
*/
module regFile (
                // Outputs
                read1Data, read2Data, err,
                // Inputs
                clk, rst, read1RegSel, read2RegSel, writeRegSel, writeData, writeEn
                );
	
   parameter WIDTHSELECT = 16;
   input        clk, rst;
   input [2:0]  read1RegSel;
   input [2:0]  read2RegSel;
   input [2:0]  writeRegSel;
   input [WIDTHSELECT - 1:0] writeData;
   input        writeEn;

   output [WIDTHSELECT - 1:0] read1Data;
   output [WIDTHSELECT - 1:0] read2Data;
   output        err;

   /* YOUR CODE HERE */
    
    wire [WIDTHSELECT - 1:0] register0_read;
    wire [WIDTHSELECT - 1:0] register1_read;
    wire [WIDTHSELECT - 1:0] register2_read;
    wire [WIDTHSELECT - 1:0] register3_read;
    wire [WIDTHSELECT - 1:0] register4_read;
    wire [WIDTHSELECT - 1:0] register5_read;
    wire [WIDTHSELECT - 1:0] register6_read;
    wire [WIDTHSELECT - 1:0] register7_read;
    wire [WIDTHSELECT - 1:0] writeIn0;
    wire [WIDTHSELECT - 1:0] writeIn1;
    wire [WIDTHSELECT - 1:0] writeIn2;
    wire [WIDTHSELECT - 1:0] writeIn3;
    wire [WIDTHSELECT - 1:0] writeIn4;
    wire [WIDTHSELECT - 1:0] writeIn5;
    wire [WIDTHSELECT - 1:0] writeIn6;
    wire [WIDTHSELECT - 1:0] writeIn7;
    wire write_en [7:0];
    wire err_temp1;
    wire err_temp2;
    wire err_temp3;
    
    assign write_en[0] = (~writeRegSel[0] & ~writeRegSel[1] & ~writeRegSel[2]) & writeEn;
    assign write_en[1] = (writeRegSel[0] & ~writeRegSel[1] & ~writeRegSel[2]) & writeEn;
    assign write_en[2] = (~writeRegSel[0] & writeRegSel[1] & ~writeRegSel[2]) & writeEn;
    assign write_en[3] = (writeRegSel[0] & writeRegSel[1] & ~writeRegSel[2]) & writeEn;
    assign write_en[4] = (~writeRegSel[0] & ~writeRegSel[1] & writeRegSel[2]) & writeEn;
    assign write_en[5] = (writeRegSel[0] & ~writeRegSel[1] & writeRegSel[2]) & writeEn;
    assign write_en[6] = (~writeRegSel[0] & writeRegSel[1] & writeRegSel[2]) & writeEn;
    assign write_en[7] = (writeRegSel[0] & writeRegSel[1] & writeRegSel[2]) & writeEn;
    
    assign writeIn0 = write_en[0] ? writeData : register0_read;
    assign writeIn1 = write_en[1] ? writeData : register1_read;
    assign writeIn2 = write_en[2] ? writeData : register2_read;
    assign writeIn3 = write_en[3] ? writeData : register3_read;
    assign writeIn4 = write_en[4] ? writeData : register4_read;
    assign writeIn5 = write_en[5] ? writeData : register5_read;
    assign writeIn6 = write_en[6] ? writeData : register6_read;
    assign writeIn7 = write_en[7] ? writeData : register7_read;

    register iREG0(.clk(clk), .rst(rst), .read(register0_read), .write(writeIn0));
    register iREG1(.clk(clk), .rst(rst), .read(register1_read), .write(writeIn1));
    register iREG2(.clk(clk), .rst(rst), .read(register2_read), .write(writeIn2));
    register iREG3(.clk(clk), .rst(rst), .read(register3_read), .write(writeIn3));
    register iREG4(.clk(clk), .rst(rst), .read(register4_read), .write(writeIn4));
    register iREG5(.clk(clk), .rst(rst), .read(register5_read), .write(writeIn5));
    register iREG6(.clk(clk), .rst(rst), .read(register6_read), .write(writeIn6));
    register iREG7(.clk(clk), .rst(rst), .read(register7_read), .write(writeIn7));
    
    assign read1Data = read1RegSel[2] ? (read1RegSel[1] ? (read1RegSel[0] ? (register7_read) : (register6_read)) : (read1RegSel[0] ? (register5_read) : (register4_read))) : (read1RegSel[1] ? (read1RegSel[0] ? (register3_read) : (register2_read)) : (read1RegSel[0] ? (register1_read) : (register0_read)));
    
    assign read2Data = read2RegSel[2] ? (read2RegSel[1] ? (read2RegSel[0] ? (register7_read) : (register6_read)) : (read2RegSel[0] ? (register5_read) : (register4_read))) : (read2RegSel[1] ? (read2RegSel[0] ? (register3_read) : (register2_read)) : (read2RegSel[0] ? (register1_read) : (register0_read)));
    
    assign err_temp1 = (writeEn === 1'bx) ? 1'b1 : ((writeEn === 1'bz) ? 1'b1 : 1'b0);

    assign err_temp2 = (read1RegSel === 3'bxxx) ? 1'b1 : ((read1RegSel === 3'bzzz) ? 1'b1 : 1'b0);

    assign err_temp3 = (read2RegSel === 3'bxxx) ? 1'b1 : ((read2RegSel === 3'bzzz) ? 1'b1 : 1'b0);

    assign err = err_temp1 | err_temp2 | err_temp3;
    
endmodule