module register(clk, rst, read, write);
	
    parameter WIDTHSELECT = 16;    

    input clk, rst;
    input [WIDTHSELECT - 1:0] write;
    output [WIDTHSELECT - 1:0] read;

    dff iDFF[WIDTHSELECT - 1:0](.q(read[WIDTHSELECT - 1:0]), .d(write[WIDTHSELECT - 1:0]), .clk(clk), .rst(rst));
      
    
endmodule