# vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" 
# Start time: 22:05:21 on May 02,2022
# //  ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic
# //
# //  Copyright 1991-2018 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  ModelSim DE and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading __work.proc_hier_pbench
# Loading __work.proc_hier
# Loading __work.clkrst
# Loading __work.proc
# Loading __work.fetch
# Loading __work.register
# Loading __work.mem_system
# Loading __work.cache
# Loading __work.memc
# Loading __work.memv
# Loading __work.four_bank_mem
# Loading __work.final_memory
# Loading __work.dff
# Loading __work.controller
# Loading __work.cla_16b
# Loading __work.carryLogic16
# Loading __work.and4
# Loading __work.nand2
# Loading __work.nor2
# Loading __work.bigG
# Loading __work.and2
# Loading __work.not1
# Loading __work.and3
# Loading __work.nand3
# Loading __work.or4
# Loading __work.or2
# Loading __work.or3
# Loading __work.nor3
# Loading __work.and5
# Loading __work.or5
# Loading __work.cla_4b
# Loading __work.carryLogic4
# Loading __work.PFA
# Loading __work.xor2
# Loading __work.IF_ID_pipeline_reg
# Loading __work.decode
# Loading __work.control_unit
# Loading __work.regFile_bypass
# Loading __work.regFile
# Loading __work.extension_unit
# Loading __work.ID_EX_pipeline_reg
# Loading __work.hazard_detection
# Loading __work.forwarding_detection
# Loading __work.execute
# Loading __work.alu_control
# Loading __work.alu
# Loading __work.shifter
# Loading __work.rotate_left
# Loading __work.shift_left
# Loading __work.rotate_right
# Loading __work.shift_right_logical
# Loading __work.btr
# Loading __work.EX_MEM_pipeline_reg
# Loading __work.memory
# Loading __work.MEM_WB_pipeline_reg
# Loading __work.wb
# log -howmany -rec /* 
# 12588
#  run -all
# Hello world...simulation starting
# See verilogsim.log and verilogsim.ptrace for output
# ** Note: $finish    : proc_hier_pbench.v(115)
#    Time: 1805 ns  Iteration: 0  Instance: /proc_hier_pbench
# End time: 22:05:21 on May 02,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0