WISC-SP22-5-Stage-Pipelined-Processor / verilog / verilogsim.log
verilogsim.log
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SIMLOG:: Cycle           4 PC: 00000000 I: 00000000 R: 0   0 00000000 M: 0 0 00000000 00000000
SIMLOG:: Cycle           5 PC: 00000000 I: 00000000 R: 0   0 00000000 M: 0 0 00000000 00000000
SIMLOG:: Cycle           6 PC: 00000000 I: 00000000 R: 0   0 00000000 M: 0 0 00000000 00000000
SIMLOG:: Cycle           7 PC: 00000000 I: 00000000 R: 0   0 00000000 M: 0 0 00000000 00000000
SIMLOG:: Cycle           8 PC: 00000000 I: 00000000 R: 0   0 00000000 M: 0 0 00000000 00000000
SIMLOG:: Cycle           9 PC: 00000000 I: 00000000 R: 0   0 00000000 M: 0 0 00000000 00000000
SIMLOG:: Cycle          10 PC: 00000000 I: 00000000 R: 0   0 00000000 M: 0 0 00000000 00000000
SIMLOG:: Cycle          11 PC: 00000000 I: 00000000 R: 0   0 00000000 M: 0 0 00000000 00000000
SIMLOG:: Cycle          12 PC: 00000000 I: 0000c118 R: 0   0 00000000 M: 0 0 00000000 00000000
SIMLOG:: Cycle          13 PC: 00000002 I: 00000000 R: 0   0 00000000 M: 0 0 00000000 00000000
SIMLOG:: Cycle          14 PC: 00000002 I: 00005147 R: 0   0 00000000 M: 0 0 00000000 00000000
SIMLOG:: Cycle          15 PC: 00000004 I: 00000000 R: 0   0 00000000 M: 0 0 00000018 00000000
SIMLOG:: Cycle          16 PC: 00000004 I: 00000000 R: 1   1 00000018 M: 0 0 00000000 00000000
SIMLOG:: Cycle          17 PC: 00000006 I: 00000000 R: 0   0 00000000 M: 0 0 0000001f 00000000
SIMLOG:: Cycle          18 PC: 00000006 I: 00000000 R: 1   2 0000001f M: 0 0 00000000 00000000
SIMLOG:: Cycle          19 PC: 00000008 I: 00000000 R: 0   0 00000000 M: 0 0 00000000 00000000
SIMLOG:: Processor halted

SIMLOG:: sim_cycles          19

SIMLOG:: inst_count           3

SIMLOG:: dcachehit_count          16

SIMLOG:: icachehit_count           9

SIMLOG:: dcachereq_count           0

SIMLOG:: icachereq_count           4
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