/*
   CS/ECE 552 Spring '20
  
   Filename        : wb.v
   Description     : This is the module for the overall Write Back stage of the processor.
*/
module wb (R7Sel, OutData, PCinc, REGWriteData);

    input R7Sel;
    input [15:0] OutData;
    input [15:0] PCinc;
    output [15:0] REGWriteData;
    
    wire [15:0] ALUorMEM;
    
    //assign ALUorMEM = MemtoReg ? MEMReadData : ALUResult;
    assign REGWriteData = R7Sel ? PCinc : OutData;
   
endmodule