Model Technology ModelSim DE vlog 10.7c Compiler 2018.08 Aug 17 2018 Start time: 21:59:05 on May 02,2022 vlog "+define+RANDSEED=3" -work __work EX_MEM_pipeline_reg.v ID_EX_pipeline_reg.v IF_ID_pipeline_reg.v MEM_WB_pipeline_reg.v PFA.v alu.v alu_control.v and2.v and3.v and4.v and5.v bigG.v btr.v cache.v carryLogic16.v carryLogic4.v cla_16b.v cla_16b_bench.v cla_4b.v clkrst.v control_unit.v controller.v decode.v decode_tb.v dff.v execute.v execute_tb.v extension_unit.v fetch.v fetch_tb.v final_memory.v forwarding_detection.v four_bank_mem.v fullAdder_1b.v fullAdder_tb.v hazard_detection.v mem_system.v mem_system_hier.v mem_system_perfbench.v mem_system_randbench.v mem_system_ref.v memc.v memory.v memory2c.v memory2c_align.v memv.v nand2.v nand3.v nor2.v nor3.v not1.v or2.v or3.v or4.v or5.v proc.v proc_hier.v proc_hier_bench.v proc_hier_pbench.v regFile.v regFile_bypass.v register.v rotate_left.v rotate_right.v shift_left.v shift_right_logical.v shifter.v shifter_hier.v shifter_hier_bench.v stallmem.v wb.v xor2.v xor3.v -- Compiling module EX_MEM_pipeline_reg -- Compiling module ID_EX_pipeline_reg -- Compiling module IF_ID_pipeline_reg -- Compiling module MEM_WB_pipeline_reg -- Compiling module PFA -- Compiling module alu -- Compiling module alu_control -- Compiling module and2 -- Compiling module and3 -- Compiling module and4 -- Compiling module and5 -- Compiling module bigG -- Compiling module btr -- Compiling module cache -- Compiling module carryLogic16 -- Compiling module carryLogic4 -- Compiling module cla_16b -- Compiling module cla_16b_bench -- Compiling module cla_4b -- Compiling module clkrst -- Compiling module control_unit -- Compiling module controller -- Compiling module decode -- Compiling module decode_tb -- Compiling module dff -- Compiling module execute -- Compiling module execute_tb -- Compiling module extension_unit -- Compiling module fetch -- Compiling module fetch_tb -- Compiling module final_memory -- Compiling module forwarding_detection -- Compiling module four_bank_mem -- Compiling module fullAdder_1b -- Compiling module fullAdder_tb -- Compiling module hazard_detection -- Compiling module mem_system -- Compiling module mem_system_hier -- Compiling module mem_system_perfbench -- Compiling module mem_system_randbench -- Compiling module mem_system_ref -- Compiling module memc -- Compiling module memory -- Compiling module memory2c -- Compiling module memory2c_align -- Compiling module memv -- Compiling module nand2 -- Compiling module nand3 -- Compiling module nor2 -- Compiling module nor3 -- Compiling module not1 -- Compiling module or2 -- Compiling module or3 -- Compiling module or4 -- Compiling module or5 -- Compiling module proc -- Compiling module proc_hier -- Compiling module proc_hier_bench -- Compiling module proc_hier_pbench -- Compiling module regFile -- Compiling module regFile_bypass -- Compiling module register -- Compiling module rotate_left -- Compiling module rotate_right -- Compiling module shift_left -- Compiling module shift_right_logical -- Compiling module shifter -- Compiling module shifter_hier -- Compiling module shifter_hier_bench -- Compiling module stallmem -- Compiling module wb -- Compiling module xor2 -- Compiling module xor3 Top level modules: cla_16b_bench decode_tb execute_tb fetch_tb fullAdder_tb mem_system_perfbench mem_system_randbench memory2c memory2c_align proc_hier_bench proc_hier_pbench shifter_hier_bench stallmem xor3 End time: 21:59:05 on May 02,2022, Elapsed time: 0:00:00 Errors: 0, Warnings: 0 Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:06 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4405 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:06 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/add_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:07 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:08 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/add_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:09 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:09 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/addi_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:11 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:11 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/addi_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:12 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:13 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/addi_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:14 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:14 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/addi_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:16 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:16 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/andn_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:17 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:18 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/andn_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:19 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:20 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/andn_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:21 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:21 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/andni_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:23 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:23 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/andni_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:24 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:25 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/andni_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:26 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:26 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/andni_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:28 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:28 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/andni_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:29 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:30 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bgez_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:31 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 12305 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:31 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bgez_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:33 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:33 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bgez_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:34 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:35 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bgez_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:36 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3505 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:37 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bgez_5.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:38 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:38 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bgez_6.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:39 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:40 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bgez_7.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:41 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 9705 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:42 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bgez_8.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:43 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:43 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bgez_9.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:45 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 5705 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:45 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/beqz_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:47 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 5905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:47 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bltz_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:48 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:49 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bltz_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:50 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:50 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bltz_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:52 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:52 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bltz_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:53 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3305 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:54 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bnez_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:55 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:56 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bnez_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:57 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:57 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bnez_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 21:59:59 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2705 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 21:59:59 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bnez_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:00 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2705 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:01 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bnez_5.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:02 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:03 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/bnez_6.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:04 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:05 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/btr_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:06 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:06 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/btr_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:08 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:08 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/btr_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:09 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:10 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/btr_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:11 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:11 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/btr_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:13 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:13 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/btr_5.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:14 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:15 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/btr_6.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:16 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:17 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/btr_7.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:18 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:18 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/btr_8.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:20 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:20 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/j_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:21 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3505 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:22 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/j_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:23 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3505 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:23 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/j_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:25 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:25 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/j_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:26 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:27 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/j_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:28 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 5505 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:28 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:30 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:30 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_10.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:31 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2505 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:32 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_11.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:33 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3505 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:34 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_12.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:35 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:36 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_15.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:37 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:37 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_16.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:38 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2505 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:39 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_17.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:40 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2705 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:41 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_19.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:42 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3305 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:42 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:44 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4205 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:44 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_22.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:45 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:46 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_24.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:47 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2505 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:48 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_25.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:49 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2505 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:49 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_26.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:51 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 5005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:51 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_27.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:53 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3305 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:54 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_28.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:55 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:55 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_29.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:57 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:57 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:00:59 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:00:59 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_30.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:00 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 5505 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:01 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_31.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:02 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:02 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_32.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:04 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2505 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:04 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_33.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:06 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2505 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:06 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_35.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:08 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:08 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_36.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:09 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:10 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:11 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:11 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:13 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:13 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_5.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:15 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:15 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_6.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:16 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3305 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:17 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jal_8.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:18 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:19 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:20 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4205 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:20 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_11.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:22 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4605 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:22 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_12.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:24 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3305 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:24 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_13.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:25 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3305 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:26 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_14.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:27 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3305 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:28 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_15.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:29 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:29 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_16.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:31 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:31 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_17.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:32 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4205 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:33 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_18.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:34 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:35 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_19.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:36 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4405 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:36 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:38 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3305 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:39 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_27.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:40 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 7005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:40 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_28.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:42 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:42 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_29.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:43 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:44 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:45 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:46 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_30.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:47 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2705 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:47 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_31.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:48 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4705 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:49 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_32.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:50 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4205 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:51 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_33.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:52 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2705 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:52 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_34.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:54 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2705 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:54 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_36.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:55 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2705 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:56 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:57 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 6005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:57 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:01:59 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 5005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:01:59 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_5.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:01 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3705 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:01 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_6.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:02 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3305 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:03 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jalr_7.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:04 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:04 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/jr_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:06 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:06 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/lbi_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:07 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:08 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/lbi_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:09 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4405 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:10 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/ld_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:11 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3605 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:11 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/ld_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:13 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3605 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:13 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/ld_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:14 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3605 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:15 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/ld_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:16 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 7705 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:17 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/rol_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:18 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:18 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/rol_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:20 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 13805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:20 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/roli_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:21 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:22 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/roli_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:23 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:23 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/roli_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:25 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:25 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/roli_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:26 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:27 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/roli_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:28 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:29 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/ror_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:30 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:30 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/ror_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:32 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:32 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/ror_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:33 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:34 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/ror_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:35 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:35 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/ror_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:37 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:37 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/ror_6.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:39 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:39 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/rori_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:40 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 13805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:41 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sco_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:42 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:42 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sco_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:44 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:44 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sco_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:46 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:46 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/seq_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:47 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 30005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:48 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/seq_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:49 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:50 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/seq_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:51 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:51 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/seq_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:53 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:53 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/seq_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:54 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:55 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/seq_5.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:56 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:57 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/seq_6.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:02:58 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:02:58 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/seq_7.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:00 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:00 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/seq_8.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:01 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:02 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/seq_9.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:03 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:03 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/siic_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:05 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:05 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/slbi_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:07 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:07 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/slbi_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:08 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:09 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/slbi_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:10 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:10 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sle_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:12 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 14905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:12 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sle_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:14 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:14 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sle_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:15 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:16 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sle_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:17 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:18 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sle_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:19 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:19 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sle_5.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:21 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:21 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sle_6.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:22 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:23 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/srl_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:24 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:24 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/srl_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:26 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:26 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/srl_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:27 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:28 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/srl_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:29 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:30 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/srl_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:31 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:31 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sll_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:33 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:33 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sll_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:34 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:35 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sll_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:36 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:37 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sll_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:38 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:38 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sll_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:40 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:40 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/slli_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:41 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4405 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:42 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/slli_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:43 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:44 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/slli_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:45 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:45 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/slt_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:47 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:47 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/slt_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:48 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:49 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/slt_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:50 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:51 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/slt_5.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:52 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 4605 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:52 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/srli_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:54 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:54 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/srli_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:55 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:56 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/srli_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:57 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:58 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/st_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:03:59 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3605 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:03:59 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/st_10.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:01 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:01 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/st_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:03 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3605 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:03 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/st_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:05 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3605 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:05 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/st_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:06 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:07 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/st_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:08 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:08 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/st_5.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:10 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:10 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/st_6.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:12 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:12 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/st_7.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:13 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:14 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/st_8.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:15 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:15 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/st_9.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:17 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:17 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/stu_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:19 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3205 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:19 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/stu_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:20 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3205 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:21 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/stu_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:22 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3205 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:23 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sub_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:24 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:24 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sub_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:26 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 3105 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:26 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sub_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:28 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:28 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sub_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:29 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:30 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sub_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:31 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:32 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sub_5.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:33 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:33 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sub_6.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:35 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:35 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/sub_7.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:36 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:37 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/subi_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:38 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:39 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/subi_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:40 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:40 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/subi_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:42 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:42 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xor_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:44 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:44 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xor_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:45 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:46 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xor_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:47 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:47 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xor_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:49 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:49 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xor_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:51 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2005 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:51 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xor_5.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:52 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:53 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xor_6.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:54 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 2905 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:54 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_0.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:56 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:56 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_10.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:04:58 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:04:59 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_11.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:05:00 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:05:01 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_12.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:05:02 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:05:02 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_13.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:05:04 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:05:04 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_1.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:05:05 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:05:06 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_2.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:05:07 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:05:08 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_3.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:05:10 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:05:10 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_4.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:05:11 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:05:12 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_5.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:05:14 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:05:14 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_6.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:05:16 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:05:16 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_7.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:05:17 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:05:18 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_8.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:05:19 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:05:20 on May 02,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Full name to pass to Assemble.java: /u/s/i/sinclair/courses/cs552/spring2022/handouts/testprograms/public/inst_tests/xori_9.asm Created the following files loadfile_0.img loadfile_1.img loadfile_2.img loadfile_3.img loadfile_all.img loadfile.lst Reading pref.tcl # 10.7c # vsim -c proc_hier_pbench -lib __work -voptargs="+acc" -wlf dump.wlf -do "log -howmany -rec /* ; run -all" # Start time: 22:05:21 on May 02,2022 # // ModelSim DE 10.7c Aug 17 2018Linux 5.4.0-109-generic # // # // Copyright 1991-2018 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim DE and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # Loading __work.proc_hier_pbench # Loading __work.proc_hier # Loading __work.clkrst # Loading __work.proc # Loading __work.fetch # Loading __work.register # Loading __work.mem_system # Loading __work.cache # Loading __work.memc # Loading __work.memv # Loading __work.four_bank_mem # Loading __work.final_memory # Loading __work.dff # Loading __work.controller # Loading __work.cla_16b # Loading __work.carryLogic16 # Loading __work.and4 # Loading __work.nand2 # Loading __work.nor2 # Loading __work.bigG # Loading __work.and2 # Loading __work.not1 # Loading __work.and3 # Loading __work.nand3 # Loading __work.or4 # Loading __work.or2 # Loading __work.or3 # Loading __work.nor3 # Loading __work.and5 # Loading __work.or5 # Loading __work.cla_4b # Loading __work.carryLogic4 # Loading __work.PFA # Loading __work.xor2 # Loading __work.IF_ID_pipeline_reg # Loading __work.decode # Loading __work.control_unit # Loading __work.regFile_bypass # Loading __work.regFile # Loading __work.extension_unit # Loading __work.ID_EX_pipeline_reg # Loading __work.hazard_detection # Loading __work.forwarding_detection # Loading __work.execute # Loading __work.alu_control # Loading __work.alu # Loading __work.shifter # Loading __work.rotate_left # Loading __work.shift_left # Loading __work.rotate_right # Loading __work.shift_right_logical # Loading __work.btr # Loading __work.EX_MEM_pipeline_reg # Loading __work.memory # Loading __work.MEM_WB_pipeline_reg # Loading __work.wb # log -howmany -rec /* # 12588 # run -all # Hello world...simulation starting # See verilogsim.log and verilogsim.ptrace for output # ** Note: $finish : proc_hier_pbench.v(115) # Time: 1805 ns Iteration: 0 Instance: /proc_hier_pbench # End time: 22:05:21 on May 02,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0