[ { "ActiveList": [], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 ], "IntegerQueue": [], "PC": 0, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [ 0, 1, 2, 3 ], "Exception": false, "ExceptionPC": 0, "FreeList": [ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 ], "IntegerQueue": [], "PC": 4, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 0, "PC": 0 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 32, "PC": 1 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 33, "PC": 2 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 34, "PC": 3 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [ 4, 5, 6, 7 ], "Exception": false, "ExceptionPC": 0, "FreeList": [ 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 ], "IntegerQueue": [ { "DestRegister": 32, "OpAIsReady": true, "OpARegTag": 0, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 1, "OpCode": "add", "PC": 0 }, { "DestRegister": 33, "OpAIsReady": false, "OpARegTag": 32, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 2, "OpCode": "add", "PC": 1 }, { "DestRegister": 34, "OpAIsReady": false, "OpARegTag": 33, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 33, "OpBValue": 0, "OpCode": "add", "PC": 2 }, { "DestRegister": 35, "OpAIsReady": false, "OpARegTag": 34, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 34, "OpBValue": 0, "OpCode": "add", "PC": 3 } ], "PC": 8, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 35, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 0, "PC": 0 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 32, "PC": 1 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 33, "PC": 2 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 34, "PC": 3 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 35, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 36, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [ 8, 9, 10, 11 ], "Exception": false, "ExceptionPC": 0, "FreeList": [ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 ], "IntegerQueue": [ { "DestRegister": 33, "OpAIsReady": false, "OpARegTag": 32, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 2, "OpCode": "add", "PC": 1 }, { "DestRegister": 34, "OpAIsReady": false, "OpARegTag": 33, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 33, "OpBValue": 0, "OpCode": "add", "PC": 2 }, { "DestRegister": 35, "OpAIsReady": false, "OpARegTag": 34, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 34, "OpBValue": 0, "OpCode": "add", "PC": 3 }, { "DestRegister": 36, "OpAIsReady": false, "OpARegTag": 35, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 35, "OpBValue": 0, "OpCode": "sub", "PC": 4 }, { "DestRegister": 37, "OpAIsReady": false, "OpARegTag": 36, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 2, "OpCode": "add", "PC": 5 }, { "DestRegister": 38, "OpAIsReady": false, "OpARegTag": 37, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 6 }, { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 39, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 0, "PC": 0 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 32, "PC": 1 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 33, "PC": 2 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 34, "PC": 3 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 35, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 36, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 ], "IntegerQueue": [ { "DestRegister": 33, "OpAIsReady": false, "OpARegTag": 32, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 2, "OpCode": "add", "PC": 1 }, { "DestRegister": 34, "OpAIsReady": false, "OpARegTag": 33, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 33, "OpBValue": 0, "OpCode": "add", "PC": 2 }, { "DestRegister": 35, "OpAIsReady": false, "OpARegTag": 34, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 34, "OpBValue": 0, "OpCode": "add", "PC": 3 }, { "DestRegister": 36, "OpAIsReady": false, "OpARegTag": 35, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 35, "OpBValue": 0, "OpCode": "sub", "PC": 4 }, { "DestRegister": 37, "OpAIsReady": false, "OpARegTag": 36, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 2, "OpCode": "add", "PC": 5 }, { "DestRegister": 38, "OpAIsReady": false, "OpARegTag": 37, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 6 }, { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 }, { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 0, "PC": 0 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 32, "PC": 1 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 33, "PC": 2 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 34, "PC": 3 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 35, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 36, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 ], "IntegerQueue": [ { "DestRegister": 34, "OpAIsReady": false, "OpARegTag": 33, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 33, "OpBValue": 0, "OpCode": "add", "PC": 2 }, { "DestRegister": 35, "OpAIsReady": false, "OpARegTag": 34, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 34, "OpBValue": 0, "OpCode": "add", "PC": 3 }, { "DestRegister": 36, "OpAIsReady": false, "OpARegTag": 35, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 35, "OpBValue": 0, "OpCode": "sub", "PC": 4 }, { "DestRegister": 37, "OpAIsReady": false, "OpARegTag": 36, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 2, "OpCode": "add", "PC": 5 }, { "DestRegister": 38, "OpAIsReady": false, "OpARegTag": 37, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 6 }, { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 }, { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 32, "PC": 1 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 33, "PC": 2 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 34, "PC": 3 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 35, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 36, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0 ], "IntegerQueue": [ { "DestRegister": 34, "OpAIsReady": false, "OpARegTag": 33, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 33, "OpBValue": 0, "OpCode": "add", "PC": 2 }, { "DestRegister": 35, "OpAIsReady": false, "OpARegTag": 34, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 34, "OpBValue": 0, "OpCode": "add", "PC": 3 }, { "DestRegister": 36, "OpAIsReady": false, "OpARegTag": 35, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 35, "OpBValue": 0, "OpCode": "sub", "PC": 4 }, { "DestRegister": 37, "OpAIsReady": false, "OpARegTag": 36, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 2, "OpCode": "add", "PC": 5 }, { "DestRegister": 38, "OpAIsReady": false, "OpARegTag": 37, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 6 }, { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 }, { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 32, "PC": 1 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 33, "PC": 2 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 34, "PC": 3 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 35, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 36, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0 ], "IntegerQueue": [ { "DestRegister": 35, "OpAIsReady": false, "OpARegTag": 34, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 34, "OpBValue": 0, "OpCode": "add", "PC": 3 }, { "DestRegister": 36, "OpAIsReady": false, "OpARegTag": 35, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 35, "OpBValue": 0, "OpCode": "sub", "PC": 4 }, { "DestRegister": 37, "OpAIsReady": false, "OpARegTag": 36, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 2, "OpCode": "add", "PC": 5 }, { "DestRegister": 38, "OpAIsReady": false, "OpARegTag": 37, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 6 }, { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 }, { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 33, "PC": 2 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 34, "PC": 3 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 35, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 36, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32 ], "IntegerQueue": [ { "DestRegister": 35, "OpAIsReady": false, "OpARegTag": 34, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 34, "OpBValue": 0, "OpCode": "add", "PC": 3 }, { "DestRegister": 36, "OpAIsReady": false, "OpARegTag": 35, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 35, "OpBValue": 0, "OpCode": "sub", "PC": 4 }, { "DestRegister": 37, "OpAIsReady": false, "OpARegTag": 36, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 2, "OpCode": "add", "PC": 5 }, { "DestRegister": 38, "OpAIsReady": false, "OpARegTag": 37, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 6 }, { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 }, { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 33, "PC": 2 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 34, "PC": 3 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 35, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 36, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32 ], "IntegerQueue": [ { "DestRegister": 36, "OpAIsReady": false, "OpARegTag": 35, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 35, "OpBValue": 0, "OpCode": "sub", "PC": 4 }, { "DestRegister": 37, "OpAIsReady": false, "OpARegTag": 36, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 2, "OpCode": "add", "PC": 5 }, { "DestRegister": 38, "OpAIsReady": false, "OpARegTag": 37, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 6 }, { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 }, { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 34, "PC": 3 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 35, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 36, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33 ], "IntegerQueue": [ { "DestRegister": 36, "OpAIsReady": false, "OpARegTag": 35, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 35, "OpBValue": 0, "OpCode": "sub", "PC": 4 }, { "DestRegister": 37, "OpAIsReady": false, "OpARegTag": 36, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 2, "OpCode": "add", "PC": 5 }, { "DestRegister": 38, "OpAIsReady": false, "OpARegTag": 37, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 6 }, { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 }, { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 34, "PC": 3 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 35, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 36, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33 ], "IntegerQueue": [ { "DestRegister": 37, "OpAIsReady": false, "OpARegTag": 36, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 2, "OpCode": "add", "PC": 5 }, { "DestRegister": 38, "OpAIsReady": false, "OpARegTag": 37, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 6 }, { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 }, { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 35, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 36, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34 ], "IntegerQueue": [ { "DestRegister": 37, "OpAIsReady": false, "OpARegTag": 36, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 2, "OpCode": "add", "PC": 5 }, { "DestRegister": 38, "OpAIsReady": false, "OpARegTag": 37, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 6 }, { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 }, { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 35, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 36, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34 ], "IntegerQueue": [ { "DestRegister": 38, "OpAIsReady": false, "OpARegTag": 37, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 6 }, { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 }, { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 36, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35 ], "IntegerQueue": [ { "DestRegister": 38, "OpAIsReady": false, "OpARegTag": 37, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 6 }, { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 }, { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 36, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35 ], "IntegerQueue": [ { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 }, { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35, 36 ], "IntegerQueue": [ { "DestRegister": 39, "OpAIsReady": false, "OpARegTag": 38, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 7 }, { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 37, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35, 36 ], "IntegerQueue": [ { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35, 36, 37 ], "IntegerQueue": [ { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 39, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "add", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 38, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35, 36, 37 ], "IntegerQueue": [ { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 4, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35, 36, 37, 38 ], "IntegerQueue": [ { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "add", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 4, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 39, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35, 36, 37, 38 ], "IntegerQueue": [ { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 4, 16, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35, 36, 37, 38, 39 ], "IntegerQueue": [ { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "divu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 4, 16, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 40, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35, 36, 37, 38, 39 ], "IntegerQueue": [ { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 4, 16, 32, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35, 36, 37, 38, 39, 40 ], "IntegerQueue": [ { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "remu", "PC": 11 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 4, 16, 32, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 41, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35, 36, 37, 38, 39, 40 ], "IntegerQueue": [], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 4, 16, 32, 64, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41 ], "IntegerQueue": [], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 4, 16, 32, 64, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 42, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41 ], "IntegerQueue": [], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 4, 16, 32, 64, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 ], "IntegerQueue": [], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 6, 12, 0, 2, 4, 16, 32, 64, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 43, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] } ]