[ { "ActiveList": [], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 ], "IntegerQueue": [], "PC": 0, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [ 0, 1, 2, 3 ], "Exception": false, "ExceptionPC": 0, "FreeList": [ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 ], "IntegerQueue": [], "PC": 4, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 0, "PC": 0 }, { "Done": false, "Exception": false, "LogicalDestination": 1, "OldDestination": 1, "PC": 1 }, { "Done": false, "Exception": false, "LogicalDestination": 2, "OldDestination": 2, "PC": 2 }, { "Done": false, "Exception": false, "LogicalDestination": 3, "OldDestination": 3, "PC": 3 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [ 4, 5, 6, 7 ], "Exception": false, "ExceptionPC": 0, "FreeList": [ 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 ], "IntegerQueue": [ { "DestRegister": 32, "OpAIsReady": true, "OpARegTag": 0, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 10, "OpCode": "add", "PC": 0 }, { "DestRegister": 33, "OpAIsReady": true, "OpARegTag": 0, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 20, "OpCode": "add", "PC": 1 }, { "DestRegister": 34, "OpAIsReady": true, "OpARegTag": 0, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 30, "OpCode": "add", "PC": 2 }, { "DestRegister": 35, "OpAIsReady": true, "OpARegTag": 0, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 40, "OpCode": "add", "PC": 3 } ], "PC": 8, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 32, 33, 34, 35, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 0, "PC": 0 }, { "Done": false, "Exception": false, "LogicalDestination": 1, "OldDestination": 1, "PC": 1 }, { "Done": false, "Exception": false, "LogicalDestination": 2, "OldDestination": 2, "PC": 2 }, { "Done": false, "Exception": false, "LogicalDestination": 3, "OldDestination": 3, "PC": 3 }, { "Done": false, "Exception": false, "LogicalDestination": 9, "OldDestination": 9, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 10, "OldDestination": 10, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 11, "OldDestination": 11, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 12, "OldDestination": 12, "PC": 7 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [ 8, 9, 10, 11 ], "Exception": false, "ExceptionPC": 0, "FreeList": [ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 ], "IntegerQueue": [ { "DestRegister": 36, "OpAIsReady": true, "OpARegTag": 0, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 50, "OpCode": "add", "PC": 4 }, { "DestRegister": 37, "OpAIsReady": true, "OpARegTag": 0, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 60, "OpCode": "add", "PC": 5 }, { "DestRegister": 38, "OpAIsReady": true, "OpARegTag": 0, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 70, "OpCode": "add", "PC": 6 }, { "DestRegister": 39, "OpAIsReady": true, "OpARegTag": 0, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 80, "OpCode": "add", "PC": 7 } ], "PC": 12, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 32, 33, 34, 35, 4, 5, 6, 7, 8, 36, 37, 38, 39, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 0, "PC": 0 }, { "Done": false, "Exception": false, "LogicalDestination": 1, "OldDestination": 1, "PC": 1 }, { "Done": false, "Exception": false, "LogicalDestination": 2, "OldDestination": 2, "PC": 2 }, { "Done": false, "Exception": false, "LogicalDestination": 3, "OldDestination": 3, "PC": 3 }, { "Done": false, "Exception": false, "LogicalDestination": 9, "OldDestination": 9, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 10, "OldDestination": 10, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 11, "OldDestination": 11, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 12, "OldDestination": 12, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 4, "OldDestination": 4, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 5, "OldDestination": 5, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 6, "OldDestination": 6, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 7, "OldDestination": 7, "PC": 11 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [ 12, 13, 14, 15 ], "Exception": false, "ExceptionPC": 0, "FreeList": [ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 ], "IntegerQueue": [ { "DestRegister": 40, "OpAIsReady": false, "OpARegTag": 32, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 36, "OpBValue": 0, "OpCode": "mulu", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": false, "OpARegTag": 33, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": false, "OpARegTag": 34, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": false, "OpARegTag": 35, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "mulu", "PC": 11 } ], "PC": 16, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 32, 33, 34, 35, 40, 41, 42, 43, 8, 36, 37, 38, 39, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 0, "PC": 0 }, { "Done": true, "Exception": false, "LogicalDestination": 1, "OldDestination": 1, "PC": 1 }, { "Done": true, "Exception": false, "LogicalDestination": 2, "OldDestination": 2, "PC": 2 }, { "Done": true, "Exception": false, "LogicalDestination": 3, "OldDestination": 3, "PC": 3 }, { "Done": false, "Exception": false, "LogicalDestination": 9, "OldDestination": 9, "PC": 4 }, { "Done": false, "Exception": false, "LogicalDestination": 10, "OldDestination": 10, "PC": 5 }, { "Done": false, "Exception": false, "LogicalDestination": 11, "OldDestination": 11, "PC": 6 }, { "Done": false, "Exception": false, "LogicalDestination": 12, "OldDestination": 12, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 4, "OldDestination": 4, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 5, "OldDestination": 5, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 6, "OldDestination": 6, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 7, "OldDestination": 7, "PC": 11 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 32, "PC": 12 }, { "Done": false, "Exception": false, "LogicalDestination": 1, "OldDestination": 33, "PC": 13 }, { "Done": false, "Exception": false, "LogicalDestination": 3, "OldDestination": 35, "PC": 14 }, { "Done": false, "Exception": false, "LogicalDestination": 2, "OldDestination": 34, "PC": 15 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [ 16, 17, 18, 19 ], "Exception": false, "ExceptionPC": 0, "FreeList": [ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 ], "IntegerQueue": [ { "DestRegister": 40, "OpAIsReady": true, "OpARegTag": 32, "OpAValue": 10, "OpBIsReady": false, "OpBRegTag": 36, "OpBValue": 0, "OpCode": "mulu", "PC": 8 }, { "DestRegister": 41, "OpAIsReady": true, "OpARegTag": 33, "OpAValue": 20, "OpBIsReady": false, "OpBRegTag": 37, "OpBValue": 0, "OpCode": "mulu", "PC": 9 }, { "DestRegister": 42, "OpAIsReady": true, "OpARegTag": 34, "OpAValue": 30, "OpBIsReady": false, "OpBRegTag": 38, "OpBValue": 0, "OpCode": "mulu", "PC": 10 }, { "DestRegister": 43, "OpAIsReady": true, "OpARegTag": 35, "OpAValue": 40, "OpBIsReady": false, "OpBRegTag": 39, "OpBValue": 0, "OpCode": "mulu", "PC": 11 }, { "DestRegister": 44, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "mulu", "PC": 12 }, { "DestRegister": 45, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 43, "OpBValue": 0, "OpCode": "mulu", "PC": 13 }, { "DestRegister": 46, "OpAIsReady": false, "OpARegTag": 43, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "mulu", "PC": 14 }, { "DestRegister": 47, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "mulu", "PC": 15 } ], "PC": 20, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 20, 30, 40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 44, 45, 47, 46, 40, 41, 42, 43, 8, 36, 37, 38, 39, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 9, "OldDestination": 9, "PC": 4 }, { "Done": true, "Exception": false, "LogicalDestination": 10, "OldDestination": 10, "PC": 5 }, { "Done": true, "Exception": false, "LogicalDestination": 11, "OldDestination": 11, "PC": 6 }, { "Done": true, "Exception": false, "LogicalDestination": 12, "OldDestination": 12, "PC": 7 }, { "Done": false, "Exception": false, "LogicalDestination": 4, "OldDestination": 4, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 5, "OldDestination": 5, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 6, "OldDestination": 6, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 7, "OldDestination": 7, "PC": 11 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 32, "PC": 12 }, { "Done": false, "Exception": false, "LogicalDestination": 1, "OldDestination": 33, "PC": 13 }, { "Done": false, "Exception": false, "LogicalDestination": 3, "OldDestination": 35, "PC": 14 }, { "Done": false, "Exception": false, "LogicalDestination": 2, "OldDestination": 34, "PC": 15 }, { "Done": false, "Exception": false, "LogicalDestination": 9, "OldDestination": 36, "PC": 16 }, { "Done": false, "Exception": false, "LogicalDestination": 10, "OldDestination": 37, "PC": 17 }, { "Done": false, "Exception": false, "LogicalDestination": 11, "OldDestination": 38, "PC": 18 }, { "Done": false, "Exception": false, "LogicalDestination": 12, "OldDestination": 39, "PC": 19 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [ 20, 21, 22, 23 ], "Exception": false, "ExceptionPC": 0, "FreeList": [ 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 0, 1, 2, 3 ], "IntegerQueue": [ { "DestRegister": 44, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "mulu", "PC": 12 }, { "DestRegister": 45, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 43, "OpBValue": 0, "OpCode": "mulu", "PC": 13 }, { "DestRegister": 46, "OpAIsReady": false, "OpARegTag": 43, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "mulu", "PC": 14 }, { "DestRegister": 47, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "mulu", "PC": 15 }, { "DestRegister": 48, "OpAIsReady": true, "OpARegTag": 36, "OpAValue": 50, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 40, "OpCode": "add", "PC": 16 }, { "DestRegister": 49, "OpAIsReady": true, "OpARegTag": 37, "OpAValue": 60, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 30, "OpCode": "add", "PC": 17 }, { "DestRegister": 50, "OpAIsReady": true, "OpARegTag": 38, "OpAValue": 70, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 20, "OpCode": "add", "PC": 18 }, { "DestRegister": 51, "OpAIsReady": true, "OpARegTag": 39, "OpAValue": 80, "OpBIsReady": true, "OpBRegTag": 0, "OpBValue": 10, "OpCode": "add", "PC": 19 } ], "PC": 24, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 20, 30, 40, 50, 60, 70, 80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 44, 45, 47, 46, 40, 41, 42, 43, 8, 48, 49, 50, 51, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 4, "OldDestination": 4, "PC": 8 }, { "Done": false, "Exception": false, "LogicalDestination": 5, "OldDestination": 5, "PC": 9 }, { "Done": false, "Exception": false, "LogicalDestination": 6, "OldDestination": 6, "PC": 10 }, { "Done": false, "Exception": false, "LogicalDestination": 7, "OldDestination": 7, "PC": 11 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 32, "PC": 12 }, { "Done": false, "Exception": false, "LogicalDestination": 1, "OldDestination": 33, "PC": 13 }, { "Done": false, "Exception": false, "LogicalDestination": 3, "OldDestination": 35, "PC": 14 }, { "Done": false, "Exception": false, "LogicalDestination": 2, "OldDestination": 34, "PC": 15 }, { "Done": false, "Exception": false, "LogicalDestination": 9, "OldDestination": 36, "PC": 16 }, { "Done": false, "Exception": false, "LogicalDestination": 10, "OldDestination": 37, "PC": 17 }, { "Done": false, "Exception": false, "LogicalDestination": 11, "OldDestination": 38, "PC": 18 }, { "Done": false, "Exception": false, "LogicalDestination": 12, "OldDestination": 39, "PC": 19 }, { "Done": false, "Exception": false, "LogicalDestination": 4, "OldDestination": 40, "PC": 20 }, { "Done": false, "Exception": false, "LogicalDestination": 5, "OldDestination": 41, "PC": 21 }, { "Done": false, "Exception": false, "LogicalDestination": 6, "OldDestination": 42, "PC": 22 }, { "Done": false, "Exception": false, "LogicalDestination": 7, "OldDestination": 43, "PC": 23 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false ], "DecodedPCs": [ 24, 25, 26, 27 ], "Exception": false, "ExceptionPC": 0, "FreeList": [ 56, 57, 58, 59, 60, 61, 62, 63, 0, 1, 2, 3, 9, 10, 11, 12 ], "IntegerQueue": [ { "DestRegister": 44, "OpAIsReady": false, "OpARegTag": 40, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 41, "OpBValue": 0, "OpCode": "mulu", "PC": 12 }, { "DestRegister": 45, "OpAIsReady": false, "OpARegTag": 41, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 43, "OpBValue": 0, "OpCode": "mulu", "PC": 13 }, { "DestRegister": 46, "OpAIsReady": false, "OpARegTag": 43, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 42, "OpBValue": 0, "OpCode": "mulu", "PC": 14 }, { "DestRegister": 47, "OpAIsReady": false, "OpARegTag": 42, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 40, "OpBValue": 0, "OpCode": "mulu", "PC": 15 }, { "DestRegister": 52, "OpAIsReady": false, "OpARegTag": 45, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 46, "OpBValue": 0, "OpCode": "sub", "PC": 20 }, { "DestRegister": 53, "OpAIsReady": false, "OpARegTag": 46, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 45, "OpBValue": 0, "OpCode": "sub", "PC": 21 }, { "DestRegister": 54, "OpAIsReady": false, "OpARegTag": 47, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 44, "OpBValue": 0, "OpCode": "sub", "PC": 22 }, { "DestRegister": 55, "OpAIsReady": false, "OpARegTag": 44, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 47, "OpBValue": 0, "OpCode": "sub", "PC": 23 } ], "PC": 28, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 20, 30, 40, 50, 60, 70, 80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 44, 45, 47, 46, 52, 53, 54, 55, 8, 48, 49, 50, 51, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 4, "OldDestination": 4, "PC": 8 }, { "Done": true, "Exception": false, "LogicalDestination": 5, "OldDestination": 5, "PC": 9 }, { "Done": true, "Exception": false, "LogicalDestination": 6, "OldDestination": 6, "PC": 10 }, { "Done": true, "Exception": false, "LogicalDestination": 7, "OldDestination": 7, "PC": 11 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 32, "PC": 12 }, { "Done": false, "Exception": false, "LogicalDestination": 1, "OldDestination": 33, "PC": 13 }, { "Done": false, "Exception": false, "LogicalDestination": 3, "OldDestination": 35, "PC": 14 }, { "Done": false, "Exception": false, "LogicalDestination": 2, "OldDestination": 34, "PC": 15 }, { "Done": false, "Exception": false, "LogicalDestination": 9, "OldDestination": 36, "PC": 16 }, { "Done": false, "Exception": false, "LogicalDestination": 10, "OldDestination": 37, "PC": 17 }, { "Done": false, "Exception": false, "LogicalDestination": 11, "OldDestination": 38, "PC": 18 }, { "Done": false, "Exception": false, "LogicalDestination": 12, "OldDestination": 39, "PC": 19 }, { "Done": false, "Exception": false, "LogicalDestination": 4, "OldDestination": 40, "PC": 20 }, { "Done": false, "Exception": false, "LogicalDestination": 5, "OldDestination": 41, "PC": 21 }, { "Done": false, "Exception": false, "LogicalDestination": 6, "OldDestination": 42, "PC": 22 }, { "Done": false, "Exception": false, "LogicalDestination": 7, "OldDestination": 43, "PC": 23 }, { "Done": false, "Exception": false, "LogicalDestination": 1, "OldDestination": 45, "PC": 24 }, { "Done": false, "Exception": false, "LogicalDestination": 2, "OldDestination": 47, "PC": 25 }, { "Done": false, "Exception": false, "LogicalDestination": 3, "OldDestination": 46, "PC": 26 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 44, "PC": 27 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false ], "DecodedPCs": [ 28, 29, 30, 31 ], "Exception": false, "ExceptionPC": 0, "FreeList": [ 60, 61, 62, 63, 0, 1, 2, 3, 9, 10, 11, 12 ], "IntegerQueue": [ { "DestRegister": 52, "OpAIsReady": false, "OpARegTag": 45, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 46, "OpBValue": 0, "OpCode": "sub", "PC": 20 }, { "DestRegister": 53, "OpAIsReady": false, "OpARegTag": 46, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 45, "OpBValue": 0, "OpCode": "sub", "PC": 21 }, { "DestRegister": 54, "OpAIsReady": false, "OpARegTag": 47, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 44, "OpBValue": 0, "OpCode": "sub", "PC": 22 }, { "DestRegister": 55, "OpAIsReady": false, "OpARegTag": 44, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 47, "OpBValue": 0, "OpCode": "sub", "PC": 23 }, { "DestRegister": 56, "OpAIsReady": false, "OpARegTag": 45, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 45, "OpBValue": 0, "OpCode": "sub", "PC": 24 }, { "DestRegister": 57, "OpAIsReady": false, "OpARegTag": 47, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 47, "OpBValue": 0, "OpCode": "sub", "PC": 25 }, { "DestRegister": 58, "OpAIsReady": false, "OpARegTag": 46, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 46, "OpBValue": 0, "OpCode": "sub", "PC": 26 }, { "DestRegister": 59, "OpAIsReady": false, "OpARegTag": 44, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 44, "OpBValue": 0, "OpCode": "sub", "PC": 27 } ], "PC": 32, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 20, 30, 40, 50, 60, 70, 80, 500, 1200, 2100, 3200, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 59, 56, 57, 58, 52, 53, 54, 55, 8, 48, 49, 50, 51, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 32, "PC": 12 }, { "Done": false, "Exception": false, "LogicalDestination": 1, "OldDestination": 33, "PC": 13 }, { "Done": false, "Exception": false, "LogicalDestination": 3, "OldDestination": 35, "PC": 14 }, { "Done": false, "Exception": false, "LogicalDestination": 2, "OldDestination": 34, "PC": 15 }, { "Done": true, "Exception": false, "LogicalDestination": 9, "OldDestination": 36, "PC": 16 }, { "Done": true, "Exception": false, "LogicalDestination": 10, "OldDestination": 37, "PC": 17 }, { "Done": true, "Exception": false, "LogicalDestination": 11, "OldDestination": 38, "PC": 18 }, { "Done": true, "Exception": false, "LogicalDestination": 12, "OldDestination": 39, "PC": 19 }, { "Done": false, "Exception": false, "LogicalDestination": 4, "OldDestination": 40, "PC": 20 }, { "Done": false, "Exception": false, "LogicalDestination": 5, "OldDestination": 41, "PC": 21 }, { "Done": false, "Exception": false, "LogicalDestination": 6, "OldDestination": 42, "PC": 22 }, { "Done": false, "Exception": false, "LogicalDestination": 7, "OldDestination": 43, "PC": 23 }, { "Done": false, "Exception": false, "LogicalDestination": 1, "OldDestination": 45, "PC": 24 }, { "Done": false, "Exception": false, "LogicalDestination": 2, "OldDestination": 47, "PC": 25 }, { "Done": false, "Exception": false, "LogicalDestination": 3, "OldDestination": 46, "PC": 26 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 44, "PC": 27 }, { "Done": false, "Exception": false, "LogicalDestination": 9, "OldDestination": 48, "PC": 28 }, { "Done": false, "Exception": false, "LogicalDestination": 10, "OldDestination": 49, "PC": 29 }, { "Done": false, "Exception": false, "LogicalDestination": 11, "OldDestination": 50, "PC": 30 }, { "Done": false, "Exception": false, "LogicalDestination": 12, "OldDestination": 51, "PC": 31 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 0, 1, 2, 3, 9, 10, 11, 12, 4, 5, 6, 7 ], "IntegerQueue": [ { "DestRegister": 52, "OpAIsReady": false, "OpARegTag": 45, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 46, "OpBValue": 0, "OpCode": "sub", "PC": 20 }, { "DestRegister": 53, "OpAIsReady": false, "OpARegTag": 46, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 45, "OpBValue": 0, "OpCode": "sub", "PC": 21 }, { "DestRegister": 54, "OpAIsReady": false, "OpARegTag": 47, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 44, "OpBValue": 0, "OpCode": "sub", "PC": 22 }, { "DestRegister": 55, "OpAIsReady": false, "OpARegTag": 44, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 47, "OpBValue": 0, "OpCode": "sub", "PC": 23 }, { "DestRegister": 56, "OpAIsReady": false, "OpARegTag": 45, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 45, "OpBValue": 0, "OpCode": "sub", "PC": 24 }, { "DestRegister": 57, "OpAIsReady": false, "OpARegTag": 47, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 47, "OpBValue": 0, "OpCode": "sub", "PC": 25 }, { "DestRegister": 58, "OpAIsReady": false, "OpARegTag": 46, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 46, "OpBValue": 0, "OpCode": "sub", "PC": 26 }, { "DestRegister": 59, "OpAIsReady": false, "OpARegTag": 44, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 44, "OpBValue": 0, "OpCode": "sub", "PC": 27 }, { "DestRegister": 60, "OpAIsReady": true, "OpARegTag": 51, "OpAValue": 90, "OpBIsReady": false, "OpBRegTag": 55, "OpBValue": 0, "OpCode": "sub", "PC": 28 }, { "DestRegister": 61, "OpAIsReady": true, "OpARegTag": 50, "OpAValue": 90, "OpBIsReady": false, "OpBRegTag": 54, "OpBValue": 0, "OpCode": "sub", "PC": 29 }, { "DestRegister": 62, "OpAIsReady": false, "OpARegTag": 61, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 53, "OpBValue": 0, "OpCode": "sub", "PC": 30 }, { "DestRegister": 63, "OpAIsReady": false, "OpARegTag": 60, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 58, "OpBValue": 0, "OpCode": "sub", "PC": 31 } ], "PC": 32, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 20, 30, 40, 50, 60, 70, 80, 500, 1200, 2100, 3200, 0, 0, 0, 0, 90, 90, 90, 90, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 59, 56, 57, 58, 52, 53, 54, 55, 8, 60, 61, 62, 63, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 32, "PC": 12 }, { "Done": true, "Exception": false, "LogicalDestination": 1, "OldDestination": 33, "PC": 13 }, { "Done": true, "Exception": false, "LogicalDestination": 3, "OldDestination": 35, "PC": 14 }, { "Done": true, "Exception": false, "LogicalDestination": 2, "OldDestination": 34, "PC": 15 }, { "Done": true, "Exception": false, "LogicalDestination": 9, "OldDestination": 36, "PC": 16 }, { "Done": true, "Exception": false, "LogicalDestination": 10, "OldDestination": 37, "PC": 17 }, { "Done": true, "Exception": false, "LogicalDestination": 11, "OldDestination": 38, "PC": 18 }, { "Done": true, "Exception": false, "LogicalDestination": 12, "OldDestination": 39, "PC": 19 }, { "Done": false, "Exception": false, "LogicalDestination": 4, "OldDestination": 40, "PC": 20 }, { "Done": false, "Exception": false, "LogicalDestination": 5, "OldDestination": 41, "PC": 21 }, { "Done": false, "Exception": false, "LogicalDestination": 6, "OldDestination": 42, "PC": 22 }, { "Done": false, "Exception": false, "LogicalDestination": 7, "OldDestination": 43, "PC": 23 }, { "Done": false, "Exception": false, "LogicalDestination": 1, "OldDestination": 45, "PC": 24 }, { "Done": false, "Exception": false, "LogicalDestination": 2, "OldDestination": 47, "PC": 25 }, { "Done": false, "Exception": false, "LogicalDestination": 3, "OldDestination": 46, "PC": 26 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 44, "PC": 27 }, { "Done": false, "Exception": false, "LogicalDestination": 9, "OldDestination": 48, "PC": 28 }, { "Done": false, "Exception": false, "LogicalDestination": 10, "OldDestination": 49, "PC": 29 }, { "Done": false, "Exception": false, "LogicalDestination": 11, "OldDestination": 50, "PC": 30 }, { "Done": false, "Exception": false, "LogicalDestination": 12, "OldDestination": 51, "PC": 31 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 0, 1, 2, 3, 9, 10, 11, 12, 4, 5, 6, 7 ], "IntegerQueue": [ { "DestRegister": 56, "OpAIsReady": true, "OpARegTag": 45, "OpAValue": 3840000, "OpBIsReady": true, "OpBRegTag": 45, "OpBValue": 3840000, "OpCode": "sub", "PC": 24 }, { "DestRegister": 57, "OpAIsReady": true, "OpARegTag": 47, "OpAValue": 1050000, "OpBIsReady": true, "OpBRegTag": 47, "OpBValue": 1050000, "OpCode": "sub", "PC": 25 }, { "DestRegister": 58, "OpAIsReady": true, "OpARegTag": 46, "OpAValue": 6720000, "OpBIsReady": true, "OpBRegTag": 46, "OpBValue": 6720000, "OpCode": "sub", "PC": 26 }, { "DestRegister": 59, "OpAIsReady": true, "OpARegTag": 44, "OpAValue": 600000, "OpBIsReady": true, "OpBRegTag": 44, "OpBValue": 600000, "OpCode": "sub", "PC": 27 }, { "DestRegister": 60, "OpAIsReady": true, "OpARegTag": 51, "OpAValue": 90, "OpBIsReady": false, "OpBRegTag": 55, "OpBValue": 0, "OpCode": "sub", "PC": 28 }, { "DestRegister": 61, "OpAIsReady": true, "OpARegTag": 50, "OpAValue": 90, "OpBIsReady": false, "OpBRegTag": 54, "OpBValue": 0, "OpCode": "sub", "PC": 29 }, { "DestRegister": 62, "OpAIsReady": false, "OpARegTag": 61, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 53, "OpBValue": 0, "OpCode": "sub", "PC": 30 }, { "DestRegister": 63, "OpAIsReady": false, "OpARegTag": 60, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 58, "OpBValue": 0, "OpCode": "sub", "PC": 31 } ], "PC": 32, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 20, 30, 40, 50, 60, 70, 80, 500, 1200, 2100, 3200, 600000, 3840000, 6720000, 1050000, 90, 90, 90, 90, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 59, 56, 57, 58, 52, 53, 54, 55, 8, 60, 61, 62, 63, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 9, "OldDestination": 36, "PC": 16 }, { "Done": true, "Exception": false, "LogicalDestination": 10, "OldDestination": 37, "PC": 17 }, { "Done": true, "Exception": false, "LogicalDestination": 11, "OldDestination": 38, "PC": 18 }, { "Done": true, "Exception": false, "LogicalDestination": 12, "OldDestination": 39, "PC": 19 }, { "Done": false, "Exception": false, "LogicalDestination": 4, "OldDestination": 40, "PC": 20 }, { "Done": false, "Exception": false, "LogicalDestination": 5, "OldDestination": 41, "PC": 21 }, { "Done": false, "Exception": false, "LogicalDestination": 6, "OldDestination": 42, "PC": 22 }, { "Done": false, "Exception": false, "LogicalDestination": 7, "OldDestination": 43, "PC": 23 }, { "Done": false, "Exception": false, "LogicalDestination": 1, "OldDestination": 45, "PC": 24 }, { "Done": false, "Exception": false, "LogicalDestination": 2, "OldDestination": 47, "PC": 25 }, { "Done": false, "Exception": false, "LogicalDestination": 3, "OldDestination": 46, "PC": 26 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 44, "PC": 27 }, { "Done": false, "Exception": false, "LogicalDestination": 9, "OldDestination": 48, "PC": 28 }, { "Done": false, "Exception": false, "LogicalDestination": 10, "OldDestination": 49, "PC": 29 }, { "Done": false, "Exception": false, "LogicalDestination": 11, "OldDestination": 50, "PC": 30 }, { "Done": false, "Exception": false, "LogicalDestination": 12, "OldDestination": 51, "PC": 31 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 0, 1, 2, 3, 9, 10, 11, 12, 4, 5, 6, 7, 32, 33, 35, 34 ], "IntegerQueue": [ { "DestRegister": 60, "OpAIsReady": true, "OpARegTag": 51, "OpAValue": 90, "OpBIsReady": false, "OpBRegTag": 55, "OpBValue": 0, "OpCode": "sub", "PC": 28 }, { "DestRegister": 61, "OpAIsReady": true, "OpARegTag": 50, "OpAValue": 90, "OpBIsReady": false, "OpBRegTag": 54, "OpBValue": 0, "OpCode": "sub", "PC": 29 }, { "DestRegister": 62, "OpAIsReady": false, "OpARegTag": 61, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 53, "OpBValue": 0, "OpCode": "sub", "PC": 30 }, { "DestRegister": 63, "OpAIsReady": false, "OpARegTag": 60, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 58, "OpBValue": 0, "OpCode": "sub", "PC": 31 } ], "PC": 32, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 20, 30, 40, 50, 60, 70, 80, 500, 1200, 2100, 3200, 600000, 3840000, 6720000, 1050000, 90, 90, 90, 90, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 59, 56, 57, 58, 52, 53, 54, 55, 8, 60, 61, 62, 63, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 4, "OldDestination": 40, "PC": 20 }, { "Done": true, "Exception": false, "LogicalDestination": 5, "OldDestination": 41, "PC": 21 }, { "Done": true, "Exception": false, "LogicalDestination": 6, "OldDestination": 42, "PC": 22 }, { "Done": true, "Exception": false, "LogicalDestination": 7, "OldDestination": 43, "PC": 23 }, { "Done": false, "Exception": false, "LogicalDestination": 1, "OldDestination": 45, "PC": 24 }, { "Done": false, "Exception": false, "LogicalDestination": 2, "OldDestination": 47, "PC": 25 }, { "Done": false, "Exception": false, "LogicalDestination": 3, "OldDestination": 46, "PC": 26 }, { "Done": false, "Exception": false, "LogicalDestination": 0, "OldDestination": 44, "PC": 27 }, { "Done": false, "Exception": false, "LogicalDestination": 9, "OldDestination": 48, "PC": 28 }, { "Done": false, "Exception": false, "LogicalDestination": 10, "OldDestination": 49, "PC": 29 }, { "Done": false, "Exception": false, "LogicalDestination": 11, "OldDestination": 50, "PC": 30 }, { "Done": false, "Exception": false, "LogicalDestination": 12, "OldDestination": 51, "PC": 31 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 0, 1, 2, 3, 9, 10, 11, 12, 4, 5, 6, 7, 32, 33, 35, 34, 36, 37, 38, 39 ], "IntegerQueue": [ { "DestRegister": 62, "OpAIsReady": false, "OpARegTag": 61, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 53, "OpBValue": 2880000, "OpCode": "sub", "PC": 30 }, { "DestRegister": 63, "OpAIsReady": false, "OpARegTag": 60, "OpAValue": 0, "OpBIsReady": false, "OpBRegTag": 58, "OpBValue": 0, "OpCode": "sub", "PC": 31 } ], "PC": 32, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 20, 30, 40, 50, 60, 70, 80, 500, 1200, 2100, 3200, 600000, 3840000, 6720000, 1050000, 90, 90, 90, 90, 18446744073706671616, 2880000, 450000, 18446744073709101616, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 59, 56, 57, 58, 52, 53, 54, 55, 8, 60, 61, 62, 63, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 1, "OldDestination": 45, "PC": 24 }, { "Done": true, "Exception": false, "LogicalDestination": 2, "OldDestination": 47, "PC": 25 }, { "Done": true, "Exception": false, "LogicalDestination": 3, "OldDestination": 46, "PC": 26 }, { "Done": true, "Exception": false, "LogicalDestination": 0, "OldDestination": 44, "PC": 27 }, { "Done": false, "Exception": false, "LogicalDestination": 9, "OldDestination": 48, "PC": 28 }, { "Done": false, "Exception": false, "LogicalDestination": 10, "OldDestination": 49, "PC": 29 }, { "Done": false, "Exception": false, "LogicalDestination": 11, "OldDestination": 50, "PC": 30 }, { "Done": false, "Exception": false, "LogicalDestination": 12, "OldDestination": 51, "PC": 31 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 0, 1, 2, 3, 9, 10, 11, 12, 4, 5, 6, 7, 32, 33, 35, 34, 36, 37, 38, 39, 40, 41, 42, 43 ], "IntegerQueue": [ { "DestRegister": 62, "OpAIsReady": false, "OpARegTag": 61, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 53, "OpBValue": 2880000, "OpCode": "sub", "PC": 30 }, { "DestRegister": 63, "OpAIsReady": false, "OpARegTag": 60, "OpAValue": 0, "OpBIsReady": true, "OpBRegTag": 58, "OpBValue": 0, "OpCode": "sub", "PC": 31 } ], "PC": 32, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 20, 30, 40, 50, 60, 70, 80, 500, 1200, 2100, 3200, 600000, 3840000, 6720000, 1050000, 90, 90, 90, 90, 18446744073706671616, 2880000, 450000, 18446744073709101616, 0, 0, 0, 0, 0, 0, 0, 0 ], "RegisterMapTable": [ 59, 56, 57, 58, 52, 53, 54, 55, 8, 60, 61, 62, 63, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 9, "OldDestination": 48, "PC": 28 }, { "Done": true, "Exception": false, "LogicalDestination": 10, "OldDestination": 49, "PC": 29 }, { "Done": false, "Exception": false, "LogicalDestination": 11, "OldDestination": 50, "PC": 30 }, { "Done": false, "Exception": false, "LogicalDestination": 12, "OldDestination": 51, "PC": 31 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 0, 1, 2, 3, 9, 10, 11, 12, 4, 5, 6, 7, 32, 33, 35, 34, 36, 37, 38, 39, 40, 41, 42, 43, 45, 47, 46, 44 ], "IntegerQueue": [], "PC": 32, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 20, 30, 40, 50, 60, 70, 80, 500, 1200, 2100, 3200, 600000, 3840000, 6720000, 1050000, 90, 90, 90, 90, 18446744073706671616, 2880000, 450000, 18446744073709101616, 0, 0, 0, 0, 450090, 18446744073709101706, 0, 0 ], "RegisterMapTable": [ 59, 56, 57, 58, 52, 53, 54, 55, 8, 60, 61, 62, 63, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": false, "Exception": false, "LogicalDestination": 11, "OldDestination": 50, "PC": 30 }, { "Done": false, "Exception": false, "LogicalDestination": 12, "OldDestination": 51, "PC": 31 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 0, 1, 2, 3, 9, 10, 11, 12, 4, 5, 6, 7, 32, 33, 35, 34, 36, 37, 38, 39, 40, 41, 42, 43, 45, 47, 46, 44, 48, 49 ], "IntegerQueue": [], "PC": 32, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 20, 30, 40, 50, 60, 70, 80, 500, 1200, 2100, 3200, 600000, 3840000, 6720000, 1050000, 90, 90, 90, 90, 18446744073706671616, 2880000, 450000, 18446744073709101616, 0, 0, 0, 0, 450090, 18446744073709101706, 0, 0 ], "RegisterMapTable": [ 59, 56, 57, 58, 52, 53, 54, 55, 8, 60, 61, 62, 63, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [ { "Done": true, "Exception": false, "LogicalDestination": 11, "OldDestination": 50, "PC": 30 }, { "Done": true, "Exception": false, "LogicalDestination": 12, "OldDestination": 51, "PC": 31 } ], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 0, 1, 2, 3, 9, 10, 11, 12, 4, 5, 6, 7, 32, 33, 35, 34, 36, 37, 38, 39, 40, 41, 42, 43, 45, 47, 46, 44, 48, 49 ], "IntegerQueue": [], "PC": 32, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 20, 30, 40, 50, 60, 70, 80, 500, 1200, 2100, 3200, 600000, 3840000, 6720000, 1050000, 90, 90, 90, 90, 18446744073706671616, 2880000, 450000, 18446744073709101616, 0, 0, 0, 0, 450090, 18446744073709101706, 18446744073706221706, 450090 ], "RegisterMapTable": [ 59, 56, 57, 58, 52, 53, 54, 55, 8, 60, 61, 62, 63, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] }, { "ActiveList": [], "BusyBitTable": [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ], "DecodedPCs": [], "Exception": false, "ExceptionPC": 0, "FreeList": [ 0, 1, 2, 3, 9, 10, 11, 12, 4, 5, 6, 7, 32, 33, 35, 34, 36, 37, 38, 39, 40, 41, 42, 43, 45, 47, 46, 44, 48, 49, 50, 51 ], "IntegerQueue": [], "PC": 32, "PhysicalRegisterFile": [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 20, 30, 40, 50, 60, 70, 80, 500, 1200, 2100, 3200, 600000, 3840000, 6720000, 1050000, 90, 90, 90, 90, 18446744073706671616, 2880000, 450000, 18446744073709101616, 0, 0, 0, 0, 450090, 18446744073709101706, 18446744073706221706, 450090 ], "RegisterMapTable": [ 59, 56, 57, 58, 52, 53, 54, 55, 8, 60, 61, 62, 63, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] } ]