****** Vivado v2021.1 (64-bit)
**** SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
**** IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/scripts/impl.tcl
# source ../target.tcl
## set ABS_TOP /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware
## set TOP z1top
## set FPGA_PART xc7z020clg400-1
## set_param general.maxThreads 4
## set_param general.maxBackupLogs 0
## set RTL { /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/EECS151.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/clocks.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/button_parser.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/debouncer.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/edge_detector.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/fifo.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/dmem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/imem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/imm_gen.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/reg_file.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/branch_predictor.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cmb_ctrl_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/pipeline.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.v }
## set CONSTRAINTS { /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.xdc }
# open_checkpoint ${ABS_TOP}/build/synth/${TOP}.dcp
Command: open_checkpoint /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/build/synth/z1top.dcp
Starting open_checkpoint Task
Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2556.422 ; gain = 0.000 ; free physical = 3871 ; free virtual = 13716
INFO: [Device 21-403] Loading part xc7z020clg400-1
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2562.727 ; gain = 0.000 ; free physical = 3451 ; free virtual = 13315
INFO: [Netlist 29-17] Analyzing 183 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2021.1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2606.574 ; gain = 0.000 ; free physical = 2964 ; free virtual = 12826
Restored from archive | CPU: 0.090000 secs | Memory: 1.166237 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2606.574 ; gain = 0.000 ; free physical = 2964 ; free virtual = 12826
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2606.574 ; gain = 0.000 ; free physical = 2962 ; free virtual = 12825
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 43 instances were transformed.
RAM16X1D => RAM32X1D (RAMD32(x2)): 29 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 10 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
INFO: [Project 1-604] Checkpoint was created with Vivado v2021.1 (64-bit) build 3247384
open_checkpoint: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 2606.574 ; gain = 50.156 ; free physical = 2961 ; free virtual = 12824
# if {[string trim ${CONSTRAINTS}] ne ""} {
# read_xdc ${CONSTRAINTS}
# }
Parsing XDC File [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.xdc]
Finished Parsing XDC File [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.xdc]
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.92 . Memory (MB): peak = 2681.207 ; gain = 74.633 ; free physical = 2955 ; free virtual = 12819
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks
Ending Cache Timing Information Task | Checksum: 1180de9fa
Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2753.020 ; gain = 71.812 ; free physical = 2953 ; free virtual = 12817
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 10d21d685
Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2909.020 ; gain = 0.004 ; free physical = 2779 ; free virtual = 12644
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Retarget, 2 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: e35a9d46
Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.30 . Memory (MB): peak = 2909.020 ; gain = 0.004 ; free physical = 2779 ; free virtual = 12644
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 1444f049f
Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2909.020 ; gain = 0.004 ; free physical = 2779 ; free virtual = 12644
INFO: [Opt 31-389] Phase Sweep created 1 cells and removed 4 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 1444f049f
Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2909.020 ; gain = 0.004 ; free physical = 2778 ; free virtual = 12643
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 1444f049f
Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2909.020 ; gain = 0.004 ; free physical = 2778 ; free virtual = 12643
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 1444f049f
Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2909.020 ; gain = 0.004 ; free physical = 2777 ; free virtual = 12642
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 2 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 1 | 4 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2909.020 ; gain = 0.000 ; free physical = 2772 ; free virtual = 12637
Ending Logic Optimization Task | Checksum: dbc3d097
Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2909.020 ; gain = 0.004 ; free physical = 2772 ; free virtual = 12637
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 34 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 68
Ending PowerOpt Patch Enables Task | Checksum: dbc3d097
Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2739 ; free virtual = 12602
Ending Power Optimization Task | Checksum: dbc3d097
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 3134.133 ; gain = 225.113 ; free physical = 2747 ; free virtual = 12611
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: dbc3d097
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2747 ; free virtual = 12611
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2746 ; free virtual = 12610
Ending Netlist Obfuscation Task | Checksum: dbc3d097
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2746 ; free virtual = 12610
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 3134.133 ; gain = 527.559 ; free physical = 2746 ; free virtual = 12610
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2703 ; free virtual = 12570
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cba4c4cd
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2703 ; free virtual = 12570
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2703 ; free virtual = 12570
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
CRITICAL WARNING: [Place 30-722] Terminal 'AUD_PWM' has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fa9dd115
Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2736 ; free virtual = 12602
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1a44bf6b2
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2752 ; free virtual = 12618
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1a44bf6b2
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2752 ; free virtual = 12618
Phase 1 Placer Initialization | Checksum: 1a44bf6b2
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2752 ; free virtual = 12617
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1e72930a8
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2748 ; free virtual = 12614
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1a9270f04
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2747 ; free virtual = 12612
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1a9270f04
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2746 ; free virtual = 12611
Phase 2.4 Global Placement Core
Phase 2.4.1 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 66 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 25 nets or LUTs. Breaked 0 LUT, combined 25 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2733 ; free virtual = 12599
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 25 | 25 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 25 | 25 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.1 Physical Synthesis In Placer | Checksum: e9579e65
Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2733 ; free virtual = 12599
Phase 2.4 Global Placement Core | Checksum: 1af9826f7
Time (s): cpu = 00:00:12 ; elapsed = 00:00:06 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2733 ; free virtual = 12598
Phase 2 Global Placement | Checksum: 1af9826f7
Time (s): cpu = 00:00:12 ; elapsed = 00:00:06 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2734 ; free virtual = 12600
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1937cc0ab
Time (s): cpu = 00:00:12 ; elapsed = 00:00:06 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2734 ; free virtual = 12599
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 10f302df4
Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2731 ; free virtual = 12594
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 147fe693f
Time (s): cpu = 00:00:14 ; elapsed = 00:00:07 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2725 ; free virtual = 12588
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 128697d09
Time (s): cpu = 00:00:14 ; elapsed = 00:00:07 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2723 ; free virtual = 12586
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 2199d0a7c
Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2734 ; free virtual = 12598
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1a3ef5df2
Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2734 ; free virtual = 12598
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 18455f204
Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2734 ; free virtual = 12598
Phase 3 Detail Placement | Checksum: 18455f204
Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2734 ; free virtual = 12598
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 113319c5f
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.548 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1053b900d
Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2726 ; free virtual = 12590
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Ending Physical Synthesis Task | Checksum: 339c9d8d
Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.21 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2723 ; free virtual = 12587
Phase 4.1.1.1 BUFG Insertion | Checksum: 113319c5f
Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2720 ; free virtual = 12584
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=1.548. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 10f258b14
Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2716 ; free virtual = 12579
Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2716 ; free virtual = 12579
Phase 4.1 Post Commit Optimization | Checksum: 10f258b14
Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2729 ; free virtual = 12593
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 10f258b14
Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2726 ; free virtual = 12590
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 4x4|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 2x2|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 10f258b14
Time (s): cpu = 00:00:17 ; elapsed = 00:00:09 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2724 ; free virtual = 12587
Phase 4.3 Placer Reporting | Checksum: 10f258b14
Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2722 ; free virtual = 12585
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2722 ; free virtual = 12585
Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2722 ; free virtual = 12585
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1644f462d
Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2717 ; free virtual = 12581
Ending Placer Task | Checksum: 78a74cdc
Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2716 ; free virtual = 12579
INFO: [Common 17-83] Releasing license: Implementation
29 Infos, 0 Warnings, 1 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:11 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2728 ; free virtual = 12591
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
# write_checkpoint -force ${TOP}_placed.dcp
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.71 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2743 ; free virtual = 12612
INFO: [Common 17-1381] The checkpoint '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/build/impl/z1top_placed.dcp' has been generated.
# report_utilization -file post_place_utilization.rpt
# phys_opt_design
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 4 threads
WARNING: [DRC PLIO-8] Placement Constraints Check for IO constraints: Terminal AUD_PWM has IOB constraint set to TRUE, but it is either not connected to a FLOP element or the connected FLOP element could not be brought into the I/O.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
Checksum: PlaceDB: 1e15181c ConstDB: 0 ShapeSum: 5a9234c0 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: b9a0b780
Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2591 ; free virtual = 12442
Post Restoration Checksum: NetGraph: ab7f6d01 NumContArr: e214a7f Constraints: 0 Timing: 0
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: b9a0b780
Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2611 ; free virtual = 12457
Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: b9a0b780
Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2588 ; free virtual = 12434
Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: b9a0b780
Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 3134.133 ; gain = 0.000 ; free physical = 2587 ; free virtual = 12433
Number of Nodes with overlaps = 0
Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 1f3b7f5cc
Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 3149.023 ; gain = 14.891 ; free physical = 2582 ; free virtual = 12429
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.759 | TNS=0.000 | WHS=-0.152 | THS=-28.476|
Phase 2 Router Initialization | Checksum: 1764ecb82
Time (s): cpu = 00:00:27 ; elapsed = 00:00:20 . Memory (MB): peak = 3149.023 ; gain = 14.891 ; free physical = 2559 ; free virtual = 12425
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
Global Horizontal Routing Utilization = 0 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 2261
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 2261
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 1764ecb82
Time (s): cpu = 00:00:27 ; elapsed = 00:00:20 . Memory (MB): peak = 3150.148 ; gain = 16.016 ; free physical = 2554 ; free virtual = 12420
Phase 3 Initial Routing | Checksum: 235f9d703
Time (s): cpu = 00:00:59 ; elapsed = 00:00:30 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2553 ; free virtual = 12417
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 1371
Number of Nodes with overlaps = 581
Number of Nodes with overlaps = 290
Number of Nodes with overlaps = 152
Number of Nodes with overlaps = 71
Number of Nodes with overlaps = 22
Number of Nodes with overlaps = 7
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.395 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 10fb9e8ac
Time (s): cpu = 00:01:42 ; elapsed = 00:00:51 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2541 ; free virtual = 12409
Phase 4.2 Global Iteration 1
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.395 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.2 Global Iteration 1 | Checksum: 1623f3150
Time (s): cpu = 00:01:42 ; elapsed = 00:00:52 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2544 ; free virtual = 12411
Phase 4 Rip-up And Reroute | Checksum: 1623f3150
Time (s): cpu = 00:01:42 ; elapsed = 00:00:52 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2544 ; free virtual = 12411
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1623f3150
Time (s): cpu = 00:01:43 ; elapsed = 00:00:52 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2544 ; free virtual = 12411
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1623f3150
Time (s): cpu = 00:01:43 ; elapsed = 00:00:52 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2544 ; free virtual = 12411
Phase 5 Delay and Skew Optimization | Checksum: 1623f3150
Time (s): cpu = 00:01:43 ; elapsed = 00:00:52 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2544 ; free virtual = 12411
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: eefc1896
Time (s): cpu = 00:01:43 ; elapsed = 00:00:52 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2543 ; free virtual = 12410
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.424 | TNS=0.000 | WHS=0.075 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: eefc1896
Time (s): cpu = 00:01:43 ; elapsed = 00:00:52 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2543 ; free virtual = 12410
Phase 6 Post Hold Fix | Checksum: eefc1896
Time (s): cpu = 00:01:43 ; elapsed = 00:00:52 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2543 ; free virtual = 12410
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 1.11432 %
Global Horizontal Routing Utilization = 1.69177 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 128702134
Time (s): cpu = 00:01:43 ; elapsed = 00:00:52 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2543 ; free virtual = 12410
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 128702134
Time (s): cpu = 00:01:44 ; elapsed = 00:00:52 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2541 ; free virtual = 12408
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 182c77580
Time (s): cpu = 00:01:44 ; elapsed = 00:00:53 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2535 ; free virtual = 12400
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.424 | TNS=0.000 | WHS=0.075 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 182c77580
Time (s): cpu = 00:01:45 ; elapsed = 00:00:53 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2543 ; free virtual = 12408
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:01:45 ; elapsed = 00:00:53 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2567 ; free virtual = 12432
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
13 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 3226.148 ; gain = 92.016 ; free physical = 2567 ; free virtual = 12432
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
# write_checkpoint -force ${TOP}_routed.dcp
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.69 . Memory (MB): peak = 3234.152 ; gain = 0.004 ; free physical = 2557 ; free virtual = 12428
INFO: [Common 17-1381] The checkpoint '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/build/impl/z1top_routed.dcp' has been generated.
# write_verilog -force post_route.v
# write_xdc -force post_route.xdc
# report_drc -file post_route_drc.rpt
Command: report_drc -file post_route_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/share/instsww/xilinx/Vivado/2021.1/data/ip'.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/build/impl/post_route_drc.rpt.
report_drc completed successfully
# report_timing_summary -warn_on_violation -file post_route_timing_summary.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
# write_bitstream -force ${TOP}.bit
Command: write_bitstream -force z1top.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./z1top.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [#UNDEF] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/build/impl/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Fri Dec 9 08:08:15 2022. For additional details about this file, please refer to the WebTalk help file at /share/instsww/xilinx/Vivado/2021.1/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
10 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 3536.020 ; gain = 301.867 ; free physical = 2516 ; free virtual = 12380
INFO: [Common 17-206] Exiting Vivado at Fri Dec 9 08:08:15 2022...