Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021 | Date : Fri Dec 9 08:06:48 2022 | Host : c111-4.eecs.berkeley.edu running 64-bit CentOS Linux release 7.9.2009 (Core) | Command : report_utilization -file post_place_utilization.rpt | Design : z1top | Device : 7z020clg400-1 | Design State : Fully Placed ---------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Slice Logic 1.1 Summary of Registers by Type 2. Slice Logic Distribution 3. Memory 4. DSP 5. IO and GT Specific 6. Clocking 7. Specific Feature 8. Primitives 9. Black Boxes 10. Instantiated Netlists 1. Slice Logic -------------- +----------------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +----------------------------+------+-------+------------+-----------+-------+ | Slice LUTs | 1486 | 0 | 0 | 53200 | 2.79 | | LUT as Logic | 1413 | 0 | 0 | 53200 | 2.66 | | LUT as Memory | 73 | 0 | 0 | 17400 | 0.42 | | LUT as Distributed RAM | 73 | 0 | | | | | LUT as Shift Register | 0 | 0 | | | | | Slice Registers | 543 | 0 | 0 | 106400 | 0.51 | | Register as Flip Flop | 543 | 0 | 0 | 106400 | 0.51 | | Register as Latch | 0 | 0 | 0 | 106400 | 0.00 | | F7 Muxes | 0 | 0 | 0 | 26600 | 0.00 | | F8 Muxes | 0 | 0 | 0 | 13300 | 0.00 | +----------------------------+------+-------+------------+-----------+-------+ 1.1 Summary of Registers by Type -------------------------------- +-------+--------------+-------------+--------------+ | Total | Clock Enable | Synchronous | Asynchronous | +-------+--------------+-------------+--------------+ | 0 | _ | - | - | | 0 | _ | - | Set | | 0 | _ | - | Reset | | 0 | _ | Set | - | | 0 | _ | Reset | - | | 0 | Yes | - | - | | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 2 | Yes | Set | - | | 543 | Yes | Reset | - | +-------+--------------+-------------+--------------+ 2. Slice Logic Distribution --------------------------- +--------------------------------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +--------------------------------------------+------+-------+------------+-----------+-------+ | Slice | 469 | 0 | 0 | 13300 | 3.53 | | SLICEL | 320 | 0 | | | | | SLICEM | 149 | 0 | | | | | LUT as Logic | 1413 | 0 | 0 | 53200 | 2.66 | | using O5 output only | 0 | | | | | | using O6 output only | 1196 | | | | | | using O5 and O6 | 217 | | | | | | LUT as Memory | 73 | 0 | 0 | 17400 | 0.42 | | LUT as Distributed RAM | 73 | 0 | | | | | using O5 output only | 1 | | | | | | using O6 output only | 0 | | | | | | using O5 and O6 | 72 | | | | | | LUT as Shift Register | 0 | 0 | | | | | Slice Registers | 543 | 0 | 0 | 106400 | 0.51 | | Register driven from within the Slice | 322 | | | | | | Register driven from outside the Slice | 221 | | | | | | LUT in front of the register is unused | 53 | | | | | | LUT in front of the register is used | 168 | | | | | | Unique Control Sets | 16 | | 0 | 13300 | 0.12 | +--------------------------------------------+------+-------+------------+-----------+-------+ * * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. 3. Memory --------- +-------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------+------+-------+------------+-----------+-------+ | Block RAM Tile | 34 | 0 | 0 | 140 | 24.29 | | RAMB36/FIFO* | 34 | 0 | 0 | 140 | 24.29 | | RAMB36E1 only | 34 | | | | | | RAMB18 | 0 | 0 | 0 | 280 | 0.00 | +-------------------+------+-------+------------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 4. DSP ------ +-----------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-----------+------+-------+------------+-----------+-------+ | DSPs | 0 | 0 | 0 | 220 | 0.00 | +-----------+------+-------+------------+-----------+-------+ 5. IO and GT Specific --------------------- +-----------------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-----------------------------+------+-------+------------+-----------+-------+ | Bonded IOB | 13 | 13 | 0 | 125 | 10.40 | | IOB Master Pads | 6 | | | | | | IOB Slave Pads | 7 | | | | | | IOB Flip Flops | 2 | 2 | | | | | Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | | Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 | | PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 | | PHASER_REF | 0 | 0 | 0 | 4 | 0.00 | | OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 | | IN_FIFO | 0 | 0 | 0 | 16 | 0.00 | | IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 | | IBUFDS | 0 | 0 | 0 | 121 | 0.00 | | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 | | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 | | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 | | ILOGIC | 1 | 1 | 0 | 125 | 0.80 | | IFF_Register | 1 | 1 | | | | | OLOGIC | 1 | 1 | 0 | 125 | 0.80 | | OUTFF_Register | 1 | 1 | | | | +-----------------------------+------+-------+------------+-----------+-------+ 6. Clocking ----------- +------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +------------+------+-------+------------+-----------+-------+ | BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 | | BUFIO | 0 | 0 | 0 | 16 | 0.00 | | MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 | | PLLE2_ADV | 1 | 0 | 0 | 4 | 25.00 | | BUFMRCE | 0 | 0 | 0 | 8 | 0.00 | | BUFHCE | 0 | 0 | 0 | 72 | 0.00 | | BUFR | 0 | 0 | 0 | 16 | 0.00 | +------------+------+-------+------------+-----------+-------+ 7. Specific Feature ------------------- +-------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------+------+-------+------------+-----------+-------+ | BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | | CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | | DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | | EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | | FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | | ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | | STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | | XADC | 0 | 0 | 0 | 1 | 0.00 | +-------------+------+-------+------------+-----------+-------+ 8. Primitives ------------- +-----------+------+---------------------+ | Ref Name | Used | Functional Category | +-----------+------+---------------------+ | LUT6 | 740 | LUT | | FDRE | 543 | Flop & Latch | | LUT4 | 297 | LUT | | LUT5 | 269 | LUT | | LUT3 | 185 | LUT | | LUT2 | 128 | LUT | | RAMD32 | 124 | Distributed Memory | | CARRY4 | 104 | CarryLogic | | RAMB36E1 | 34 | Block Memory | | RAMS32 | 21 | Distributed Memory | | LUT1 | 11 | LUT | | OBUFT | 6 | IO | | IBUF | 4 | IO | | OBUF | 3 | IO | | FDSE | 2 | Flop & Latch | | BUFG | 2 | Clock | | PLLE2_ADV | 1 | Clock | +-----------+------+---------------------+ 9. Black Boxes -------------- +----------+------+ | Ref Name | Used | +----------+------+ 10. Instantiated Netlists ------------------------- +----------+------+ | Ref Name | Used | +----------+------+