// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021 // Date : Fri Dec 9 08:05:45 2022 // Host : c111-4.eecs.berkeley.edu running 64-bit CentOS Linux release 7.9.2009 (Core) // Command : write_verilog -force -file post_synth.v // Design : z1top // Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an // IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input // design files. // Device : xc7z020clg400-1 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps module bios_mem (\f_ex_imm_reg[16] , \f_ex_imm_reg[4] , \f_ex_imm_reg[4]_0 , wb_mux, \ex_wb_inst_reg[12] , \f_ex_pc_reg[30] , p_1_in, ex_alu, dmem_we, imem_wea, \clock_counter_reg[0] , start, SR, p_1_in_0, douta_reg_0_0, out, \f_ex_pc_reg[30]_0 , \f_ex_inst_reg[12] , ADDRARDADDR, addra, \f_ex_inst_reg[2] , addr, CO, wb_BrEq_i_7_0, BrLt, \wb_alu_reg[1] , \wb_alu_reg[0] , cnt_reset, douta_reg_0_1, douta_reg_1_0, \tx_shift_reg[8] , \wb_alu_reg[0]_i_18_0 , \wb_alu_reg[0]_i_18_1 , ALUSel, Q, BSel, mem_reg_3_3, mem_reg_r1_0_31_18_23_i_15_0, mem_reg_r1_0_31_6_11_i_15_0, mem_reg_r1_0_31_6_11_i_23_0, mem_reg_r1_0_31_6_11_i_12_0, mem_reg_r1_0_31_6_11_i_21_0, mem_reg_r1_0_31_6_11_i_18_0, mem_reg_r1_0_31_12_17_i_11_0, mem_reg_r1_0_31_12_17_i_8_0, mem_reg_r1_0_31_12_17_i_17_0, mem_reg_r1_0_31_18_23_i_15_1, mem_reg_r1_0_31_12_17_i_21_0, mem_reg_r1_0_31_12_17_i_19_0, mem_reg_r1_0_31_18_23_i_9_0, mem_reg_r1_0_31_18_23_i_7_0, mem_reg_r1_0_31_18_23_i_13_0, mem_reg_r1_0_31_18_23_i_11_0, mem_reg_r1_0_31_18_23_i_17_0, mem_reg_r1_0_31_18_23_i_15_2, wb_BrLt_reg_i_2_0, wb_BrLt_reg_i_2_1, wb_BrLt_reg_i_3_0, douta_reg_0_2, mem_reg_2_0, mem_reg_2_3, MemRW, \wb_alu_reg[16] , wb_BrLt_reg_i_2_2, symbol_edge__7, buttons_pressed, cpu_clk_locked, tx_shift, tx_running__2, doutb, \br_inst_cnt_reg[0] , \br_inst_cnt_reg[0]_0 , wb_BrLt_i_63_0, \pprev_data_reg[0] , \pprev_data_reg[0]_0 , mem_reg_1_0, mem_reg_1_0_0, wb_BrLt_i_63_1, \pprev_data_reg[1] , mem_reg_1_0_1, wb_BrEq_i_32_0, wb_BrLt_i_62_0, wb_BrEq_i_31_0, wb_BrEq_i_31_1, wb_BrLt_i_60_0, wb_BrLt_i_60_1, wb_BrEq_i_30_0, wb_BrLt_i_46_0, wb_BrEq_i_29_0, wb_BrEq_i_29_1, wb_BrLt_i_44_0, wb_BrLt_i_44_1, wb_BrEq_i_16_0, wb_BrLt_i_43_0, wb_BrEq_i_15_0, wb_BrEq_i_15_1, wb_BrLt_i_25_0, wb_BrLt_i_25_1, wb_BrEq_i_14_0, wb_BrLt_i_24_0, wb_BrEq_i_13_0, wb_BrEq_i_13_1, wb_BrLt_i_8_0, wb_BrLt_i_8_1, wb_BrEq_i_7_1, wb_BrLt_i_7_0, wb_BrEq_i_6_0, wb_BrEq_i_6_1, \pprev_data_reg[2] , mem_reg_1_1, \pprev_data_reg[3] , mem_reg_1_1_0, \pprev_data_reg[4] , mem_reg_1_2, mem_reg_1_2_0, mem_reg_1_3, mem_reg_1_3_0, mem_reg_1_0_2, mem_reg_1_0_3, mem_reg_1_1_1, mem_reg_1_1_2, mem_reg_1_2_1, mem_reg_1_2_2, mem_reg_1_3_1, mem_reg_1_3_2, mem_reg_2_0_i_14_0, mem_reg_2_0_i_13_0, mem_reg_2_1_i_4_0, mem_reg_2_1_i_3_0, mem_reg_2_2_i_6_0, mem_reg_2_2_i_5_0, mem_reg_2_3_i_4_0, mem_reg_2_3_i_3_0, mem_reg_3_0, mem_reg_3_0_0, mem_reg_3_1, mem_reg_3_1_0, mem_reg_3_2, mem_reg_3_2_0, mem_reg_3_3_0, S, \wb_alu[28]_i_6 , mem_reg_3_3_1, \wb_alu_reg[29] , \wb_alu[21]_i_3_0 , mem_reg_3_3_2, \bit_counter[3]_i_11_0 , \bit_counter[3]_i_11_1 , \wb_alu[23]_i_4_0 , douta_reg_0_3, douta_reg_0_4, douta_reg_0_5, douta_reg_0_6, \wb_alu[20]_i_4_0 , \bit_counter[3]_i_17_0 , mem_reg_3_3_3, \bit_counter[3]_i_15_0 , \wb_alu[22]_i_3_0 , douta_reg_0_7, douta_reg_0_8, douta_reg_0_9, \wb_alu_reg[22] , mem_reg_2_2, \bit_counter[3]_i_15_1 , \bit_counter[3]_i_12_0 , \bit_counter[3]_i_12_1 , \bit_counter[3]_i_17_1 , \wb_alu_reg[28] , douta_reg_1_1, \bit_counter[3]_i_16_0 , \bit_counter[3]_i_12_2 , \wb_alu_reg[29]_0 , DI, wb_BrLt_reg, mem_reg_3_0_1, \pprev_data_reg[0]_1 , mem_wb_mux, mem_reg_0_0_i_227_0, mem_reg_0_0_i_224_0, \pprev_data_reg[2]_0 , mem_reg_0_1_i_7_0, \pprev_data_reg[3]_0 , mem_reg_0_1_i_5_0, \pprev_data_reg[4]_0 , mem_reg_0_2_i_7_0, \pprev_data_reg[5] , \pprev_data_reg[6] , \pprev_data_reg[7] , \pprev_data[31]_i_2 , mem_reg_0_0_i_227_1, mem_reg_0_0_i_224_1, mem_reg_0_1_i_7_1, mem_reg_0_1_i_5_1, mem_reg_0_2_i_7_1, mem_reg_r1_0_31_0_5_i_22_0, mem_reg_r1_0_31_6_11_i_9_0, mem_reg_r1_0_31_6_11_i_15_1, \bit_counter[3]_i_5_0 , \bit_counter[3]_i_5_1 , mem_reg_3_3_4, mem_reg_3_3_5, \bit_counter[3]_i_4_0 , mem_reg_1_3_3, \wb_alu_reg[29]_i_5_0 , ASel, \pprev_data_reg[5]_0 , \pprev_data_reg[6]_0 , \pprev_data_reg[7]_0 , \pprev_data_reg[8] , \pprev_data_reg[9] , \pprev_data_reg[10] , \pprev_data_reg[11] , \pprev_data_reg[12] , \pprev_data_reg[13] , \pprev_data_reg[14] , \pprev_data_reg[15] , \pprev_data_reg[16] , \pprev_data_reg[17] , \pprev_data_reg[18] , \pprev_data_reg[19] , \pprev_data_reg[20] , \pprev_data_reg[21] , \pprev_data_reg[22] , \pprev_data_reg[23] , \pprev_data_reg[24] , \pprev_data_reg[25] , \pprev_data_reg[26] , \pprev_data_reg[27] , \pprev_data_reg[28] , \pprev_data_reg[29] , \pprev_data_reg[30] , dout, cpu_clk, sel); output [2:0]\f_ex_imm_reg[16] ; output \f_ex_imm_reg[4] ; output \f_ex_imm_reg[4]_0 ; output [30:0]wb_mux; output \ex_wb_inst_reg[12] ; output [7:0]\f_ex_pc_reg[30] ; output [31:0]p_1_in; output [30:0]ex_alu; output [3:0]dmem_we; output [3:0]imem_wea; output \clock_counter_reg[0] ; output start; output [0:0]SR; output [6:0]p_1_in_0; output douta_reg_0_0; output [31:0]out; output [17:0]\f_ex_pc_reg[30]_0 ; output \f_ex_inst_reg[12] ; output [13:0]ADDRARDADDR; output [1:0]addra; output [1:0]\f_ex_inst_reg[2] ; output [1:0]addr; output [0:0]CO; output [0:0]wb_BrEq_i_7_0; output BrLt; output \wb_alu_reg[1] ; output \wb_alu_reg[0] ; output cnt_reset; output douta_reg_0_1; output [19:0]douta_reg_1_0; output \tx_shift_reg[8] ; input [0:0]\wb_alu_reg[0]_i_18_0 ; input [0:0]\wb_alu_reg[0]_i_18_1 ; input [3:0]ALUSel; input [30:0]Q; input BSel; input [0:0]mem_reg_3_3; input mem_reg_r1_0_31_18_23_i_15_0; input mem_reg_r1_0_31_6_11_i_15_0; input [5:0]mem_reg_r1_0_31_6_11_i_23_0; input mem_reg_r1_0_31_6_11_i_12_0; input mem_reg_r1_0_31_6_11_i_21_0; input mem_reg_r1_0_31_6_11_i_18_0; input mem_reg_r1_0_31_12_17_i_11_0; input mem_reg_r1_0_31_12_17_i_8_0; input mem_reg_r1_0_31_12_17_i_17_0; input mem_reg_r1_0_31_18_23_i_15_1; input mem_reg_r1_0_31_12_17_i_21_0; input mem_reg_r1_0_31_12_17_i_19_0; input mem_reg_r1_0_31_18_23_i_9_0; input mem_reg_r1_0_31_18_23_i_7_0; input mem_reg_r1_0_31_18_23_i_13_0; input mem_reg_r1_0_31_18_23_i_11_0; input mem_reg_r1_0_31_18_23_i_17_0; input mem_reg_r1_0_31_18_23_i_15_2; input wb_BrLt_reg_i_2_0; input wb_BrLt_reg_i_2_1; input wb_BrLt_reg_i_3_0; input douta_reg_0_2; input [4:0]mem_reg_2_0; input [0:0]mem_reg_2_3; input [2:0]MemRW; input \wb_alu_reg[16] ; input wb_BrLt_reg_i_2_2; input symbol_edge__7; input buttons_pressed; input cpu_clk_locked; input [6:0]tx_shift; input tx_running__2; input [2:0]doutb; input \br_inst_cnt_reg[0] ; input \br_inst_cnt_reg[0]_0 ; input wb_BrLt_i_63_0; input \pprev_data_reg[0] ; input \pprev_data_reg[0]_0 ; input mem_reg_1_0; input mem_reg_1_0_0; input wb_BrLt_i_63_1; input \pprev_data_reg[1] ; input mem_reg_1_0_1; input wb_BrEq_i_32_0; input wb_BrLt_i_62_0; input wb_BrEq_i_31_0; input wb_BrEq_i_31_1; input wb_BrLt_i_60_0; input wb_BrLt_i_60_1; input wb_BrEq_i_30_0; input wb_BrLt_i_46_0; input wb_BrEq_i_29_0; input wb_BrEq_i_29_1; input wb_BrLt_i_44_0; input wb_BrLt_i_44_1; input wb_BrEq_i_16_0; input wb_BrLt_i_43_0; input wb_BrEq_i_15_0; input wb_BrEq_i_15_1; input wb_BrLt_i_25_0; input wb_BrLt_i_25_1; input wb_BrEq_i_14_0; input wb_BrLt_i_24_0; input wb_BrEq_i_13_0; input wb_BrEq_i_13_1; input wb_BrLt_i_8_0; input wb_BrLt_i_8_1; input wb_BrEq_i_7_1; input wb_BrLt_i_7_0; input wb_BrEq_i_6_0; input wb_BrEq_i_6_1; input \pprev_data_reg[2] ; input mem_reg_1_1; input \pprev_data_reg[3] ; input mem_reg_1_1_0; input \pprev_data_reg[4] ; input mem_reg_1_2; input mem_reg_1_2_0; input mem_reg_1_3; input mem_reg_1_3_0; input mem_reg_1_0_2; input mem_reg_1_0_3; input mem_reg_1_1_1; input mem_reg_1_1_2; input mem_reg_1_2_1; input mem_reg_1_2_2; input mem_reg_1_3_1; input mem_reg_1_3_2; input mem_reg_2_0_i_14_0; input mem_reg_2_0_i_13_0; input mem_reg_2_1_i_4_0; input mem_reg_2_1_i_3_0; input mem_reg_2_2_i_6_0; input mem_reg_2_2_i_5_0; input mem_reg_2_3_i_4_0; input mem_reg_2_3_i_3_0; input mem_reg_3_0; input mem_reg_3_0_0; input mem_reg_3_1; input mem_reg_3_1_0; input mem_reg_3_2; input mem_reg_3_2_0; input mem_reg_3_3_0; input [0:0]S; input [0:0]\wb_alu[28]_i_6 ; input mem_reg_3_3_1; input \wb_alu_reg[29] ; input \wb_alu[21]_i_3_0 ; input mem_reg_3_3_2; input \bit_counter[3]_i_11_0 ; input \bit_counter[3]_i_11_1 ; input \wb_alu[23]_i_4_0 ; input douta_reg_0_3; input douta_reg_0_4; input douta_reg_0_5; input douta_reg_0_6; input \wb_alu[20]_i_4_0 ; input \bit_counter[3]_i_17_0 ; input mem_reg_3_3_3; input \bit_counter[3]_i_15_0 ; input \wb_alu[22]_i_3_0 ; input douta_reg_0_7; input douta_reg_0_8; input douta_reg_0_9; input \wb_alu_reg[22] ; input mem_reg_2_2; input \bit_counter[3]_i_15_1 ; input \bit_counter[3]_i_12_0 ; input \bit_counter[3]_i_12_1 ; input \bit_counter[3]_i_17_1 ; input \wb_alu_reg[28] ; input douta_reg_1_1; input \bit_counter[3]_i_16_0 ; input \bit_counter[3]_i_12_2 ; input \wb_alu_reg[29]_0 ; input [0:0]DI; input [0:0]wb_BrLt_reg; input mem_reg_3_0_1; input [2:0]\pprev_data_reg[0]_1 ; input [17:0]mem_wb_mux; input mem_reg_0_0_i_227_0; input mem_reg_0_0_i_224_0; input \pprev_data_reg[2]_0 ; input mem_reg_0_1_i_7_0; input \pprev_data_reg[3]_0 ; input mem_reg_0_1_i_5_0; input \pprev_data_reg[4]_0 ; input mem_reg_0_2_i_7_0; input \pprev_data_reg[5] ; input \pprev_data_reg[6] ; input \pprev_data_reg[7] ; input \pprev_data[31]_i_2 ; input mem_reg_0_0_i_227_1; input mem_reg_0_0_i_224_1; input mem_reg_0_1_i_7_1; input mem_reg_0_1_i_5_1; input mem_reg_0_2_i_7_1; input mem_reg_r1_0_31_0_5_i_22_0; input mem_reg_r1_0_31_6_11_i_9_0; input mem_reg_r1_0_31_6_11_i_15_1; input \bit_counter[3]_i_5_0 ; input \bit_counter[3]_i_5_1 ; input mem_reg_3_3_4; input mem_reg_3_3_5; input \bit_counter[3]_i_4_0 ; input mem_reg_1_3_3; input [30:0]\wb_alu_reg[29]_i_5_0 ; input ASel; input \pprev_data_reg[5]_0 ; input \pprev_data_reg[6]_0 ; input \pprev_data_reg[7]_0 ; input \pprev_data_reg[8] ; input \pprev_data_reg[9] ; input \pprev_data_reg[10] ; input \pprev_data_reg[11] ; input \pprev_data_reg[12] ; input \pprev_data_reg[13] ; input \pprev_data_reg[14] ; input \pprev_data_reg[15] ; input \pprev_data_reg[16] ; input \pprev_data_reg[17] ; input \pprev_data_reg[18] ; input \pprev_data_reg[19] ; input \pprev_data_reg[20] ; input \pprev_data_reg[21] ; input \pprev_data_reg[22] ; input \pprev_data_reg[23] ; input \pprev_data_reg[24] ; input \pprev_data_reg[25] ; input \pprev_data_reg[26] ; input \pprev_data_reg[27] ; input \pprev_data_reg[28] ; input \pprev_data_reg[29] ; input \pprev_data_reg[30] ; input [31:0]dout; input cpu_clk; input [10:0]sel; wire \<const0> ; wire \<const1> ; wire [13:0]ADDRARDADDR; wire [3:0]ALUSel; wire ASel; wire BSel; wire BrLt; wire [0:0]CO; wire [0:0]DI; wire [2:0]MemRW; wire [30:0]Q; wire [0:0]S; wire [0:0]SR; wire [30:0]a_mux; wire [1:0]addr; wire [1:0]addra; wire [29:0]\alu/data0 ; wire \alu/data2 ; wire \alu/data3 ; wire [30:0]\alu/data8 ; wire [30:0]b_mux; wire \bit_counter[3]_i_11_0 ; wire \bit_counter[3]_i_11_1 ; wire \bit_counter[3]_i_11_n_0 ; wire \bit_counter[3]_i_12_0 ; wire \bit_counter[3]_i_12_1 ; wire \bit_counter[3]_i_12_2 ; wire \bit_counter[3]_i_12_n_0 ; wire \bit_counter[3]_i_13_n_0 ; wire \bit_counter[3]_i_14_n_0 ; wire \bit_counter[3]_i_15_0 ; wire \bit_counter[3]_i_15_1 ; wire \bit_counter[3]_i_15_n_0 ; wire \bit_counter[3]_i_16_0 ; wire \bit_counter[3]_i_16_n_0 ; wire \bit_counter[3]_i_17_0 ; wire \bit_counter[3]_i_17_1 ; wire \bit_counter[3]_i_17_n_0 ; wire \bit_counter[3]_i_18_n_0 ; wire \bit_counter[3]_i_19_n_0 ; wire \bit_counter[3]_i_20_n_0 ; wire \bit_counter[3]_i_21_n_0 ; wire \bit_counter[3]_i_22_n_0 ; wire \bit_counter[3]_i_23_n_0 ; wire \bit_counter[3]_i_24_n_0 ; wire \bit_counter[3]_i_25_n_0 ; wire \bit_counter[3]_i_27_n_0 ; wire \bit_counter[3]_i_28_n_0 ; wire \bit_counter[3]_i_29_n_0 ; wire \bit_counter[3]_i_30_n_0 ; wire \bit_counter[3]_i_31_n_0 ; wire \bit_counter[3]_i_32_n_0 ; wire \bit_counter[3]_i_33_n_0 ; wire \bit_counter[3]_i_34_n_0 ; wire \bit_counter[3]_i_35_n_0 ; wire \bit_counter[3]_i_36_n_0 ; wire \bit_counter[3]_i_37_n_0 ; wire \bit_counter[3]_i_38_n_0 ; wire \bit_counter[3]_i_39_n_0 ; wire \bit_counter[3]_i_40_n_0 ; wire \bit_counter[3]_i_41_n_0 ; wire \bit_counter[3]_i_42_n_0 ; wire \bit_counter[3]_i_44_n_0 ; wire \bit_counter[3]_i_45_n_0 ; wire \bit_counter[3]_i_47_n_0 ; wire \bit_counter[3]_i_4_0 ; wire \bit_counter[3]_i_50_n_0 ; wire \bit_counter[3]_i_51_n_0 ; wire \bit_counter[3]_i_52_n_0 ; wire \bit_counter[3]_i_53_n_0 ; wire \bit_counter[3]_i_54_n_0 ; wire \bit_counter[3]_i_57_n_0 ; wire \bit_counter[3]_i_58_n_0 ; wire \bit_counter[3]_i_59_n_0 ; wire \bit_counter[3]_i_5_0 ; wire \bit_counter[3]_i_5_1 ; wire \bit_counter[3]_i_5_n_0 ; wire \bit_counter[3]_i_60_n_0 ; wire \bit_counter[3]_i_62_n_0 ; wire \bit_counter[3]_i_63_n_0 ; wire \bit_counter[3]_i_66_n_0 ; wire \bit_counter[3]_i_67_n_0 ; wire \bit_counter[3]_i_68_n_0 ; wire \bit_counter[3]_i_69_n_0 ; wire \bit_counter[3]_i_6_n_0 ; wire \bit_counter[3]_i_70_n_0 ; wire \bit_counter[3]_i_71_n_0 ; wire \bit_counter[3]_i_72_n_0 ; wire \bit_counter[3]_i_73_n_0 ; wire \bit_counter[3]_i_7_n_0 ; wire \bit_counter[3]_i_8_n_0 ; wire \bit_counter[3]_i_9_n_0 ; wire \br_inst_cnt_reg[0] ; wire \br_inst_cnt_reg[0]_0 ; wire buttons_pressed; wire \clock_counter_reg[0] ; wire cnt_reset; wire cpu_clk; wire cpu_clk_locked; wire \cycle_cnt[0]_i_10_n_0 ; wire \cycle_cnt[0]_i_3_n_0 ; wire \cycle_cnt[0]_i_4_n_0 ; wire \cycle_cnt[0]_i_5_n_0 ; wire \cycle_cnt[0]_i_6_n_0 ; wire \cycle_cnt[0]_i_7_n_0 ; wire \cycle_cnt[0]_i_9_n_0 ; wire [3:0]dmem_we; wire [31:0]dout; wire douta_reg_0_0; wire douta_reg_0_1; wire douta_reg_0_2; wire douta_reg_0_3; wire douta_reg_0_4; wire douta_reg_0_5; wire douta_reg_0_6; wire douta_reg_0_7; wire douta_reg_0_8; wire douta_reg_0_9; wire douta_reg_0_i_1_n_0; wire douta_reg_0_i_2_n_0; wire [19:0]douta_reg_1_0; wire douta_reg_1_1; wire [2:0]doutb; wire [14:2]doutb_reg; wire [30:0]ex_alu; wire \ex_wb_inst_reg[12] ; wire [2:0]\f_ex_imm_reg[16] ; wire \f_ex_imm_reg[4] ; wire \f_ex_imm_reg[4]_0 ; wire \f_ex_inst_reg[12] ; wire [1:0]\f_ex_inst_reg[2] ; wire [7:0]\f_ex_pc_reg[30] ; wire [17:0]\f_ex_pc_reg[30]_0 ; wire [29:0]fwd_a; wire [30:0]fwd_b; wire [3:0]imem_wea; wire [7:0]\ld/in ; wire [4:0]ld_data; wire mem_reg_0_0_i_101_n_0; wire mem_reg_0_0_i_104_n_0; wire mem_reg_0_0_i_104_n_1; wire mem_reg_0_0_i_104_n_2; wire mem_reg_0_0_i_104_n_3; wire mem_reg_0_0_i_105_n_0; wire mem_reg_0_0_i_107_n_0; wire mem_reg_0_0_i_108_n_0; wire mem_reg_0_0_i_109_n_0; wire mem_reg_0_0_i_110_n_0; wire mem_reg_0_0_i_113_n_0; wire mem_reg_0_0_i_114_n_0; wire mem_reg_0_0_i_115_n_0; wire mem_reg_0_0_i_116_n_0; wire mem_reg_0_0_i_117_n_0; wire mem_reg_0_0_i_120_n_0; wire mem_reg_0_0_i_121_n_0; wire mem_reg_0_0_i_122_n_0; wire mem_reg_0_0_i_123_n_0; wire mem_reg_0_0_i_124_n_0; wire mem_reg_0_0_i_127_n_0; wire mem_reg_0_0_i_128_n_0; wire mem_reg_0_0_i_129_n_0; wire mem_reg_0_0_i_129_n_1; wire mem_reg_0_0_i_129_n_2; wire mem_reg_0_0_i_129_n_3; wire mem_reg_0_0_i_130_n_0; wire mem_reg_0_0_i_131_n_0; wire mem_reg_0_0_i_132_n_0; wire mem_reg_0_0_i_135_n_0; wire mem_reg_0_0_i_136_n_0; wire mem_reg_0_0_i_137_n_0; wire mem_reg_0_0_i_138_n_0; wire mem_reg_0_0_i_140_n_0; wire mem_reg_0_0_i_141_n_0; wire mem_reg_0_0_i_143_n_0; wire mem_reg_0_0_i_144_n_0; wire mem_reg_0_0_i_145_n_0; wire mem_reg_0_0_i_146_n_0; wire mem_reg_0_0_i_147_n_0; wire mem_reg_0_0_i_150_n_0; wire mem_reg_0_0_i_151_n_0; wire mem_reg_0_0_i_152_n_0; wire mem_reg_0_0_i_153_n_0; wire mem_reg_0_0_i_155_n_0; wire mem_reg_0_0_i_157_n_0; wire mem_reg_0_0_i_158_n_0; wire mem_reg_0_0_i_159_n_0; wire mem_reg_0_0_i_160_n_0; wire mem_reg_0_0_i_161_n_0; wire mem_reg_0_0_i_162_n_0; wire mem_reg_0_0_i_164_n_0; wire mem_reg_0_0_i_166_n_0; wire mem_reg_0_0_i_167_n_0; wire mem_reg_0_0_i_167_n_1; wire mem_reg_0_0_i_167_n_2; wire mem_reg_0_0_i_167_n_3; wire mem_reg_0_0_i_168_n_0; wire mem_reg_0_0_i_169_n_0; wire mem_reg_0_0_i_170_n_0; wire mem_reg_0_0_i_171_n_0; wire mem_reg_0_0_i_172_n_0; wire mem_reg_0_0_i_173_n_0; wire mem_reg_0_0_i_175_n_0; wire mem_reg_0_0_i_176_n_0; wire mem_reg_0_0_i_177_n_0; wire mem_reg_0_0_i_178_n_0; wire mem_reg_0_0_i_179_n_0; wire mem_reg_0_0_i_180_n_0; wire mem_reg_0_0_i_182_n_0; wire mem_reg_0_0_i_183_n_0; wire mem_reg_0_0_i_184_n_0; wire mem_reg_0_0_i_185_n_0; wire mem_reg_0_0_i_18_n_0; wire mem_reg_0_0_i_190_n_0; wire mem_reg_0_0_i_191_n_0; wire mem_reg_0_0_i_192_n_0; wire mem_reg_0_0_i_193_n_0; wire mem_reg_0_0_i_195_n_0; wire mem_reg_0_0_i_196_n_0; wire mem_reg_0_0_i_197_n_0; wire mem_reg_0_0_i_198_n_0; wire mem_reg_0_0_i_199_n_0; wire mem_reg_0_0_i_19_n_0; wire mem_reg_0_0_i_201_n_0; wire mem_reg_0_0_i_202_n_0; wire mem_reg_0_0_i_202_n_1; wire mem_reg_0_0_i_202_n_2; wire mem_reg_0_0_i_202_n_3; wire mem_reg_0_0_i_203_n_0; wire mem_reg_0_0_i_204_n_0; wire mem_reg_0_0_i_205_n_0; wire mem_reg_0_0_i_206_n_0; wire mem_reg_0_0_i_20__0_n_0; wire mem_reg_0_0_i_211_n_0; wire mem_reg_0_0_i_212_n_0; wire mem_reg_0_0_i_213_n_0; wire mem_reg_0_0_i_214_n_0; wire mem_reg_0_0_i_215_n_0; wire mem_reg_0_0_i_216_n_0; wire mem_reg_0_0_i_217_n_0; wire mem_reg_0_0_i_218_n_0; wire mem_reg_0_0_i_220_n_0; wire mem_reg_0_0_i_221_n_0; wire mem_reg_0_0_i_222_n_0; wire mem_reg_0_0_i_223_n_0; wire mem_reg_0_0_i_224_0; wire mem_reg_0_0_i_224_1; wire mem_reg_0_0_i_227_0; wire mem_reg_0_0_i_227_1; wire mem_reg_0_0_i_22_n_0; wire mem_reg_0_0_i_230_n_0; wire mem_reg_0_0_i_231_n_0; wire mem_reg_0_0_i_232_n_0; wire mem_reg_0_0_i_233_n_0; wire mem_reg_0_0_i_234_n_0; wire mem_reg_0_0_i_235_n_0; wire mem_reg_0_0_i_236_n_0; wire mem_reg_0_0_i_237_n_0; wire mem_reg_0_0_i_239_n_0; wire mem_reg_0_0_i_23_n_0; wire mem_reg_0_0_i_240_n_0; wire mem_reg_0_0_i_241_n_0; wire mem_reg_0_0_i_245_n_0; wire mem_reg_0_0_i_246_n_0; wire mem_reg_0_0_i_247_n_0; wire mem_reg_0_0_i_248_n_0; wire mem_reg_0_0_i_249_n_0; wire mem_reg_0_0_i_24_n_0; wire mem_reg_0_0_i_250_n_0; wire mem_reg_0_0_i_251_n_0; wire mem_reg_0_0_i_252_n_0; wire mem_reg_0_0_i_253_n_0; wire mem_reg_0_0_i_254_n_0; wire mem_reg_0_0_i_257_n_0; wire mem_reg_0_0_i_258_n_0; wire mem_reg_0_0_i_259_n_0; wire mem_reg_0_0_i_25__0_n_0; wire mem_reg_0_0_i_260_n_0; wire mem_reg_0_0_i_261_n_0; wire mem_reg_0_0_i_262_n_0; wire mem_reg_0_0_i_263_n_0; wire mem_reg_0_0_i_264_n_0; wire mem_reg_0_0_i_265_n_0; wire mem_reg_0_0_i_266_n_0; wire mem_reg_0_0_i_267_n_0; wire mem_reg_0_0_i_269_n_0; wire mem_reg_0_0_i_270_n_0; wire mem_reg_0_0_i_271_n_0; wire mem_reg_0_0_i_272_n_0; wire mem_reg_0_0_i_273_n_0; wire mem_reg_0_0_i_274_n_0; wire mem_reg_0_0_i_275_n_0; wire mem_reg_0_0_i_277_n_0; wire mem_reg_0_0_i_278_n_0; wire mem_reg_0_0_i_279_n_0; wire mem_reg_0_0_i_27_n_0; wire mem_reg_0_0_i_280_n_0; wire mem_reg_0_0_i_281_n_0; wire mem_reg_0_0_i_282_n_0; wire mem_reg_0_0_i_283_n_0; wire mem_reg_0_0_i_285_n_0; wire mem_reg_0_0_i_286_n_0; wire mem_reg_0_0_i_287_n_0; wire mem_reg_0_0_i_289_n_0; wire mem_reg_0_0_i_28_n_0; wire mem_reg_0_0_i_290_n_0; wire mem_reg_0_0_i_293_n_0; wire mem_reg_0_0_i_294_n_0; wire mem_reg_0_0_i_295_n_0; wire mem_reg_0_0_i_296_n_0; wire mem_reg_0_0_i_297_n_0; wire mem_reg_0_0_i_298_n_0; wire mem_reg_0_0_i_299_n_0; wire mem_reg_0_0_i_29_n_0; wire mem_reg_0_0_i_300_n_0; wire mem_reg_0_0_i_305_n_0; wire mem_reg_0_0_i_306_n_0; wire mem_reg_0_0_i_307_n_0; wire mem_reg_0_0_i_308_n_0; wire mem_reg_0_0_i_309_n_0; wire mem_reg_0_0_i_30_n_0; wire mem_reg_0_0_i_310_n_0; wire mem_reg_0_0_i_315_n_0; wire mem_reg_0_0_i_316_n_0; wire mem_reg_0_0_i_31__0_n_0; wire mem_reg_0_0_i_321_n_0; wire mem_reg_0_0_i_325_n_0; wire mem_reg_0_0_i_331_n_0; wire mem_reg_0_0_i_33_n_0; wire mem_reg_0_0_i_34_n_0; wire mem_reg_0_0_i_35_n_0; wire mem_reg_0_0_i_36_n_0; wire mem_reg_0_0_i_37__0_n_0; wire mem_reg_0_0_i_39_n_0; wire mem_reg_0_0_i_40_n_0; wire mem_reg_0_0_i_41_n_0; wire mem_reg_0_0_i_42_n_0; wire mem_reg_0_0_i_43__0_n_0; wire mem_reg_0_0_i_45_n_0; wire mem_reg_0_0_i_46_n_0; wire mem_reg_0_0_i_48_n_0; wire mem_reg_0_0_i_49_n_0; wire mem_reg_0_0_i_50_n_0; wire mem_reg_0_0_i_51_n_0; wire mem_reg_0_0_i_52__0_n_0; wire mem_reg_0_0_i_53_n_0; wire mem_reg_0_0_i_54_n_0; wire mem_reg_0_0_i_56_n_0; wire mem_reg_0_0_i_56_n_1; wire mem_reg_0_0_i_56_n_2; wire mem_reg_0_0_i_56_n_3; wire mem_reg_0_0_i_58_n_0; wire mem_reg_0_0_i_59_n_0; wire mem_reg_0_0_i_60_n_0; wire mem_reg_0_0_i_61_n_0; wire mem_reg_0_0_i_62__0_n_0; wire mem_reg_0_0_i_63_n_0; wire mem_reg_0_0_i_65_n_0; wire mem_reg_0_0_i_67_n_0; wire mem_reg_0_0_i_68_n_0; wire mem_reg_0_0_i_70_n_0; wire mem_reg_0_0_i_72_n_0; wire mem_reg_0_0_i_73_n_0; wire mem_reg_0_0_i_74_n_0; wire mem_reg_0_0_i_75_n_0; wire mem_reg_0_0_i_75_n_1; wire mem_reg_0_0_i_75_n_2; wire mem_reg_0_0_i_75_n_3; wire mem_reg_0_0_i_76_n_0; wire mem_reg_0_0_i_77_n_0; wire mem_reg_0_0_i_79_n_0; wire mem_reg_0_0_i_80_n_0; wire mem_reg_0_0_i_81_n_0; wire mem_reg_0_0_i_82_n_0; wire mem_reg_0_0_i_83_n_0; wire mem_reg_0_0_i_83_n_1; wire mem_reg_0_0_i_83_n_2; wire mem_reg_0_0_i_83_n_3; wire mem_reg_0_0_i_84_n_0; wire mem_reg_0_0_i_85_n_0; wire mem_reg_0_0_i_86_n_0; wire mem_reg_0_0_i_87_n_0; wire mem_reg_0_0_i_88_n_0; wire mem_reg_0_0_i_90_n_0; wire mem_reg_0_0_i_91_n_0; wire mem_reg_0_0_i_95_n_0; wire mem_reg_0_0_i_96_n_0; wire mem_reg_0_0_i_96_n_1; wire mem_reg_0_0_i_96_n_2; wire mem_reg_0_0_i_96_n_3; wire mem_reg_0_0_i_97_n_0; wire mem_reg_0_0_i_99_n_0; wire mem_reg_0_1_i_10_n_0; wire mem_reg_0_1_i_5_0; wire mem_reg_0_1_i_5_1; wire mem_reg_0_1_i_7_0; wire mem_reg_0_1_i_7_1; wire mem_reg_0_1_i_9_n_0; wire mem_reg_0_2_i_7_0; wire mem_reg_0_2_i_7_1; wire mem_reg_0_2_i_9_n_0; wire mem_reg_1_0; wire mem_reg_1_0_0; wire mem_reg_1_0_1; wire mem_reg_1_0_2; wire mem_reg_1_0_3; wire mem_reg_1_0_i_4_n_0; wire mem_reg_1_0_i_6_n_0; wire mem_reg_1_0_i_8_n_0; wire mem_reg_1_1; wire mem_reg_1_1_0; wire mem_reg_1_1_1; wire mem_reg_1_1_2; wire mem_reg_1_2; wire mem_reg_1_2_0; wire mem_reg_1_2_1; wire mem_reg_1_2_2; wire mem_reg_1_3; wire mem_reg_1_3_0; wire mem_reg_1_3_1; wire mem_reg_1_3_2; wire mem_reg_1_3_3; wire [4:0]mem_reg_2_0; wire mem_reg_2_0_i_13_0; wire mem_reg_2_0_i_13_n_0; wire mem_reg_2_0_i_14_0; wire mem_reg_2_0_i_14_n_0; wire mem_reg_2_0_i_15_n_0; wire mem_reg_2_0_i_16_n_0; wire mem_reg_2_1_i_3_0; wire mem_reg_2_1_i_3_n_0; wire mem_reg_2_1_i_4_0; wire mem_reg_2_1_i_4_n_0; wire mem_reg_2_2; wire mem_reg_2_2_i_5_0; wire mem_reg_2_2_i_5_n_0; wire mem_reg_2_2_i_6_0; wire mem_reg_2_2_i_6_n_0; wire [0:0]mem_reg_2_3; wire mem_reg_2_3_i_3_0; wire mem_reg_2_3_i_3_n_0; wire mem_reg_2_3_i_4_0; wire mem_reg_2_3_i_4_n_0; wire mem_reg_3_0; wire mem_reg_3_0_0; wire mem_reg_3_0_1; wire mem_reg_3_0_i_6_n_0; wire mem_reg_3_0_i_7_n_0; wire mem_reg_3_0_i_9_n_0; wire mem_reg_3_1; wire mem_reg_3_1_0; wire mem_reg_3_2; wire mem_reg_3_2_0; wire [0:0]mem_reg_3_3; wire mem_reg_3_3_0; wire mem_reg_3_3_1; wire mem_reg_3_3_2; wire mem_reg_3_3_3; wire mem_reg_3_3_4; wire mem_reg_3_3_5; wire mem_reg_r1_0_31_0_5_i_22_0; wire mem_reg_r1_0_31_0_5_i_28_n_0; wire mem_reg_r1_0_31_0_5_i_31_n_0; wire mem_reg_r1_0_31_0_5_i_34_n_0; wire mem_reg_r1_0_31_0_5_i_37_n_0; wire mem_reg_r1_0_31_0_5_i_38_n_0; wire mem_reg_r1_0_31_0_5_i_41_n_0; wire mem_reg_r1_0_31_0_5_i_42_n_0; wire mem_reg_r1_0_31_0_5_i_45_n_0; wire mem_reg_r1_0_31_0_5_i_46_n_0; wire mem_reg_r1_0_31_0_5_i_49_n_0; wire mem_reg_r1_0_31_0_5_i_51_n_0; wire mem_reg_r1_0_31_0_5_i_54_n_0; wire mem_reg_r1_0_31_0_5_i_60_n_0; wire mem_reg_r1_0_31_0_5_i_62_n_0; wire mem_reg_r1_0_31_0_5_i_66_n_0; wire mem_reg_r1_0_31_0_5_i_68_n_0; wire mem_reg_r1_0_31_0_5_i_74_n_0; wire mem_reg_r1_0_31_0_5_i_76_n_0; wire mem_reg_r1_0_31_0_5_i_80_n_0; wire mem_reg_r1_0_31_0_5_i_82_n_0; wire mem_reg_r1_0_31_0_5_i_86_n_0; wire mem_reg_r1_0_31_0_5_i_88_n_0; wire mem_reg_r1_0_31_12_17_i_10_n_0; wire mem_reg_r1_0_31_12_17_i_11_0; wire mem_reg_r1_0_31_12_17_i_11_n_0; wire mem_reg_r1_0_31_12_17_i_14_n_0; wire mem_reg_r1_0_31_12_17_i_16_n_0; wire mem_reg_r1_0_31_12_17_i_17_0; wire mem_reg_r1_0_31_12_17_i_17_n_0; wire mem_reg_r1_0_31_12_17_i_19_0; wire mem_reg_r1_0_31_12_17_i_19_n_0; wire mem_reg_r1_0_31_12_17_i_21_0; wire mem_reg_r1_0_31_12_17_i_21_n_0; wire mem_reg_r1_0_31_12_17_i_23_n_0; wire mem_reg_r1_0_31_12_17_i_24_n_0; wire mem_reg_r1_0_31_12_17_i_26_n_0; wire mem_reg_r1_0_31_12_17_i_27_n_0; wire mem_reg_r1_0_31_12_17_i_29_n_0; wire mem_reg_r1_0_31_12_17_i_30_n_0; wire mem_reg_r1_0_31_12_17_i_31_n_0; wire mem_reg_r1_0_31_12_17_i_32_n_0; wire mem_reg_r1_0_31_12_17_i_7_n_0; wire mem_reg_r1_0_31_12_17_i_8_0; wire mem_reg_r1_0_31_12_17_i_8_n_0; wire mem_reg_r1_0_31_18_23_i_11_0; wire mem_reg_r1_0_31_18_23_i_11_n_0; wire mem_reg_r1_0_31_18_23_i_13_0; wire mem_reg_r1_0_31_18_23_i_13_n_0; wire mem_reg_r1_0_31_18_23_i_15_0; wire mem_reg_r1_0_31_18_23_i_15_1; wire mem_reg_r1_0_31_18_23_i_15_2; wire mem_reg_r1_0_31_18_23_i_15_n_0; wire mem_reg_r1_0_31_18_23_i_17_0; wire mem_reg_r1_0_31_18_23_i_17_n_0; wire mem_reg_r1_0_31_18_23_i_19_n_0; wire mem_reg_r1_0_31_18_23_i_20_n_0; wire mem_reg_r1_0_31_18_23_i_21_n_0; wire mem_reg_r1_0_31_18_23_i_23_n_0; wire mem_reg_r1_0_31_18_23_i_24_n_0; wire mem_reg_r1_0_31_18_23_i_25_n_0; wire mem_reg_r1_0_31_18_23_i_26_n_0; wire mem_reg_r1_0_31_18_23_i_7_0; wire mem_reg_r1_0_31_18_23_i_7_n_0; wire mem_reg_r1_0_31_18_23_i_9_0; wire mem_reg_r1_0_31_18_23_i_9_n_0; wire mem_reg_r1_0_31_24_29_i_11_n_0; wire mem_reg_r1_0_31_24_29_i_13_n_0; wire mem_reg_r1_0_31_24_29_i_15_n_0; wire mem_reg_r1_0_31_24_29_i_17_n_0; wire mem_reg_r1_0_31_24_29_i_7_n_0; wire mem_reg_r1_0_31_24_29_i_9_n_0; wire mem_reg_r1_0_31_6_11_i_11_n_0; wire mem_reg_r1_0_31_6_11_i_12_0; wire mem_reg_r1_0_31_6_11_i_12_n_0; wire mem_reg_r1_0_31_6_11_i_14_n_0; wire mem_reg_r1_0_31_6_11_i_15_0; wire mem_reg_r1_0_31_6_11_i_15_1; wire mem_reg_r1_0_31_6_11_i_15_n_0; wire mem_reg_r1_0_31_6_11_i_17_n_0; wire mem_reg_r1_0_31_6_11_i_18_0; wire mem_reg_r1_0_31_6_11_i_18_n_0; wire mem_reg_r1_0_31_6_11_i_20_n_0; wire mem_reg_r1_0_31_6_11_i_21_0; wire mem_reg_r1_0_31_6_11_i_21_n_0; wire [5:0]mem_reg_r1_0_31_6_11_i_23_0; wire mem_reg_r1_0_31_6_11_i_23_n_0; wire mem_reg_r1_0_31_6_11_i_26_n_0; wire mem_reg_r1_0_31_6_11_i_27_n_0; wire mem_reg_r1_0_31_6_11_i_30_n_0; wire mem_reg_r1_0_31_6_11_i_31_n_0; wire mem_reg_r1_0_31_6_11_i_33_n_0; wire mem_reg_r1_0_31_6_11_i_34_n_0; wire mem_reg_r1_0_31_6_11_i_35_n_0; wire mem_reg_r1_0_31_6_11_i_37_n_0; wire mem_reg_r1_0_31_6_11_i_39_n_0; wire mem_reg_r1_0_31_6_11_i_44_n_0; wire mem_reg_r1_0_31_6_11_i_46_n_0; wire mem_reg_r1_0_31_6_11_i_49_n_0; wire mem_reg_r1_0_31_6_11_i_50_n_0; wire mem_reg_r1_0_31_6_11_i_52_n_0; wire mem_reg_r1_0_31_6_11_i_53_n_0; wire mem_reg_r1_0_31_6_11_i_54_n_0; wire mem_reg_r1_0_31_6_11_i_9_0; wire [17:0]mem_wb_mux; wire [31:0]out; wire [31:0]p_1_in; wire [6:0]p_1_in_0; wire \pprev_data[30]_i_2_n_0 ; wire \pprev_data[31]_i_2 ; wire \pprev_data_reg[0] ; wire \pprev_data_reg[0]_0 ; wire [2:0]\pprev_data_reg[0]_1 ; wire \pprev_data_reg[10] ; wire \pprev_data_reg[11] ; wire \pprev_data_reg[12] ; wire \pprev_data_reg[13] ; wire \pprev_data_reg[14] ; wire \pprev_data_reg[15] ; wire \pprev_data_reg[16] ; wire \pprev_data_reg[17] ; wire \pprev_data_reg[18] ; wire \pprev_data_reg[19] ; wire \pprev_data_reg[1] ; wire \pprev_data_reg[20] ; wire \pprev_data_reg[21] ; wire \pprev_data_reg[22] ; wire \pprev_data_reg[23] ; wire \pprev_data_reg[24] ; wire \pprev_data_reg[25] ; wire \pprev_data_reg[26] ; wire \pprev_data_reg[27] ; wire \pprev_data_reg[28] ; wire \pprev_data_reg[29] ; wire \pprev_data_reg[2] ; wire \pprev_data_reg[2]_0 ; wire \pprev_data_reg[30] ; wire \pprev_data_reg[3] ; wire \pprev_data_reg[3]_0 ; wire \pprev_data_reg[4] ; wire \pprev_data_reg[4]_0 ; wire \pprev_data_reg[5] ; wire \pprev_data_reg[5]_0 ; wire \pprev_data_reg[6] ; wire \pprev_data_reg[6]_0 ; wire \pprev_data_reg[7] ; wire \pprev_data_reg[7]_0 ; wire \pprev_data_reg[8] ; wire \pprev_data_reg[9] ; wire [10:0]sel; wire start; wire symbol_edge__7; wire tx_running__2; wire [6:0]tx_shift; wire \tx_shift_reg[8] ; wire wb_BrEq_i_10_n_0; wire wb_BrEq_i_11_n_0; wire wb_BrEq_i_13_0; wire wb_BrEq_i_13_1; wire wb_BrEq_i_13_n_0; wire wb_BrEq_i_14_0; wire wb_BrEq_i_14_n_0; wire wb_BrEq_i_15_0; wire wb_BrEq_i_15_1; wire wb_BrEq_i_15_n_0; wire wb_BrEq_i_16_0; wire wb_BrEq_i_16_n_0; wire wb_BrEq_i_25_n_0; wire wb_BrEq_i_26_n_0; wire wb_BrEq_i_27_n_0; wire wb_BrEq_i_28_n_0; wire wb_BrEq_i_29_0; wire wb_BrEq_i_29_1; wire wb_BrEq_i_29_n_0; wire wb_BrEq_i_30_0; wire wb_BrEq_i_30_n_0; wire wb_BrEq_i_31_0; wire wb_BrEq_i_31_1; wire wb_BrEq_i_31_n_0; wire wb_BrEq_i_32_0; wire wb_BrEq_i_32_n_0; wire wb_BrEq_i_45_n_0; wire wb_BrEq_i_46_n_0; wire wb_BrEq_i_47_n_0; wire wb_BrEq_i_48_n_0; wire wb_BrEq_i_5_n_0; wire wb_BrEq_i_6_0; wire wb_BrEq_i_6_1; wire wb_BrEq_i_6_n_0; wire [0:0]wb_BrEq_i_7_0; wire wb_BrEq_i_7_1; wire wb_BrEq_i_7_n_0; wire wb_BrEq_i_9_n_0; wire wb_BrEq_reg_i_12_n_0; wire wb_BrEq_reg_i_12_n_1; wire wb_BrEq_reg_i_12_n_2; wire wb_BrEq_reg_i_12_n_3; wire wb_BrEq_reg_i_24_n_0; wire wb_BrEq_reg_i_24_n_1; wire wb_BrEq_reg_i_24_n_2; wire wb_BrEq_reg_i_24_n_3; wire wb_BrEq_reg_i_2_n_2; wire wb_BrEq_reg_i_2_n_3; wire wb_BrEq_reg_i_3_n_2; wire wb_BrEq_reg_i_3_n_3; wire wb_BrEq_reg_i_4_n_0; wire wb_BrEq_reg_i_4_n_1; wire wb_BrEq_reg_i_4_n_2; wire wb_BrEq_reg_i_4_n_3; wire wb_BrEq_reg_i_8_n_0; wire wb_BrEq_reg_i_8_n_1; wire wb_BrEq_reg_i_8_n_2; wire wb_BrEq_reg_i_8_n_3; wire wb_BrLt_i_10_n_0; wire wb_BrLt_i_11_n_0; wire wb_BrLt_i_12_n_0; wire wb_BrLt_i_15_n_0; wire wb_BrLt_i_16_n_0; wire wb_BrLt_i_17_n_0; wire wb_BrLt_i_18_n_0; wire wb_BrLt_i_19_n_0; wire wb_BrLt_i_20_n_0; wire wb_BrLt_i_21_n_0; wire wb_BrLt_i_23_n_0; wire wb_BrLt_i_24_0; wire wb_BrLt_i_24_n_0; wire wb_BrLt_i_25_0; wire wb_BrLt_i_25_1; wire wb_BrLt_i_25_n_0; wire wb_BrLt_i_26_n_0; wire wb_BrLt_i_27_n_0; wire wb_BrLt_i_28_n_0; wire wb_BrLt_i_29_n_0; wire wb_BrLt_i_30_n_0; wire wb_BrLt_i_34_n_0; wire wb_BrLt_i_35_n_0; wire wb_BrLt_i_36_n_0; wire wb_BrLt_i_37_n_0; wire wb_BrLt_i_38_n_0; wire wb_BrLt_i_39_n_0; wire wb_BrLt_i_40_n_0; wire wb_BrLt_i_41_n_0; wire wb_BrLt_i_43_0; wire wb_BrLt_i_43_n_0; wire wb_BrLt_i_44_0; wire wb_BrLt_i_44_1; wire wb_BrLt_i_44_n_0; wire wb_BrLt_i_45_n_0; wire wb_BrLt_i_46_0; wire wb_BrLt_i_46_n_0; wire wb_BrLt_i_47_n_0; wire wb_BrLt_i_48_n_0; wire wb_BrLt_i_49_n_0; wire wb_BrLt_i_50_n_0; wire wb_BrLt_i_52_n_0; wire wb_BrLt_i_53_n_0; wire wb_BrLt_i_54_n_0; wire wb_BrLt_i_55_n_0; wire wb_BrLt_i_56_n_0; wire wb_BrLt_i_57_n_0; wire wb_BrLt_i_58_n_0; wire wb_BrLt_i_59_n_0; wire wb_BrLt_i_60_0; wire wb_BrLt_i_60_1; wire wb_BrLt_i_60_n_0; wire wb_BrLt_i_61_n_0; wire wb_BrLt_i_62_0; wire wb_BrLt_i_62_n_0; wire wb_BrLt_i_63_0; wire wb_BrLt_i_63_1; wire wb_BrLt_i_63_n_0; wire wb_BrLt_i_64_n_0; wire wb_BrLt_i_65_n_0; wire wb_BrLt_i_66_n_0; wire wb_BrLt_i_67_n_0; wire wb_BrLt_i_68_n_0; wire wb_BrLt_i_69_n_0; wire wb_BrLt_i_6_n_0; wire wb_BrLt_i_70_n_0; wire wb_BrLt_i_71_n_0; wire wb_BrLt_i_72_n_0; wire wb_BrLt_i_73_n_0; wire wb_BrLt_i_74_n_0; wire wb_BrLt_i_75_n_0; wire wb_BrLt_i_7_0; wire wb_BrLt_i_7_n_0; wire wb_BrLt_i_8_0; wire wb_BrLt_i_8_1; wire wb_BrLt_i_8_n_0; wire wb_BrLt_i_9_n_0; wire [0:0]wb_BrLt_reg; wire wb_BrLt_reg_i_13_n_0; wire wb_BrLt_reg_i_13_n_1; wire wb_BrLt_reg_i_13_n_2; wire wb_BrLt_reg_i_13_n_3; wire wb_BrLt_reg_i_22_n_0; wire wb_BrLt_reg_i_22_n_1; wire wb_BrLt_reg_i_22_n_2; wire wb_BrLt_reg_i_22_n_3; wire wb_BrLt_reg_i_2_0; wire wb_BrLt_reg_i_2_1; wire wb_BrLt_reg_i_2_2; wire wb_BrLt_reg_i_2_n_0; wire wb_BrLt_reg_i_2_n_1; wire wb_BrLt_reg_i_2_n_2; wire wb_BrLt_reg_i_2_n_3; wire wb_BrLt_reg_i_33_n_0; wire wb_BrLt_reg_i_33_n_1; wire wb_BrLt_reg_i_33_n_2; wire wb_BrLt_reg_i_33_n_3; wire wb_BrLt_reg_i_3_0; wire wb_BrLt_reg_i_3_n_0; wire wb_BrLt_reg_i_3_n_1; wire wb_BrLt_reg_i_3_n_2; wire wb_BrLt_reg_i_3_n_3; wire wb_BrLt_reg_i_42_n_0; wire wb_BrLt_reg_i_42_n_1; wire wb_BrLt_reg_i_42_n_2; wire wb_BrLt_reg_i_42_n_3; wire wb_BrLt_reg_i_4_n_0; wire wb_BrLt_reg_i_4_n_1; wire wb_BrLt_reg_i_4_n_2; wire wb_BrLt_reg_i_4_n_3; wire wb_BrLt_reg_i_51_n_0; wire wb_BrLt_reg_i_51_n_1; wire wb_BrLt_reg_i_51_n_2; wire wb_BrLt_reg_i_51_n_3; wire \wb_alu[0]_i_10_n_0 ; wire \wb_alu[0]_i_11_n_0 ; wire \wb_alu[0]_i_12_n_0 ; wire \wb_alu[0]_i_13_n_0 ; wire \wb_alu[0]_i_14_n_0 ; wire \wb_alu[0]_i_15_n_0 ; wire \wb_alu[0]_i_16_n_0 ; wire \wb_alu[0]_i_20_n_0 ; wire \wb_alu[0]_i_21_n_0 ; wire \wb_alu[0]_i_22_n_0 ; wire \wb_alu[0]_i_23_n_0 ; wire \wb_alu[0]_i_24_n_0 ; wire \wb_alu[0]_i_25_n_0 ; wire \wb_alu[0]_i_26_n_0 ; wire \wb_alu[0]_i_27_n_0 ; wire \wb_alu[0]_i_29_n_0 ; wire \wb_alu[0]_i_2_n_0 ; wire \wb_alu[0]_i_30_n_0 ; wire \wb_alu[0]_i_31_n_0 ; wire \wb_alu[0]_i_32_n_0 ; wire \wb_alu[0]_i_33_n_0 ; wire \wb_alu[0]_i_34_n_0 ; wire \wb_alu[0]_i_35_n_0 ; wire \wb_alu[0]_i_36_n_0 ; wire \wb_alu[0]_i_38_n_0 ; wire \wb_alu[0]_i_39_n_0 ; wire \wb_alu[0]_i_3_n_0 ; wire \wb_alu[0]_i_40_n_0 ; wire \wb_alu[0]_i_41_n_0 ; wire \wb_alu[0]_i_42_n_0 ; wire \wb_alu[0]_i_43_n_0 ; wire \wb_alu[0]_i_44_n_0 ; wire \wb_alu[0]_i_45_n_0 ; wire \wb_alu[0]_i_47_n_0 ; wire \wb_alu[0]_i_48_n_0 ; wire \wb_alu[0]_i_49_n_0 ; wire \wb_alu[0]_i_4_n_0 ; wire \wb_alu[0]_i_50_n_0 ; wire \wb_alu[0]_i_52_n_0 ; wire \wb_alu[0]_i_53_n_0 ; wire \wb_alu[0]_i_54_n_0 ; wire \wb_alu[0]_i_55_n_0 ; wire \wb_alu[0]_i_56_n_0 ; wire \wb_alu[0]_i_57_n_0 ; wire \wb_alu[0]_i_58_n_0 ; wire \wb_alu[0]_i_59_n_0 ; wire \wb_alu[0]_i_5_n_0 ; wire \wb_alu[0]_i_61_n_0 ; wire \wb_alu[0]_i_62_n_0 ; wire \wb_alu[0]_i_63_n_0 ; wire \wb_alu[0]_i_64_n_0 ; wire \wb_alu[0]_i_65_n_0 ; wire \wb_alu[0]_i_66_n_0 ; wire \wb_alu[0]_i_67_n_0 ; wire \wb_alu[0]_i_68_n_0 ; wire \wb_alu[0]_i_69_n_0 ; wire \wb_alu[0]_i_6_n_0 ; wire \wb_alu[0]_i_70_n_0 ; wire \wb_alu[0]_i_71_n_0 ; wire \wb_alu[0]_i_72_n_0 ; wire \wb_alu[0]_i_73_n_0 ; wire \wb_alu[0]_i_74_n_0 ; wire \wb_alu[0]_i_75_n_0 ; wire \wb_alu[0]_i_76_n_0 ; wire \wb_alu[0]_i_77_n_0 ; wire \wb_alu[0]_i_78_n_0 ; wire \wb_alu[0]_i_79_n_0 ; wire \wb_alu[0]_i_7_n_0 ; wire \wb_alu[0]_i_80_n_0 ; wire \wb_alu[0]_i_8_n_0 ; wire \wb_alu[0]_i_9_n_0 ; wire \wb_alu[16]_i_2_n_0 ; wire \wb_alu[16]_i_3_n_0 ; wire \wb_alu[16]_i_5_n_0 ; wire \wb_alu[16]_i_6_n_0 ; wire \wb_alu[16]_i_7_n_0 ; wire \wb_alu[16]_i_8_n_0 ; wire \wb_alu[16]_i_9_n_0 ; wire \wb_alu[17]_i_10_n_0 ; wire \wb_alu[17]_i_11_n_0 ; wire \wb_alu[17]_i_12_n_0 ; wire \wb_alu[17]_i_2_n_0 ; wire \wb_alu[17]_i_3_n_0 ; wire \wb_alu[17]_i_4_n_0 ; wire \wb_alu[17]_i_5_n_0 ; wire \wb_alu[17]_i_7_n_0 ; wire \wb_alu[17]_i_8_n_0 ; wire \wb_alu[17]_i_9_n_0 ; wire \wb_alu[18]_i_2_n_0 ; wire \wb_alu[18]_i_3_n_0 ; wire \wb_alu[18]_i_4_n_0 ; wire \wb_alu[18]_i_5_n_0 ; wire \wb_alu[18]_i_7_n_0 ; wire \wb_alu[18]_i_8_n_0 ; wire \wb_alu[18]_i_9_n_0 ; wire \wb_alu[19]_i_11_n_0 ; wire \wb_alu[19]_i_12_n_0 ; wire \wb_alu[19]_i_13_n_0 ; wire \wb_alu[19]_i_14_n_0 ; wire \wb_alu[19]_i_15_n_0 ; wire \wb_alu[19]_i_16_n_0 ; wire \wb_alu[19]_i_17_n_0 ; wire \wb_alu[19]_i_18_n_0 ; wire \wb_alu[19]_i_19_n_0 ; wire \wb_alu[19]_i_25_n_0 ; wire \wb_alu[19]_i_26_n_0 ; wire \wb_alu[19]_i_27_n_0 ; wire \wb_alu[19]_i_28_n_0 ; wire \wb_alu[19]_i_2_n_0 ; wire \wb_alu[19]_i_4_n_0 ; wire \wb_alu[19]_i_5_n_0 ; wire \wb_alu[1]_i_11_n_0 ; wire \wb_alu[1]_i_2_n_0 ; wire \wb_alu[1]_i_3_n_0 ; wire \wb_alu[1]_i_4_n_0 ; wire \wb_alu[1]_i_5_n_0 ; wire \wb_alu[1]_i_6_n_0 ; wire \wb_alu[1]_i_7_n_0 ; wire \wb_alu[1]_i_8_n_0 ; wire \wb_alu[1]_i_9_n_0 ; wire \wb_alu[20]_i_2_n_0 ; wire \wb_alu[20]_i_3_n_0 ; wire \wb_alu[20]_i_4_0 ; wire \wb_alu[20]_i_4_n_0 ; wire \wb_alu[20]_i_6_n_0 ; wire \wb_alu[20]_i_7_n_0 ; wire \wb_alu[20]_i_8_n_0 ; wire \wb_alu[20]_i_9_n_0 ; wire \wb_alu[21]_i_2_n_0 ; wire \wb_alu[21]_i_3_0 ; wire \wb_alu[21]_i_3_n_0 ; wire \wb_alu[21]_i_5_n_0 ; wire \wb_alu[21]_i_6_n_0 ; wire \wb_alu[21]_i_7_n_0 ; wire \wb_alu[21]_i_8_n_0 ; wire \wb_alu[22]_i_2_n_0 ; wire \wb_alu[22]_i_3_0 ; wire \wb_alu[22]_i_3_n_0 ; wire \wb_alu[22]_i_4_n_0 ; wire \wb_alu[22]_i_6_n_0 ; wire \wb_alu[22]_i_7_n_0 ; wire \wb_alu[22]_i_8_n_0 ; wire \wb_alu[22]_i_9_n_0 ; wire \wb_alu[23]_i_11_n_0 ; wire \wb_alu[23]_i_12_n_0 ; wire \wb_alu[23]_i_13_n_0 ; wire \wb_alu[23]_i_14_n_0 ; wire \wb_alu[23]_i_15_n_0 ; wire \wb_alu[23]_i_16_n_0 ; wire \wb_alu[23]_i_17_n_0 ; wire \wb_alu[23]_i_18_n_0 ; wire \wb_alu[23]_i_2_n_0 ; wire \wb_alu[23]_i_4_0 ; wire \wb_alu[23]_i_4_n_0 ; wire \wb_alu[23]_i_5_n_0 ; wire \wb_alu[24]_i_2_n_0 ; wire \wb_alu[24]_i_3_n_0 ; wire \wb_alu[24]_i_4_n_0 ; wire \wb_alu[24]_i_6_n_0 ; wire \wb_alu[24]_i_7_n_0 ; wire \wb_alu[25]_i_2_n_0 ; wire \wb_alu[25]_i_3_n_0 ; wire \wb_alu[25]_i_4_n_0 ; wire \wb_alu[25]_i_6_n_0 ; wire \wb_alu[25]_i_7_n_0 ; wire \wb_alu[25]_i_8_n_0 ; wire \wb_alu[26]_i_2_n_0 ; wire \wb_alu[26]_i_3_n_0 ; wire \wb_alu[26]_i_4_n_0 ; wire \wb_alu[26]_i_6_n_0 ; wire \wb_alu[26]_i_7_n_0 ; wire \wb_alu[26]_i_8_n_0 ; wire \wb_alu[27]_i_10_n_0 ; wire \wb_alu[27]_i_11_n_0 ; wire \wb_alu[27]_i_12_n_0 ; wire \wb_alu[27]_i_13_n_0 ; wire \wb_alu[27]_i_15_n_0 ; wire \wb_alu[27]_i_16_n_0 ; wire \wb_alu[27]_i_17_n_0 ; wire \wb_alu[27]_i_3_n_0 ; wire \wb_alu[27]_i_4_n_0 ; wire \wb_alu[27]_i_5_n_0 ; wire \wb_alu[28]_i_10_n_0 ; wire \wb_alu[28]_i_11_n_0 ; wire \wb_alu[28]_i_12_n_0 ; wire \wb_alu[28]_i_13_n_0 ; wire \wb_alu[28]_i_14_n_0 ; wire \wb_alu[28]_i_15_n_0 ; wire \wb_alu[28]_i_2_n_0 ; wire \wb_alu[28]_i_3_n_0 ; wire \wb_alu[28]_i_4_n_0 ; wire \wb_alu[28]_i_5_n_0 ; wire [0:0]\wb_alu[28]_i_6 ; wire \wb_alu[28]_i_7_n_0 ; wire \wb_alu[28]_i_8_n_0 ; wire \wb_alu[28]_i_9_n_0 ; wire \wb_alu[29]_i_10_n_0 ; wire \wb_alu[29]_i_15_n_0 ; wire \wb_alu[29]_i_16_n_0 ; wire \wb_alu[29]_i_17_n_0 ; wire \wb_alu[29]_i_18_n_0 ; wire \wb_alu[29]_i_19_n_0 ; wire \wb_alu[29]_i_21_n_0 ; wire \wb_alu[29]_i_22_n_0 ; wire \wb_alu[29]_i_23_n_0 ; wire \wb_alu[29]_i_24_n_0 ; wire \wb_alu[29]_i_28_n_0 ; wire \wb_alu[29]_i_29_n_0 ; wire \wb_alu[29]_i_2_n_0 ; wire \wb_alu[29]_i_30_n_0 ; wire \wb_alu[29]_i_31_n_0 ; wire \wb_alu[29]_i_32_n_0 ; wire \wb_alu[29]_i_33_n_0 ; wire \wb_alu[29]_i_34_n_0 ; wire \wb_alu[29]_i_35_n_0 ; wire \wb_alu[29]_i_36_n_0 ; wire \wb_alu[29]_i_3_n_0 ; wire \wb_alu[29]_i_6_n_0 ; wire \wb_alu[29]_i_7_n_0 ; wire \wb_alu[29]_i_9_n_0 ; wire \wb_alu[30]_i_10_n_0 ; wire \wb_alu[30]_i_11_n_0 ; wire \wb_alu[30]_i_13_n_0 ; wire \wb_alu[30]_i_14_n_0 ; wire \wb_alu[30]_i_2_n_0 ; wire \wb_alu[30]_i_3_n_0 ; wire \wb_alu[30]_i_4_n_0 ; wire \wb_alu[30]_i_5_n_0 ; wire \wb_alu[30]_i_7_n_0 ; wire \wb_alu[30]_i_8_n_0 ; wire \wb_alu[30]_i_9_n_0 ; wire \wb_alu[31]_i_10_n_0 ; wire \wb_alu[31]_i_11_n_0 ; wire \wb_alu[31]_i_12_n_0 ; wire \wb_alu[31]_i_16_n_0 ; wire \wb_alu[31]_i_17_n_0 ; wire \wb_alu[31]_i_18_n_0 ; wire \wb_alu[31]_i_19_n_0 ; wire \wb_alu[31]_i_20_n_0 ; wire \wb_alu[31]_i_9_n_0 ; wire \wb_alu_reg[0] ; wire \wb_alu_reg[0]_i_17_n_1 ; wire \wb_alu_reg[0]_i_17_n_2 ; wire \wb_alu_reg[0]_i_17_n_3 ; wire [0:0]\wb_alu_reg[0]_i_18_0 ; wire [0:0]\wb_alu_reg[0]_i_18_1 ; wire \wb_alu_reg[0]_i_18_n_1 ; wire \wb_alu_reg[0]_i_18_n_2 ; wire \wb_alu_reg[0]_i_18_n_3 ; wire \wb_alu_reg[0]_i_19_n_0 ; wire \wb_alu_reg[0]_i_19_n_1 ; wire \wb_alu_reg[0]_i_19_n_2 ; wire \wb_alu_reg[0]_i_19_n_3 ; wire \wb_alu_reg[0]_i_28_n_0 ; wire \wb_alu_reg[0]_i_28_n_1 ; wire \wb_alu_reg[0]_i_28_n_2 ; wire \wb_alu_reg[0]_i_28_n_3 ; wire \wb_alu_reg[0]_i_37_n_0 ; wire \wb_alu_reg[0]_i_37_n_1 ; wire \wb_alu_reg[0]_i_37_n_2 ; wire \wb_alu_reg[0]_i_37_n_3 ; wire \wb_alu_reg[0]_i_46_n_0 ; wire \wb_alu_reg[0]_i_46_n_1 ; wire \wb_alu_reg[0]_i_46_n_2 ; wire \wb_alu_reg[0]_i_46_n_3 ; wire \wb_alu_reg[0]_i_51_n_0 ; wire \wb_alu_reg[0]_i_51_n_1 ; wire \wb_alu_reg[0]_i_51_n_2 ; wire \wb_alu_reg[0]_i_51_n_3 ; wire \wb_alu_reg[0]_i_60_n_0 ; wire \wb_alu_reg[0]_i_60_n_1 ; wire \wb_alu_reg[0]_i_60_n_2 ; wire \wb_alu_reg[0]_i_60_n_3 ; wire \wb_alu_reg[16] ; wire \wb_alu_reg[19]_i_24_n_0 ; wire \wb_alu_reg[19]_i_24_n_1 ; wire \wb_alu_reg[19]_i_24_n_2 ; wire \wb_alu_reg[19]_i_24_n_3 ; wire \wb_alu_reg[19]_i_3_n_0 ; wire \wb_alu_reg[19]_i_3_n_1 ; wire \wb_alu_reg[19]_i_3_n_2 ; wire \wb_alu_reg[19]_i_3_n_3 ; wire \wb_alu_reg[1] ; wire \wb_alu_reg[22] ; wire \wb_alu_reg[23]_i_3_n_0 ; wire \wb_alu_reg[23]_i_3_n_1 ; wire \wb_alu_reg[23]_i_3_n_2 ; wire \wb_alu_reg[23]_i_3_n_3 ; wire \wb_alu_reg[27]_i_2_n_0 ; wire \wb_alu_reg[27]_i_2_n_1 ; wire \wb_alu_reg[27]_i_2_n_2 ; wire \wb_alu_reg[27]_i_2_n_3 ; wire \wb_alu_reg[28] ; wire \wb_alu_reg[29] ; wire \wb_alu_reg[29]_0 ; wire \wb_alu_reg[29]_i_11_n_0 ; wire \wb_alu_reg[29]_i_11_n_1 ; wire \wb_alu_reg[29]_i_11_n_2 ; wire \wb_alu_reg[29]_i_11_n_3 ; wire \wb_alu_reg[29]_i_20_n_0 ; wire \wb_alu_reg[29]_i_20_n_1 ; wire \wb_alu_reg[29]_i_20_n_2 ; wire \wb_alu_reg[29]_i_20_n_3 ; wire [30:0]\wb_alu_reg[29]_i_5_0 ; wire \wb_alu_reg[29]_i_5_n_1 ; wire \wb_alu_reg[29]_i_5_n_2 ; wire \wb_alu_reg[29]_i_5_n_3 ; wire \wb_alu_reg[31]_i_8_n_1 ; wire \wb_alu_reg[31]_i_8_n_2 ; wire \wb_alu_reg[31]_i_8_n_3 ; wire [30:0]wb_mux; GND GND (.G(\<const0> )); VCC VCC (.P(\<const1> )); LUT6 #( .INIT(64'hF0F0D0FFFFFFD0FF)) \bit_counter[3]_i_11 (.I0(\bit_counter[3]_i_19_n_0 ), .I1(\bit_counter[3]_i_20_n_0 ), .I2(\wb_alu[29]_i_2_n_0 ), .I3(\bit_counter[3]_i_21_n_0 ), .I4(ALUSel[3]), .I5(\bit_counter[3]_i_5_0 ), .O(\bit_counter[3]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFD0FFD0D0D0D0)) \bit_counter[3]_i_12 (.I0(\wb_alu[25]_i_4_n_0 ), .I1(\bit_counter[3]_i_22_n_0 ), .I2(\bit_counter[3]_i_23_n_0 ), .I3(\wb_alu[24]_i_4_n_0 ), .I4(\bit_counter[3]_i_24_n_0 ), .I5(\bit_counter[3]_i_25_n_0 ), .O(\bit_counter[3]_i_12_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFDDD0)) \bit_counter[3]_i_13 (.I0(\wb_alu[1]_i_4_n_0 ), .I1(\bit_counter[3]_i_5_1 ), .I2(\wb_alu[1]_i_3_n_0 ), .I3(\wb_alu[1]_i_2_n_0 ), .I4(\wb_alu[0]_i_5_n_0 ), .I5(\bit_counter[3]_i_27_n_0 ), .O(\bit_counter[3]_i_13_n_0 )); LUT6 #( .INIT(64'hFFFFD0FFD0D0D0D0)) \bit_counter[3]_i_14 (.I0(\bit_counter[3]_i_28_n_0 ), .I1(\wb_alu[28]_i_3_n_0 ), .I2(\wb_alu[28]_i_2_n_0 ), .I3(mem_reg_0_0_i_67_n_0), .I4(douta_reg_0_4), .I5(\bit_counter[3]_i_29_n_0 ), .O(\bit_counter[3]_i_14_n_0 )); LUT6 #( .INIT(64'hFFFFFFD0F0F0FFD0)) \bit_counter[3]_i_15 (.I0(\wb_alu[26]_i_4_n_0 ), .I1(\wb_alu[26]_i_3_n_0 ), .I2(\bit_counter[3]_i_30_n_0 ), .I3(\bit_counter[3]_i_31_n_0 ), .I4(ALUSel[3]), .I5(\wb_alu[30]_i_2_n_0 ), .O(\bit_counter[3]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFD0FFD0D0D0D0)) \bit_counter[3]_i_16 (.I0(\wb_alu[27]_i_5_n_0 ), .I1(\bit_counter[3]_i_32_n_0 ), .I2(\bit_counter[3]_i_33_n_0 ), .I3(mem_reg_0_0_i_72_n_0), .I4(douta_reg_0_8), .I5(\bit_counter[3]_i_34_n_0 ), .O(\bit_counter[3]_i_16_n_0 )); LUT6 #( .INIT(64'hFFEFFFEFFFEFEEEE)) \bit_counter[3]_i_17 (.I0(\bit_counter[3]_i_35_n_0 ), .I1(\bit_counter[3]_i_36_n_0 ), .I2(mem_reg_0_0_i_22_n_0), .I3(mem_reg_3_3_2), .I4(\bit_counter[3]_i_37_n_0 ), .I5(mem_reg_0_0_i_18_n_0), .O(\bit_counter[3]_i_17_n_0 )); LUT6 #( .INIT(64'h54FF54FF54FF5454)) \bit_counter[3]_i_18 (.I0(\bit_counter[3]_i_38_n_0 ), .I1(\bit_counter[3]_i_39_n_0 ), .I2(mem_reg_0_0_i_29_n_0), .I3(\bit_counter[3]_i_40_n_0 ), .I4(\bit_counter[3]_i_41_n_0 ), .I5(mem_reg_0_0_i_41_n_0), .O(\bit_counter[3]_i_18_n_0 )); LUT6 #( .INIT(64'h575757F7F7F757F7)) \bit_counter[3]_i_19 (.I0(\wb_alu_reg[29] ), .I1(\alu/data0 [29]), .I2(ALUSel[0]), .I3(\bit_counter[3]_i_42_n_0 ), .I4(\f_ex_imm_reg[16] [1]), .I5(mem_reg_0_0_i_114_n_0), .O(\bit_counter[3]_i_19_n_0 )); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT4 #( .INIT(16'h888A)) \bit_counter[3]_i_20 (.I0(ALUSel[2]), .I1(\wb_alu[29]_i_10_n_0 ), .I2(mem_reg_0_0_i_168_n_0), .I3(\wb_alu[29]_i_9_n_0 ), .O(\bit_counter[3]_i_20_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF40554555)) \bit_counter[3]_i_21 (.I0(\bit_counter[3]_i_11_0 ), .I1(mem_reg_0_0_i_95_n_0), .I2(\f_ex_imm_reg[16] [1]), .I3(ALUSel[0]), .I4(\bit_counter[3]_i_44_n_0 ), .I5(\bit_counter[3]_i_11_1 ), .O(\bit_counter[3]_i_21_n_0 )); LUT6 #( .INIT(64'hFFFFAABAAAAAAAAA)) \bit_counter[3]_i_22 (.I0(ALUSel[3]), .I1(\f_ex_imm_reg[16] [0]), .I2(\wb_alu[25]_i_7_n_0 ), .I3(mem_reg_0_0_i_168_n_0), .I4(\wb_alu[25]_i_6_n_0 ), .I5(ALUSel[2]), .O(\bit_counter[3]_i_22_n_0 )); LUT5 #( .INIT(32'hFFFF4544)) \bit_counter[3]_i_23 (.I0(\bit_counter[3]_i_45_n_0 ), .I1(\wb_alu_reg[22] ), .I2(\f_ex_imm_reg[16] [1]), .I3(mem_reg_0_0_i_155_n_0), .I4(\bit_counter[3]_i_12_2 ), .O(\bit_counter[3]_i_23_n_0 )); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT5 #( .INIT(32'hFFABAAAA)) \bit_counter[3]_i_24 (.I0(ALUSel[3]), .I1(mem_reg_0_0_i_158_n_0), .I2(mem_reg_0_0_i_168_n_0), .I3(\wb_alu[24]_i_6_n_0 ), .I4(ALUSel[2]), .O(\bit_counter[3]_i_24_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF44454545)) \bit_counter[3]_i_25 (.I0(\bit_counter[3]_i_47_n_0 ), .I1(\wb_alu_reg[22] ), .I2(\f_ex_imm_reg[16] [1]), .I3(\bit_counter[3]_i_12_0 ), .I4(mem_reg_0_0_i_158_n_0), .I5(\bit_counter[3]_i_12_1 ), .O(\bit_counter[3]_i_25_n_0 )); LUT6 #( .INIT(64'h000000008A008000)) \bit_counter[3]_i_27 (.I0(ALUSel[2]), .I1(\wb_alu[0]_i_4_n_0 ), .I2(\f_ex_imm_reg[16] [1]), .I3(ALUSel[0]), .I4(\bit_counter[3]_i_50_n_0 ), .I5(ALUSel[1]), .O(\bit_counter[3]_i_27_n_0 )); LUT6 #( .INIT(64'h575757F7F7F757F7)) \bit_counter[3]_i_28 (.I0(\wb_alu_reg[29] ), .I1(\alu/data0 [28]), .I2(ALUSel[0]), .I3(\bit_counter[3]_i_51_n_0 ), .I4(\f_ex_imm_reg[16] [1]), .I5(mem_reg_0_0_i_121_n_0), .O(\bit_counter[3]_i_28_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFDDFD0000)) \bit_counter[3]_i_29 (.I0(\bit_counter[3]_i_52_n_0 ), .I1(mem_reg_0_0_i_170_n_0), .I2(mem_reg_0_0_i_169_n_0), .I3(mem_reg_0_0_i_168_n_0), .I4(ALUSel[2]), .I5(\bit_counter[3]_i_53_n_0 ), .O(\bit_counter[3]_i_29_n_0 )); LUT5 #( .INIT(32'hFFFF4544)) \bit_counter[3]_i_30 (.I0(\bit_counter[3]_i_54_n_0 ), .I1(\wb_alu_reg[22] ), .I2(\f_ex_imm_reg[16] [1]), .I3(mem_reg_0_0_i_136_n_0), .I4(\bit_counter[3]_i_15_1 ), .O(\bit_counter[3]_i_30_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF45454500)) \bit_counter[3]_i_31 (.I0(\bit_counter[3]_i_15_0 ), .I1(mem_reg_0_0_i_107_n_0), .I2(\wb_alu[0]_i_3_n_0 ), .I3(\bit_counter[3]_i_57_n_0 ), .I4(\bit_counter[3]_i_58_n_0 ), .I5(\bit_counter[3]_i_59_n_0 ), .O(\bit_counter[3]_i_31_n_0 )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT5 #( .INIT(32'hFFABAAAA)) \bit_counter[3]_i_32 (.I0(ALUSel[3]), .I1(\wb_alu[27]_i_16_n_0 ), .I2(mem_reg_0_0_i_168_n_0), .I3(\wb_alu[27]_i_15_n_0 ), .I4(ALUSel[2]), .O(\bit_counter[3]_i_32_n_0 )); LUT5 #( .INIT(32'hFFFF4445)) \bit_counter[3]_i_33 (.I0(\bit_counter[3]_i_60_n_0 ), .I1(\wb_alu_reg[22] ), .I2(mem_reg_0_0_i_135_n_0), .I3(\f_ex_imm_reg[16] [1]), .I4(\bit_counter[3]_i_16_0 ), .O(\bit_counter[3]_i_33_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFDDFD0000)) \bit_counter[3]_i_34 (.I0(\bit_counter[3]_i_62_n_0 ), .I1(mem_reg_0_0_i_178_n_0), .I2(mem_reg_0_0_i_177_n_0), .I3(mem_reg_0_0_i_168_n_0), .I4(ALUSel[2]), .I5(\bit_counter[3]_i_63_n_0 ), .O(\bit_counter[3]_i_34_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFF020000)) \bit_counter[3]_i_35 (.I0(\wb_alu[0]_i_4_n_0 ), .I1(\f_ex_imm_reg[16] [1]), .I2(ALUSel[1]), .I3(\bit_counter[3]_i_17_1 ), .I4(\wb_alu_reg[16] ), .I5(\wb_alu[16]_i_3_n_0 ), .O(\bit_counter[3]_i_35_n_0 )); LUT6 #( .INIT(64'h00000000AAAAFEAE)) \bit_counter[3]_i_36 (.I0(\wb_alu[16]_i_8_n_0 ), .I1(\wb_alu[16]_i_7_n_0 ), .I2(\f_ex_imm_reg[16] [0]), .I3(\wb_alu[16]_i_6_n_0 ), .I4(\wb_alu[31]_i_9_n_0 ), .I5(\bit_counter[3]_i_17_0 ), .O(\bit_counter[3]_i_36_n_0 )); LUT6 #( .INIT(64'h00000000FF70FF40)) \bit_counter[3]_i_37 (.I0(mem_reg_0_0_i_241_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(ALUSel[0]), .I3(\bit_counter[3]_i_66_n_0 ), .I4(\bit_counter[3]_i_67_n_0 ), .I5(mem_reg_0_0_i_20__0_n_0), .O(\bit_counter[3]_i_37_n_0 )); LUT6 #( .INIT(64'h00000000AAAAFBAB)) \bit_counter[3]_i_38 (.I0(mem_reg_0_0_i_34_n_0), .I1(\bit_counter[3]_i_68_n_0 ), .I2(\f_ex_imm_reg[16] [1]), .I3(mem_reg_0_0_i_120_n_0), .I4(ALUSel[1]), .I5(mem_reg_3_3_1), .O(\bit_counter[3]_i_38_n_0 )); LUT6 #( .INIT(64'h00000000FF70FF40)) \bit_counter[3]_i_39 (.I0(\wb_alu[29]_i_9_n_0 ), .I1(\f_ex_imm_reg[16] [1]), .I2(ALUSel[0]), .I3(\bit_counter[3]_i_69_n_0 ), .I4(\bit_counter[3]_i_68_n_0 ), .I5(mem_reg_0_0_i_31__0_n_0), .O(\bit_counter[3]_i_39_n_0 )); LUT6 #( .INIT(64'h0000000000000010)) \bit_counter[3]_i_4 (.I0(\bit_counter[3]_i_5_n_0 ), .I1(\bit_counter[3]_i_6_n_0 ), .I2(\bit_counter[3]_i_7_n_0 ), .I3(\bit_counter[3]_i_8_n_0 ), .I4(\bit_counter[3]_i_9_n_0 ), .I5(tx_running__2), .O(start)); LUT6 #( .INIT(64'h00000000AAAAFBAB)) \bit_counter[3]_i_40 (.I0(mem_reg_0_0_i_46_n_0), .I1(\bit_counter[3]_i_70_n_0 ), .I2(\f_ex_imm_reg[16] [1]), .I3(mem_reg_0_0_i_135_n_0), .I4(ALUSel[1]), .I5(douta_reg_0_5), .O(\bit_counter[3]_i_40_n_0 )); LUT6 #( .INIT(64'h00000000FF70FF40)) \bit_counter[3]_i_41 (.I0(\wb_alu[27]_i_16_n_0 ), .I1(\f_ex_imm_reg[16] [1]), .I2(ALUSel[0]), .I3(mem_reg_0_0_i_283_n_0), .I4(\bit_counter[3]_i_70_n_0 ), .I5(mem_reg_0_0_i_43__0_n_0), .O(\bit_counter[3]_i_41_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \bit_counter[3]_i_42 (.I0(\wb_alu[29]_i_28_n_0 ), .I1(\wb_alu[29]_i_29_n_0 ), .I2(\f_ex_imm_reg[16] [0]), .I3(\wb_alu[29]_i_30_n_0 ), .I4(b_mux[2]), .I5(\bit_counter[3]_i_71_n_0 ), .O(\bit_counter[3]_i_42_n_0 )); LUT6 #( .INIT(64'h0F000FFF55335533)) \bit_counter[3]_i_44 (.I0(\wb_alu[31]_i_12_n_0 ), .I1(\wb_alu[31]_i_11_n_0 ), .I2(\wb_alu[31]_i_19_n_0 ), .I3(b_mux[2]), .I4(\wb_alu[31]_i_20_n_0 ), .I5(\f_ex_imm_reg[16] [0]), .O(\bit_counter[3]_i_44_n_0 )); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT3 #( .INIT(8'h5D)) \bit_counter[3]_i_45 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[25]), .O(\bit_counter[3]_i_45_n_0 )); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT3 #( .INIT(8'h5D)) \bit_counter[3]_i_47 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[24]), .O(\bit_counter[3]_i_47_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \bit_counter[3]_i_5 (.I0(\bit_counter[3]_i_11_n_0 ), .I1(\bit_counter[3]_i_12_n_0 ), .I2(\bit_counter[3]_i_13_n_0 ), .I3(\bit_counter[3]_i_14_n_0 ), .I4(\bit_counter[3]_i_15_n_0 ), .I5(\bit_counter[3]_i_16_n_0 ), .O(\bit_counter[3]_i_5_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \bit_counter[3]_i_50 (.I0(mem_reg_0_0_i_274_n_0), .I1(mem_reg_0_0_i_293_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(\wb_alu[0]_i_7_n_0 ), .I4(b_mux[2]), .I5(\wb_alu[0]_i_6_n_0 ), .O(\bit_counter[3]_i_50_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \bit_counter[3]_i_51 (.I0(\wb_alu[28]_i_11_n_0 ), .I1(\wb_alu[28]_i_12_n_0 ), .I2(\f_ex_imm_reg[16] [0]), .I3(\wb_alu[28]_i_13_n_0 ), .I4(b_mux[2]), .I5(\bit_counter[3]_i_72_n_0 ), .O(\bit_counter[3]_i_51_n_0 )); LUT6 #( .INIT(64'hCC1DFF1DFFFFFFFF)) \bit_counter[3]_i_52 (.I0(mem_reg_0_0_i_240_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_239_n_0), .I3(\f_ex_imm_reg[16] [0]), .I4(mem_reg_0_0_i_282_n_0), .I5(mem_reg_0_0_i_172_n_0), .O(\bit_counter[3]_i_52_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00005404)) \bit_counter[3]_i_53 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_164_n_0), .I2(b_mux[2]), .I3(mem_reg_0_0_i_166_n_0), .I4(\f_ex_imm_reg[16] [0]), .I5(douta_reg_0_3), .O(\bit_counter[3]_i_53_n_0 )); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT3 #( .INIT(8'h5D)) \bit_counter[3]_i_54 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[26]), .O(\bit_counter[3]_i_54_n_0 )); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT4 #( .INIT(16'hE200)) \bit_counter[3]_i_57 (.I0(\wb_alu[30]_i_14_n_0 ), .I1(b_mux[2]), .I2(\wb_alu[30]_i_13_n_0 ), .I3(\f_ex_imm_reg[16] [0]), .O(\bit_counter[3]_i_57_n_0 )); LUT6 #( .INIT(64'hDFDDDFDFDFDDDDDD)) \bit_counter[3]_i_58 (.I0(ALUSel[0]), .I1(\f_ex_imm_reg[16] [1]), .I2(\f_ex_imm_reg[16] [0]), .I3(\wb_alu[30]_i_10_n_0 ), .I4(b_mux[2]), .I5(\wb_alu[30]_i_9_n_0 ), .O(\bit_counter[3]_i_58_n_0 )); LUT5 #( .INIT(32'h888888A8)) \bit_counter[3]_i_59 (.I0(ALUSel[2]), .I1(\bit_counter[3]_i_73_n_0 ), .I2(\wb_alu[22]_i_9_n_0 ), .I3(\f_ex_imm_reg[16] [0]), .I4(mem_reg_0_0_i_168_n_0), .O(\bit_counter[3]_i_59_n_0 )); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT3 #( .INIT(8'hFB)) \bit_counter[3]_i_6 (.I0(ADDRARDADDR[2]), .I1(ex_alu[3]), .I2(ex_alu[2]), .O(\bit_counter[3]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT3 #( .INIT(8'h5D)) \bit_counter[3]_i_60 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[27]), .O(\bit_counter[3]_i_60_n_0 )); LUT6 #( .INIT(64'hCC1DFF1DFFFFFFFF)) \bit_counter[3]_i_62 (.I0(mem_reg_0_0_i_254_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_253_n_0), .I3(\f_ex_imm_reg[16] [0]), .I4(mem_reg_0_0_i_285_n_0), .I5(mem_reg_0_0_i_172_n_0), .O(\bit_counter[3]_i_62_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00005404)) \bit_counter[3]_i_63 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_175_n_0), .I2(b_mux[2]), .I3(mem_reg_0_0_i_176_n_0), .I4(\f_ex_imm_reg[16] [0]), .I5(douta_reg_0_7), .O(\bit_counter[3]_i_63_n_0 )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT4 #( .INIT(16'hAABE)) \bit_counter[3]_i_66 (.I0(ALUSel[1]), .I1(b_mux[15]), .I2(a_mux[15]), .I3(ALUSel[0]), .O(\bit_counter[3]_i_66_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \bit_counter[3]_i_67 (.I0(mem_reg_0_0_i_239_n_0), .I1(mem_reg_0_0_i_240_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_236_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_237_n_0), .O(\bit_counter[3]_i_67_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \bit_counter[3]_i_68 (.I0(mem_reg_0_0_i_263_n_0), .I1(mem_reg_0_0_i_264_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_261_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_262_n_0), .O(\bit_counter[3]_i_68_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAABFBFEAE)) \bit_counter[3]_i_69 (.I0(ALUSel[1]), .I1(fwd_b[13]), .I2(BSel), .I3(Q[13]), .I4(a_mux[13]), .I5(ALUSel[0]), .O(\bit_counter[3]_i_69_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \bit_counter[3]_i_7 (.I0(ADDRARDADDR[10]), .I1(ex_alu[14]), .I2(ex_alu[22]), .I3(ex_alu[23]), .I4(ADDRARDADDR[3]), .I5(ex_alu[21]), .O(\bit_counter[3]_i_7_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \bit_counter[3]_i_70 (.I0(mem_reg_0_0_i_240_n_0), .I1(mem_reg_0_0_i_236_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_237_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_281_n_0), .O(\bit_counter[3]_i_70_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \bit_counter[3]_i_71 (.I0(a_mux[26]), .I1(a_mux[27]), .I2(b_mux[1]), .I3(a_mux[28]), .I4(b_mux[0]), .I5(a_mux[29]), .O(\bit_counter[3]_i_71_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \bit_counter[3]_i_72 (.I0(a_mux[25]), .I1(a_mux[26]), .I2(b_mux[1]), .I3(a_mux[27]), .I4(b_mux[0]), .I5(a_mux[28]), .O(\bit_counter[3]_i_72_n_0 )); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT4 #( .INIT(16'hD414)) \bit_counter[3]_i_73 (.I0(ALUSel[0]), .I1(b_mux[30]), .I2(a_mux[30]), .I3(ALUSel[1]), .O(\bit_counter[3]_i_73_n_0 )); LUT5 #( .INIT(32'hFFFFFFFD)) \bit_counter[3]_i_8 (.I0(\bit_counter[3]_i_4_0 ), .I1(ex_alu[18]), .I2(ADDRARDADDR[6]), .I3(mem_reg_2_0[1]), .I4(ADDRARDADDR[7]), .O(\bit_counter[3]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \bit_counter[3]_i_9 (.I0(ex_alu[20]), .I1(ex_alu[17]), .I2(\bit_counter[3]_i_17_n_0 ), .I3(ex_alu[19]), .I4(ADDRARDADDR[8]), .I5(\bit_counter[3]_i_18_n_0 ), .O(\bit_counter[3]_i_9_n_0 )); LUT6 #( .INIT(64'h0A000A00CECE0E00)) \br_inst_cnt[0]_i_3 (.I0(out[5]), .I1(doutb[1]), .I2(\br_inst_cnt_reg[0] ), .I3(out[1]), .I4(doutb[0]), .I5(\br_inst_cnt_reg[0]_0 ), .O(douta_reg_0_1)); LUT4 #( .INIT(16'hFFFB)) \clock_counter[8]_i_1 (.I0(buttons_pressed), .I1(cpu_clk_locked), .I2(start), .I3(symbol_edge__7), .O(SR)); LUT6 #( .INIT(64'h0000000000000020)) \cycle_cnt[0]_i_1 (.I0(\cycle_cnt[0]_i_3_n_0 ), .I1(\cycle_cnt[0]_i_4_n_0 ), .I2(ex_alu[4]), .I3(\cycle_cnt[0]_i_5_n_0 ), .I4(\cycle_cnt[0]_i_6_n_0 ), .I5(\cycle_cnt[0]_i_7_n_0 ), .O(cnt_reset)); LUT4 #( .INIT(16'hFFFE)) \cycle_cnt[0]_i_10 (.I0(ADDRARDADDR[9]), .I1(ADDRARDADDR[11]), .I2(ADDRARDADDR[8]), .I3(ex_alu[19]), .O(\cycle_cnt[0]_i_10_n_0 )); LUT4 #( .INIT(16'h0002)) \cycle_cnt[0]_i_3 (.I0(\bit_counter[3]_i_7_n_0 ), .I1(\bit_counter[3]_i_8_n_0 ), .I2(\cycle_cnt[0]_i_9_n_0 ), .I3(\cycle_cnt[0]_i_10_n_0 ), .O(\cycle_cnt[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT2 #( .INIT(4'hB)) \cycle_cnt[0]_i_4 (.I0(ex_alu[2]), .I1(ex_alu[3]), .O(\cycle_cnt[0]_i_4_n_0 )); LUT4 #( .INIT(16'hFFEF)) \cycle_cnt[0]_i_5 (.I0(ex_alu[24]), .I1(ex_alu[25]), .I2(mem_reg_2_3), .I3(ex_alu[29]), .O(\cycle_cnt[0]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT4 #( .INIT(16'hFFFE)) \cycle_cnt[0]_i_6 (.I0(ex_alu[0]), .I1(ex_alu[1]), .I2(ADDRARDADDR[5]), .I3(ex_alu[28]), .O(\cycle_cnt[0]_i_6_n_0 )); LUT4 #( .INIT(16'hFFFE)) \cycle_cnt[0]_i_7 (.I0(ex_alu[30]), .I1(ex_alu[26]), .I2(ADDRARDADDR[4]), .I3(ex_alu[27]), .O(\cycle_cnt[0]_i_7_n_0 )); LUT4 #( .INIT(16'hFFFE)) \cycle_cnt[0]_i_9 (.I0(ex_alu[15]), .I1(ex_alu[16]), .I2(ex_alu[17]), .I3(ex_alu[20]), .O(\cycle_cnt[0]_i_9_n_0 )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "65536" *) (* RTL_RAM_NAME = "bios_mem/douta" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "2047" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "15" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h10EF04B327832703006F26232C232E230413222324232623011300EF01130137), .INIT_01(256'h2403208385132783802307B3278327036AE32783270326238793278380230793), .INIT_02(256'h470303A3079310EF006F26232A232C232E230413242326230113806701132483), .INIT_03(256'h05131517262387932783802307B327832703006F10EF05139863278312630793), .INIT_04(256'h006F2783802307B3278327031E634703C78307B327832703006F2423006F10EF), .INIT_05(256'h2623879327838023470307B3278327039AE3C78307B327832703242387932783), .INIT_06(256'h2E230113806701132403208385132783802307B327038793278364E327832703), .INIT_07(256'h222307B32783971327832423F0EF851305930793006F26232423262304132C23), .INIT_08(256'h2403208300130013E6E3270397932783262387932783A0232783071300EF2503), .INIT_09(256'h059306131617079300EF0513151700EF0513151704132C232E23011380670113), .INIT_0A(256'h0793F0EF851305930613161707939263079300EF2503859315972623F0EF8513), .INIT_0B(256'hF0EF25032583202300EF85130793F0EF85130593061316170793222300EF8513), .INIT_0C(256'h00EF85130793F0EF851305930613161707939063079300EF250385931597F06F), .INIT_0D(256'h05930613161707939C63079300EF250385931597F06F80E72783242327832623), .INIT_0E(256'h00EF8513079300EF2503859306130793282327832A2300EF85130793F0EF8513), .INIT_0F(256'h00EF0513151700EF8513079300EF8513059306130713A783278300EF05131517), .INIT_10(256'h00EF85130793F0EF851305930613161707939063079300EF250385931597F06F), .INIT_11(256'hD783278300EF0513151700EF8513079300EF25038593061307932C2327832E23), .INIT_12(256'h85931597F06F00EF0513151700EF8513079300EF8513059306130713D7939793), .INIT_13(256'h20232783222300EF85130793F0EF851305930613161707939E63079300EF2503), .INIT_14(256'h06130713F793C783278300EF0513151700EF8513079300EF2503859306130793), .INIT_15(256'h9663079300EF250385931597F06F00EF0513151700EF8513079300EF85130593), .INIT_16(256'hF0EF85130593061316170793282300EF85130793F0EF85130593061316170793), .INIT_17(256'h9863079300EF250385931597F06FA0232703278324232783262300EF85130793), .INIT_18(256'h851305930613161707931F23079300EF85130793F0EF85130593061316170793), .INIT_19(256'h079300EF250385931597F06F9023570327832A2327832C2300EF85130793F0EF), .INIT_1A(256'h059306131617079305A3079300EF85130793F0EF851305930613161707939863), .INIT_1B(256'h250300EF05131517F06F80234703278320232783222300EF85130793F0EF8513), .INIT_1C(256'hC70307B327832703006F242307A32E23041326230113F06F00EF0513151700EF), .INIT_1D(256'hF71307B3F79397934783F71397934783E2630793C70307B327832703FE630793), .INIT_1E(256'h27832703EC630793270324238793278307A38793F79307B3C78387B327832683), .INIT_1F(256'h2703006F242317232E230413262301138067011324038513478394E3C78307B3), .INIT_20(256'h57835713971397935783EE630793C70307B327832703FA630793C70307B32783), .INIT_21(256'h8793D793979307B3D7939793C78387B3278326835713971307B3D79397939793), .INIT_22(256'h011324038513578398E3C78307B327832703EC63079327032423879327831723), .INIT_23(256'h27832703F6630793C70307B327832703006F242326232E230413262301138067), .INIT_24(256'h2623879387B3470387332703268307B39793278397132783EA630793C70307B3), .INIT_25(256'h806701132403851327839CE3C78307B327832703EC6307932703242387932783), .INIT_26(256'h07B327034783F4630793C70307B327034783006F072307A32E23041326230113), .INIT_27(256'h2703478307A38793F79307B3C78387B326834783F71397934783E8630793C703), .INIT_28(256'h87B326834783F71397934783E8630793C70307B327034783F4630793C70307B3), .INIT_29(256'h0793C70307B327034783F4630793C70307B32703478307A38793F79307B3C783), .INIT_2A(256'h470307238793478307A38793F79307B3C78387B326834783F71397934783E863), .INIT_2B(256'h2E230413262301138067011324038513478392E3C78307B327034783EC630793), .INIT_2C(256'h5783E0630793C70307B327035783FC630793C70307B327035783006F16231723), .INIT_2D(256'h2703578317238793D793979307B3D7939793C78387B326835783571397139793), .INIT_2E(256'h268357835713971397935783E0630793C70307B327035783FC630793C70307B3), .INIT_2F(256'h5783FC630793C70307B32703578317238793D793979307B3D7939793C78387B3), .INIT_30(256'h07B3D7939793C78387B3268357835713971397935783E0630793C70307B32703), .INIT_31(256'h57839AE3C78307B327035783EC630793570316238793578317238793D7939793), .INIT_32(256'h0793C70307B327832703006F242326232E230413262301138067011324038513), .INIT_33(256'h2623879387B3470387332703268397932783E4630793C70307B327832703F063), .INIT_34(256'h2703268397932783E4630793C70307B327832703F0630793C70307B327832703), .INIT_35(256'h0793C70307B327832703F0630793C70307B3278327032623879387B347038733), .INIT_36(256'hEC63079327032423879327832623879387B3470387332703268397932783E463), .INIT_37(256'h2A232C230793041326230113806701132403851327839EE3C78307B327832703), .INIT_38(256'h470303A3F793F79357B39793879387B3278326834703006F2423079326230FA3), .INIT_39(256'h2703E06307934703F66307934703802377130713470307B327832703E0630793), .INIT_3A(256'hECE32703879327837A6327832703262387932783802377130713470307B32783), .INIT_3B(256'h1F232A232C23079304132623011380670113240385132783802307B327832703), .INIT_3C(256'h0793470303A3F793F79357B39793879387B3278326835703006F242307932623), .INIT_3D(256'h27832703E06307934703F66307934703802377130713470307B327832703E063), .INIT_3E(256'h2703ECE32703879327837A6327832703262387932783802377130713470307B3), .INIT_3F(256'h079326232A232C232E2304132623011380670113240385132783802307B32783), .INIT_40(256'h2703E0630793470303A3F793F79357B327039793879307B327832703006F2423), .INIT_41(256'h470307B327832703E06307934703F66307934703802377130713470307B32783), .INIT_42(256'h07B327832703ECE32703879327837A6327832703262387932783802377130713), .INIT_43(256'h8AE3F793A78307B7001307A3079304132E230113806701132403851327838023), .INIT_44(256'h2783006F26232E2304132423262301138067011324030013A0234703879307B7), .INIT_45(256'h20830013001396E3C78307B327032783262387932783F0EF8513C78307B32703), .INIT_46(256'h07A3A783879307B78AE3F793A78307B7001304132C232E230113806701132403), .INIT_47(256'h806701132403208385134783F0EF85134783006FF0EF051305171A6307934703), .INIT_48(256'h011324038513478307A3A783879307B78AE3F793A78307B7001304132E230113), .INIT_49(256'h0663C78387B327832683C70307B32783270326232C232E230413262301138067), .INIT_4A(256'h01132403851307930013F06F2623879327838A63C78307B327832703006F0793), .INIT_4B(256'h278392E3C78307B327832703262387932783006F26232E230413262301138067), .INIT_4C(256'h626C686C003A776C616A000069660D20002035310A0D08208067011324038513), .INIT_4D(256'h000000000000000000000A0D0D0A203A6B6F64656E6765720D0A627368737773), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(18), .READ_WIDTH_B(18), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(18), .WRITE_WIDTH_B(0)) douta_reg_0 (.ADDRARDADDR({\<const1> ,sel,\<const0> ,\<const0> ,\<const0> ,\<const0> }), .ADDRBWRADDR({\<const1> ,ex_alu[12:4],douta_reg_0_i_1_n_0,douta_reg_0_i_2_n_0,\<const0> ,\<const0> ,\<const0> ,\<const0> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(out[15:0]), .DOBDO({douta_reg_1_0[3],doutb_reg[14:8],douta_reg_1_0[2],doutb_reg[6:2],douta_reg_1_0[1:0]}), .ENARDEN(\<const1> ), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'h0E00EEEEEEEEEEEE)) douta_reg_0_i_1 (.I0(mem_reg_0_0_i_81_n_0), .I1(mem_reg_0_0_i_82_n_0), .I2(douta_reg_0_2), .I3(\alu/data8 [3]), .I4(ALUSel[3]), .I5(mem_reg_0_0_i_84_n_0), .O(douta_reg_0_i_1_n_0)); LUT6 #( .INIT(64'h88888888A8AAA8A8)) douta_reg_0_i_2 (.I0(mem_reg_0_0_i_85_n_0), .I1(mem_reg_0_0_i_86_n_0), .I2(mem_reg_0_0_i_87_n_0), .I3(mem_reg_0_0_i_88_n_0), .I4(ALUSel[0]), .I5(mem_reg_0_0_i_90_n_0), .O(douta_reg_0_i_2_n_0)); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "65536" *) (* RTL_RAM_NAME = "bios_mem/douta" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "2047" *) (* ram_offset = "0" *) (* ram_slice_begin = "16" *) (* ram_slice_end = "31" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h150000F7FEC4FDC40280FE04FCB4FCA40301029102810211FD012400FF011001), .INIT_01(256'h028102C10007FDC4000700F7FD84FDC4FCF7FD84FEC4FEF40017FEC400F40005), .INIT_02(256'hFE74FEF400050DC00D40FE04FCC4FCB4FCA4030102810211FD01000003010241), .INIT_03(256'h21850000FEF4FFF7FEC4000700F7FEC4FDC40A80004002000007FEC404F70080), .INIT_04(256'h0680FDC4000700F7FEC4FDC400F7FE74000700F7FE84FD440400FE0407C00200), .INIT_05(256'hFEF40017FEC400E7FE7400F7FEC4FDC4FA07000700F7FE84FD44FEF40017FE84), .INIT_06(256'h0211FC0100000301028102C10007FDC4000700F7FDC4FFF7FD84F2F7FD84FEC4), .INIT_07(256'hFEF400F7FCC40027FEC4FEA4E29F00070080FD8404C0FE04FCB4FCA404010281), .INIT_08(256'h038103C100000000FAE7FC840027FEC4FEF40017FEC400E7FE44000528D0FE84), .INIT_09(256'h08000AC60000F2046B500B4500006C100BC500000E010C810C11F20100000401), .INIT_0A(256'h0005DD5F0007080007860000F204060700057AD0FEC409850000FEA4E09F0007), .INIT_0B(256'hEBDFFA44FA04FAA45D8000070005DADF0007080005060000F204FAA41CD00007), .INIT_0C(256'h155000070005D5DF0007080000060000F204040700057350FEC402850000F65F), .INIT_0D(256'h0800FAC60000F204080700056E10FEC4FD850000F11F0007FA84FAF4FAC4FAA4), .INIT_0E(256'h5650000700054310FB4400070800F204FAF4FB44FAA4101000070005D09F0007), .INIT_0F(256'h5250F20500005310000700053FD0000700070800F2040007FB045590F7450000), .INIT_10(256'h055000070005C5DF00070800F0060000F2040A0700056350FEC4F3450000E65F), .INIT_11(256'h0007FB844AD0EC8500004B90000700053850FBC400070800F204FAF4FBC4FAA4), .INIT_12(256'hE8450000DB1F4710E6C5000047D00007000524D0000700070800F20401070107), .INIT_13(256'hFCF4FC44FCA47A0000070005BA9F00070800E4C60000F204080700055810FEC4), .INIT_14(256'h0800F2040FF70007FC043F90E14500004050000700052D10FC4400070800F204), .INIT_15(256'h060700054D10FEC4DD850000D01F3C10DBC500003CD0000700050A1000070007), .INIT_16(256'hAD1F00070800D7460000F204FCA46F0000070005AF9F00070800D9C60000F204), .INIT_17(256'h060700054510FEC4D5C50000C81F00E7FD04FC84FCF4FCC4FCA46C8000070005), .INIT_18(256'h00070800CF060000F204FCF400054D0000070005A79F00070800D1C60000F204), .INIT_19(256'h00053CD0FEC4CDC50000BFDF00E7FDE4FD44FCF4FD84FCA4644000070005A4DF), .INIT_1A(256'h0800C6C60000F204FEF400052DC0000700059F5F00070800C9860000F2040607), .INIT_1B(256'hFEC42290C5C50000B79F00E7FEB4FE04FEF4FE44FEA45C00000700059C9F0007), .INIT_1C(256'h000700F7FE84FDC40800FE04FE04FCA403010281FD01B55F2150C60500002210), .INIT_1D(256'h0FF700F70FF70017FEF40FF70037FEF404E70390000700F7FE84FDC404E702F0), .INIT_1E(256'hFE84FDC400E70020FE84FEF40017FE84FEF4FD070FF700F7000700F6FE84FDC4), .INIT_1F(256'hFDC40980FE04FE04FCA403010281FD010000030102C10007FEF4F607000700F7), .INIT_20(256'hFEE4010701070037FEE404E70390000700F7FE84FDC406E702F0000700F7FE84), .INIT_21(256'hFD070107010700F701070107000700F6FE84FDC40107010700F7010701070017), .INIT_22(256'h030102C10007FEE4F407000700F7FE84FDC400E70040FE84FEF40017FE84FEF4), .INIT_23(256'hFE84FDC404E702F0000700F7FE84FDC40700FE04FE04FCA403010281FD010000), .INIT_24(256'hFEF4FD0700E7000700E6FE84FDC400F70017FEC40037FEC402E70390000700F7), .INIT_25(256'h0000030102C10007FEC4F607000700F7FE84FDC400E70080FE84FEF40017FE84), .INIT_26(256'h00F7FDC4FEE404E702F0000700F7FDC4FEE41240FE04FE04FCA403010281FD01), .INIT_27(256'hFDC4FEE4FEF4FD070FF700F7000700F6FDC4FEE40FF70047FEF402E703900007), .INIT_28(256'h00F6FDC4FEE40FF70047FEF402E70660000700F7FDC4FEE404E70600000700F7), .INIT_29(256'h0460000700F7FDC4FEE404E70400000700F7FDC4FEE4FEF4FA970FF700F70007), .INIT_2A(256'hFEE4FEF40017FEE4FEF4FC970FF700F7000700F6FDC4FEE40FF70047FEF402E7), .INIT_2B(256'hFCA403010281FD010000030102C10007FEF4EC07000700F7FDC4FEE400E70010), .INIT_2C(256'hFEE404E70390000700F7FDC4FEC404E702F0000700F7FDC4FEC41540FE04FE04), .INIT_2D(256'hFDC4FEC4FEF4FD070107010700F701070107000700F6FDC4FEC4010701070047), .INIT_2E(256'hFDC4FEC4010701070047FEE404E70660000700F7FDC4FEC404E70600000700F7), .INIT_2F(256'hFEC404E70400000700F7FDC4FEC4FEF4FA970107010700F701070107000700F6), .INIT_30(256'h00F701070107000700F6FDC4FEC4010701070047FEE404E70460000700F7FDC4), .INIT_31(256'hFEE4E807000700F7FDC4FEC400E70030FEC4FEF40017FEC4FEF4FC9701070107), .INIT_32(256'h02F0000700F7FE84FDC410C0FE04FE04FCA403010281FD010000030102C10007), .INIT_33(256'hFEF4FD0700E7000700E6FE84FDC40047FEC402E70390000700F7FE84FDC404E7), .INIT_34(256'hFE84FDC40047FEC402E70660000700F7FE84FDC404E70600000700F7FE84FDC4), .INIT_35(256'h0460000700F7FE84FDC404E70400000700F7FE84FDC4FEF4FA9700E7000700E6), .INIT_36(256'h00E70070FE84FEF40017FE84FEF4FC9700E7000700E6FE84FDC40047FEC402E7), .INIT_37(256'hFCC4FCB4000503010281FD010000030102C10007FEC4EC07000700F7FE84FDC4), .INIT_38(256'hFE74FEF400F70FF740F70027FFF740F6FEC4FE84FDF40940FEF40020FE04FCF4), .INIT_39(256'hFD8402E700F0FE7402E70090FE7400E70FF70307FE7400F7FEC4FD8402E70090), .INIT_3A(256'hF4E7FD440017FEC400F7FE84FEC4FEF40017FEC400E70FF70577FE7400F7FEC4), .INIT_3B(256'hFCF4FCC4FCB4000503010281FD010000030102C10007FD84000700F7FEC4FD84), .INIT_3C(256'h0090FE74FEF400F70FF740F70027FFF740F6FEC4FE84FDE40940FEF40040FE04), .INIT_3D(256'hFEC4FD8402E700F0FE7402E70090FE7400E70FF70307FE7400F7FEC4FD8402E7), .INIT_3E(256'hFD84F4E7FD440017FEC400F7FE84FEC4FEF40017FEC400E70FF70577FE7400F7), .INIT_3F(256'h0080FE04FCC4FCB4FCA403010281FD010000030102C10007FD84000700F7FEC4), .INIT_40(256'hFD8402E70090FE74FEF400F70FF700F7FDC40027FFF740F7FEC4FE840940FEF4), .INIT_41(256'hFE7400F7FEC4FD8402E700F0FE7402E70090FE7400E70FF70307FE7400F7FEC4), .INIT_42(256'h00F7FEC4FD84F4E7FD440017FEC400F7FE84FEC4FEF40017FEC400E70FF70577), .INIT_43(256'hFE070017000780000000FEF4000502010081FE010000030102C10007FD840007), .INIT_44(256'hFEC40280FE04FCA4030102810211FD010000020101C1000000E7FEF400878000), .INIT_45(256'h02C100000000FC07000700F7FDC4FEC4FEF40017FEC4F89F0007000700F7FDC4), .INIT_46(256'hFEF4000700478000FE070027000780000000020100810011FE01000003010281), .INIT_47(256'h00000201018101C10007FEF4EF5F0007FEF40100F4DF19C5000000F700D0FEF4), .INIT_48(256'h020101C10007FEF4FEF4000700478000FE07002700078000000002010081FE01), .INIT_49(256'h00F7000700F6FEC4FD84000700F7FEC4FDC4FE04FCB4FCA403010281FD010000), .INIT_4A(256'h030102C1000700000000FB5FFEF40017FEC40007000700F7FEC4FDC403000010), .INIT_4B(256'hFEC4FE07000700F7FEC4FDC4FEF40017FEC40100FE04FCA403010281FD010000), .INIT_4C(256'h0075007500000000006C0000656C000000003E31000000000000030102C10007), .INIT_4D(256'h000000000000000000000000000000006E6574207A696F636E55000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(18), .READ_WIDTH_B(18), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("WRITE_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(18), .WRITE_WIDTH_B(0)) douta_reg_1 (.ADDRARDADDR({\<const1> ,sel,\<const0> ,\<const0> ,\<const0> ,\<const0> }), .ADDRBWRADDR({\<const1> ,ADDRARDADDR[10:2],douta_reg_0_i_1_n_0,douta_reg_0_i_2_n_0,\<const0> ,\<const0> ,\<const0> ,\<const0> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(out[31:16]), .DOBDO(douta_reg_1_0[19:4]), .ENARDEN(\<const1> ), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF5FFF5FF3131F1FF)) \f_ex_imm[30]_i_7 (.I0(out[5]), .I1(doutb[1]), .I2(\br_inst_cnt_reg[0] ), .I3(out[6]), .I4(doutb[2]), .I5(\br_inst_cnt_reg[0]_0 ), .O(douta_reg_0_0)); LUT5 #( .INIT(32'hAE00AEAE)) mem_reg_0_0_i_1 (.I0(mem_reg_0_0_i_18_n_0), .I1(mem_reg_0_0_i_19_n_0), .I2(mem_reg_0_0_i_20__0_n_0), .I3(mem_reg_3_3_2), .I4(mem_reg_0_0_i_22_n_0), .O(ex_alu[15])); LUT6 #( .INIT(64'hFFF40000FFF4FFF4)) mem_reg_0_0_i_10 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_68_n_0), .I2(douta_reg_0_7), .I3(mem_reg_0_0_i_70_n_0), .I4(douta_reg_0_8), .I5(mem_reg_0_0_i_72_n_0), .O(ex_alu[6])); LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_100 (.I0(Q[4]), .I1(BSel), .I2(fwd_b[4]), .O(\f_ex_imm_reg[16] [1])); LUT6 #( .INIT(64'hFFFFFFFF444F4F44)) mem_reg_0_0_i_101 (.I0(mem_reg_0_0_i_241_n_0), .I1(\wb_alu[0]_i_3_n_0 ), .I2(ALUSel[0]), .I3(a_mux[15]), .I4(b_mux[15]), .I5(ALUSel[1]), .O(mem_reg_0_0_i_101_n_0)); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_102 (.I0(\wb_alu_reg[29]_i_5_0 [15]), .I1(ASel), .I2(wb_mux[15]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_43_0), .O(a_mux[15])); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_103 (.I0(Q[15]), .I1(BSel), .I2(fwd_b[15]), .O(b_mux[15])); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_104 (.CI(mem_reg_0_0_i_56_n_0), .CO({mem_reg_0_0_i_104_n_0,mem_reg_0_0_i_104_n_1,mem_reg_0_0_i_104_n_2,mem_reg_0_0_i_104_n_3}), .CYINIT(\<const0> ), .DI(a_mux[15:12]), .O(\f_ex_pc_reg[30]_0 [10:7]), .S({mem_reg_0_0_i_245_n_0,mem_reg_0_0_i_246_n_0,mem_reg_0_0_i_247_n_0,mem_reg_0_0_i_248_n_0})); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT3 #( .INIT(8'h5D)) mem_reg_0_0_i_105 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[15]), .O(mem_reg_0_0_i_105_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_107 (.I0(mem_reg_0_0_i_176_n_0), .I1(mem_reg_0_0_i_175_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_249_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_250_n_0), .O(mem_reg_0_0_i_107_n_0)); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_108 (.I0(mem_reg_0_0_i_251_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_252_n_0), .O(mem_reg_0_0_i_108_n_0)); (* SOFT_HLUTNM = "soft_lutpair87" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_109 (.I0(mem_reg_0_0_i_253_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_254_n_0), .O(mem_reg_0_0_i_109_n_0)); LUT6 #( .INIT(64'h0E00EEEEEEEEEEEE)) mem_reg_0_0_i_11 (.I0(mem_reg_0_0_i_73_n_0), .I1(mem_reg_0_0_i_74_n_0), .I2(douta_reg_0_2), .I3(\alu/data8 [5]), .I4(ALUSel[3]), .I5(mem_reg_0_0_i_76_n_0), .O(ex_alu[5])); LUT6 #( .INIT(64'hFFFFFFFF444F4F44)) mem_reg_0_0_i_110 (.I0(\wb_alu[30]_i_11_n_0 ), .I1(\wb_alu[0]_i_3_n_0 ), .I2(ALUSel[0]), .I3(a_mux[14]), .I4(b_mux[14]), .I5(ALUSel[1]), .O(mem_reg_0_0_i_110_n_0)); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_111 (.I0(\wb_alu_reg[29]_i_5_0 [14]), .I1(ASel), .I2(wb_mux[14]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_16_0), .O(a_mux[14])); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_112 (.I0(Q[14]), .I1(BSel), .I2(fwd_b[14]), .O(b_mux[14])); LUT6 #( .INIT(64'h00FF00FF00FF01FB)) mem_reg_0_0_i_113 (.I0(\f_ex_imm_reg[16] [0]), .I1(a_mux[30]), .I2(b_mux[0]), .I3(\wb_alu_reg[0]_i_18_1 ), .I4(b_mux[1]), .I5(b_mux[2]), .O(mem_reg_0_0_i_113_n_0)); LUT6 #( .INIT(64'h5F50CFCF5F50C0C0)) mem_reg_0_0_i_114 (.I0(mem_reg_0_0_i_257_n_0), .I1(mem_reg_0_0_i_258_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_259_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_260_n_0), .O(mem_reg_0_0_i_114_n_0)); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_115 (.I0(mem_reg_0_0_i_261_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_262_n_0), .O(mem_reg_0_0_i_115_n_0)); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_116 (.I0(mem_reg_0_0_i_263_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_264_n_0), .O(mem_reg_0_0_i_116_n_0)); LUT6 #( .INIT(64'hFFFFFFFF4040FF40)) mem_reg_0_0_i_117 (.I0(\f_ex_imm_reg[16] [0]), .I1(mem_reg_0_0_i_265_n_0), .I2(\wb_alu[0]_i_3_n_0 ), .I3(mem_reg_0_0_i_266_n_0), .I4(mem_reg_0_0_i_267_n_0), .I5(ALUSel[1]), .O(mem_reg_0_0_i_117_n_0)); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_118 (.I0(\wb_alu_reg[29]_i_5_0 [13]), .I1(ASel), .I2(wb_mux[13]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_44_1), .O(a_mux[13])); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_119 (.I0(Q[13]), .I1(BSel), .I2(fwd_b[13]), .O(b_mux[13])); LUT4 #( .INIT(16'h00AE)) mem_reg_0_0_i_12 (.I0(mem_reg_0_0_i_77_n_0), .I1(ALUSel[2]), .I2(mem_reg_0_0_i_79_n_0), .I3(mem_reg_0_0_i_80_n_0), .O(ex_alu[4])); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT5 #( .INIT(32'h33333237)) mem_reg_0_0_i_120 (.I0(\f_ex_imm_reg[16] [0]), .I1(\wb_alu_reg[0]_i_18_1 ), .I2(b_mux[2]), .I3(mem_reg_0_0_i_269_n_0), .I4(b_mux[1]), .O(mem_reg_0_0_i_120_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_121 (.I0(mem_reg_0_0_i_270_n_0), .I1(mem_reg_0_0_i_271_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_272_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_273_n_0), .O(mem_reg_0_0_i_121_n_0)); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_122 (.I0(\wb_alu[0]_i_12_n_0 ), .I1(b_mux[2]), .I2(mem_reg_0_0_i_274_n_0), .O(mem_reg_0_0_i_122_n_0)); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_123 (.I0(\wb_alu[0]_i_10_n_0 ), .I1(b_mux[2]), .I2(\wb_alu[0]_i_11_n_0 ), .O(mem_reg_0_0_i_123_n_0)); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT5 #( .INIT(32'hFFFF1000)) mem_reg_0_0_i_124 (.I0(\f_ex_imm_reg[16] [0]), .I1(b_mux[2]), .I2(\wb_alu[0]_i_9_n_0 ), .I3(\wb_alu[0]_i_3_n_0 ), .I4(mem_reg_0_0_i_275_n_0), .O(mem_reg_0_0_i_124_n_0)); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_125 (.I0(\wb_alu_reg[29]_i_5_0 [12]), .I1(ASel), .I2(wb_mux[12]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_44_0), .O(a_mux[12])); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_126 (.I0(Q[12]), .I1(BSel), .I2(fwd_b[12]), .O(b_mux[12])); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT4 #( .INIT(16'h3335)) mem_reg_0_0_i_127 (.I0(\wb_alu[0]_i_9_n_0 ), .I1(\wb_alu_reg[0]_i_18_1 ), .I2(b_mux[2]), .I3(\f_ex_imm_reg[16] [0]), .O(mem_reg_0_0_i_127_n_0)); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT5 #( .INIT(32'h30BB3088)) mem_reg_0_0_i_128 (.I0(mem_reg_0_0_i_166_n_0), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_164_n_0), .I3(b_mux[2]), .I4(mem_reg_0_0_i_230_n_0), .O(mem_reg_0_0_i_128_n_0)); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_129 (.CI(mem_reg_0_0_i_167_n_0), .CO({mem_reg_0_0_i_129_n_0,mem_reg_0_0_i_129_n_1,mem_reg_0_0_i_129_n_2,mem_reg_0_0_i_129_n_3}), .CYINIT(\<const0> ), .DI(a_mux[11:8]), .O(\alu/data0 [11:8]), .S({mem_reg_0_0_i_277_n_0,mem_reg_0_0_i_278_n_0,mem_reg_0_0_i_279_n_0,mem_reg_0_0_i_280_n_0})); LUT6 #( .INIT(64'h0E00EEEEEEEEEEEE)) mem_reg_0_0_i_13 (.I0(mem_reg_0_0_i_81_n_0), .I1(mem_reg_0_0_i_82_n_0), .I2(douta_reg_0_2), .I3(\alu/data8 [3]), .I4(ALUSel[3]), .I5(mem_reg_0_0_i_84_n_0), .O(\f_ex_inst_reg[2] [1])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_130 (.I0(mem_reg_0_0_i_237_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_281_n_0), .O(mem_reg_0_0_i_130_n_0)); (* SOFT_HLUTNM = "soft_lutpair88" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_131 (.I0(mem_reg_0_0_i_240_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_236_n_0), .O(mem_reg_0_0_i_131_n_0)); LUT6 #( .INIT(64'hFFFFFFFF54040000)) mem_reg_0_0_i_132 (.I0(\f_ex_imm_reg[16] [0]), .I1(mem_reg_0_0_i_239_n_0), .I2(b_mux[2]), .I3(mem_reg_0_0_i_282_n_0), .I4(\wb_alu[0]_i_3_n_0 ), .I5(mem_reg_0_0_i_283_n_0), .O(mem_reg_0_0_i_132_n_0)); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_133 (.I0(\wb_alu_reg[29]_i_5_0 [11]), .I1(ASel), .I2(wb_mux[11]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_29_1), .O(a_mux[11])); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_134 (.I0(Q[11]), .I1(BSel), .I2(fwd_b[11]), .O(b_mux[11])); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT4 #( .INIT(16'h5547)) mem_reg_0_0_i_135 (.I0(\wb_alu_reg[0]_i_18_1 ), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_239_n_0), .I3(b_mux[2]), .O(mem_reg_0_0_i_135_n_0)); LUT6 #( .INIT(64'hFE44FF55FE44AA00)) mem_reg_0_0_i_136 (.I0(\f_ex_imm_reg[16] [0]), .I1(mem_reg_0_0_i_285_n_0), .I2(b_mux[1]), .I3(\wb_alu_reg[0]_i_18_1 ), .I4(b_mux[2]), .I5(mem_reg_0_0_i_253_n_0), .O(mem_reg_0_0_i_136_n_0)); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_137 (.I0(mem_reg_0_0_i_252_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_286_n_0), .O(mem_reg_0_0_i_137_n_0)); (* SOFT_HLUTNM = "soft_lutpair87" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_138 (.I0(mem_reg_0_0_i_254_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_251_n_0), .O(mem_reg_0_0_i_138_n_0)); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_139 (.I0(Q[10]), .I1(BSel), .I2(fwd_b[10]), .O(b_mux[10])); LUT6 #( .INIT(64'h88888888A8AAA8A8)) mem_reg_0_0_i_14 (.I0(mem_reg_0_0_i_85_n_0), .I1(mem_reg_0_0_i_86_n_0), .I2(mem_reg_0_0_i_87_n_0), .I3(mem_reg_0_0_i_88_n_0), .I4(ALUSel[0]), .I5(mem_reg_0_0_i_90_n_0), .O(\f_ex_inst_reg[2] [0])); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT5 #( .INIT(32'h30BB3088)) mem_reg_0_0_i_140 (.I0(mem_reg_0_0_i_176_n_0), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_175_n_0), .I3(b_mux[2]), .I4(mem_reg_0_0_i_249_n_0), .O(mem_reg_0_0_i_140_n_0)); LUT6 #( .INIT(64'hFFFFFFFF54040000)) mem_reg_0_0_i_141 (.I0(\f_ex_imm_reg[16] [0]), .I1(mem_reg_0_0_i_253_n_0), .I2(b_mux[2]), .I3(mem_reg_0_0_i_285_n_0), .I4(\wb_alu[0]_i_3_n_0 ), .I5(mem_reg_0_0_i_287_n_0), .O(mem_reg_0_0_i_141_n_0)); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_142 (.I0(\wb_alu_reg[29]_i_5_0 [10]), .I1(ASel), .I2(wb_mux[10]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_29_0), .O(a_mux[10])); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT5 #( .INIT(32'h30773044)) mem_reg_0_0_i_143 (.I0(mem_reg_0_0_i_257_n_0), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_258_n_0), .I3(b_mux[2]), .I4(mem_reg_0_0_i_259_n_0), .O(mem_reg_0_0_i_143_n_0)); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT4 #( .INIT(16'hABFB)) mem_reg_0_0_i_144 (.I0(\f_ex_imm_reg[16] [0]), .I1(mem_reg_0_0_i_263_n_0), .I2(b_mux[2]), .I3(mem_reg_0_0_i_289_n_0), .O(mem_reg_0_0_i_144_n_0)); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT4 #( .INIT(16'hAABE)) mem_reg_0_0_i_145 (.I0(ALUSel[1]), .I1(b_mux[9]), .I2(a_mux[9]), .I3(ALUSel[0]), .O(mem_reg_0_0_i_145_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_146 (.I0(mem_reg_0_0_i_264_n_0), .I1(mem_reg_0_0_i_261_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_262_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_290_n_0), .O(mem_reg_0_0_i_146_n_0)); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT5 #( .INIT(32'h2B00FFFF)) mem_reg_0_0_i_147 (.I0(ALUSel[0]), .I1(a_mux[9]), .I2(b_mux[9]), .I3(ALUSel[1]), .I4(ALUSel[2]), .O(mem_reg_0_0_i_147_n_0)); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_148 (.I0(\wb_alu_reg[29]_i_5_0 [9]), .I1(ASel), .I2(wb_mux[9]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_46_0), .O(a_mux[9])); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_149 (.I0(\wb_alu_reg[29]_i_5_0 [8]), .I1(ASel), .I2(wb_mux[8]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_30_0), .O(a_mux[8])); LUT2 #( .INIT(4'h8)) mem_reg_0_0_i_15 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[1]), .O(p_1_in[1])); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_150 (.I0(a_mux[11]), .I1(b_mux[11]), .O(mem_reg_0_0_i_150_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_151 (.I0(a_mux[10]), .I1(b_mux[10]), .O(mem_reg_0_0_i_151_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_152 (.I0(a_mux[9]), .I1(b_mux[9]), .O(mem_reg_0_0_i_152_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_153 (.I0(a_mux[8]), .I1(b_mux[8]), .O(mem_reg_0_0_i_153_n_0)); LUT6 #( .INIT(64'hCDC8DDDDCDC88888)) mem_reg_0_0_i_155 (.I0(\f_ex_imm_reg[16] [0]), .I1(\wb_alu_reg[0]_i_18_1 ), .I2(b_mux[1]), .I3(mem_reg_0_0_i_269_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_263_n_0), .O(mem_reg_0_0_i_155_n_0)); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_156 (.I0(Q[9]), .I1(BSel), .I2(fwd_b[9]), .O(b_mux[9])); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT5 #( .INIT(32'h30BB3088)) mem_reg_0_0_i_157 (.I0(mem_reg_0_0_i_270_n_0), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_271_n_0), .I3(b_mux[2]), .I4(mem_reg_0_0_i_272_n_0), .O(mem_reg_0_0_i_157_n_0)); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT4 #( .INIT(16'hABFB)) mem_reg_0_0_i_158 (.I0(\f_ex_imm_reg[16] [0]), .I1(\wb_alu[0]_i_10_n_0 ), .I2(b_mux[2]), .I3(\wb_alu[0]_i_9_n_0 ), .O(mem_reg_0_0_i_158_n_0)); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT4 #( .INIT(16'hAABE)) mem_reg_0_0_i_159 (.I0(ALUSel[1]), .I1(b_mux[8]), .I2(a_mux[8]), .I3(ALUSel[0]), .O(mem_reg_0_0_i_159_n_0)); LUT2 #( .INIT(4'h8)) mem_reg_0_0_i_16 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[0]), .O(p_1_in[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_160 (.I0(\wb_alu[0]_i_11_n_0 ), .I1(\wb_alu[0]_i_12_n_0 ), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_274_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_293_n_0), .O(mem_reg_0_0_i_160_n_0)); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT5 #( .INIT(32'h2B00FFFF)) mem_reg_0_0_i_161 (.I0(ALUSel[0]), .I1(a_mux[8]), .I2(b_mux[8]), .I3(ALUSel[1]), .I4(ALUSel[2]), .O(mem_reg_0_0_i_161_n_0)); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT5 #( .INIT(32'hAAAACFC0)) mem_reg_0_0_i_162 (.I0(\wb_alu_reg[0]_i_18_1 ), .I1(\wb_alu[0]_i_9_n_0 ), .I2(b_mux[2]), .I3(\wb_alu[0]_i_10_n_0 ), .I4(\f_ex_imm_reg[16] [0]), .O(mem_reg_0_0_i_162_n_0)); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_163 (.I0(Q[8]), .I1(BSel), .I2(fwd_b[8]), .O(b_mux[8])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_164 (.I0(a_mux[4]), .I1(a_mux[5]), .I2(b_mux[1]), .I3(a_mux[6]), .I4(b_mux[0]), .I5(a_mux[7]), .O(mem_reg_0_0_i_164_n_0)); LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_165 (.I0(Q[2]), .I1(BSel), .I2(fwd_b[2]), .O(b_mux[2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_166 (.I0(a_mux[0]), .I1(a_mux[1]), .I2(b_mux[1]), .I3(a_mux[2]), .I4(b_mux[0]), .I5(a_mux[3]), .O(mem_reg_0_0_i_166_n_0)); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_167 (.CI(mem_reg_0_0_i_202_n_0), .CO({mem_reg_0_0_i_167_n_0,mem_reg_0_0_i_167_n_1,mem_reg_0_0_i_167_n_2,mem_reg_0_0_i_167_n_3}), .CYINIT(\<const0> ), .DI(a_mux[7:4]), .O({\f_ex_pc_reg[30] [1:0],\alu/data0 [5:4]}), .S({mem_reg_0_0_i_294_n_0,mem_reg_0_0_i_295_n_0,mem_reg_0_0_i_296_n_0,mem_reg_0_0_i_297_n_0})); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT3 #( .INIT(8'hFB)) mem_reg_0_0_i_168 (.I0(ALUSel[1]), .I1(ALUSel[0]), .I2(\f_ex_imm_reg[16] [1]), .O(mem_reg_0_0_i_168_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_169 (.I0(mem_reg_0_0_i_236_n_0), .I1(mem_reg_0_0_i_237_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_281_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_298_n_0), .O(mem_reg_0_0_i_169_n_0)); LUT4 #( .INIT(16'h80BC)) mem_reg_0_0_i_170 (.I0(ALUSel[1]), .I1(a_mux[7]), .I2(b_mux[7]), .I3(ALUSel[0]), .O(mem_reg_0_0_i_170_n_0)); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT5 #( .INIT(32'h30BB3088)) mem_reg_0_0_i_171 (.I0(mem_reg_0_0_i_282_n_0), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_239_n_0), .I3(b_mux[2]), .I4(mem_reg_0_0_i_240_n_0), .O(mem_reg_0_0_i_171_n_0)); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT3 #( .INIT(8'h08)) mem_reg_0_0_i_172 (.I0(ALUSel[0]), .I1(\f_ex_imm_reg[16] [1]), .I2(ALUSel[1]), .O(mem_reg_0_0_i_172_n_0)); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_173 (.I0(\wb_alu_reg[0]_i_18_1 ), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_239_n_0), .I3(b_mux[2]), .I4(mem_reg_0_0_i_240_n_0), .O(mem_reg_0_0_i_173_n_0)); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_174 (.I0(Q[7]), .I1(BSel), .I2(fwd_b[7]), .O(b_mux[7])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_175 (.I0(a_mux[3]), .I1(a_mux[4]), .I2(b_mux[1]), .I3(a_mux[5]), .I4(b_mux[0]), .I5(a_mux[6]), .O(mem_reg_0_0_i_175_n_0)); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT5 #( .INIT(32'h30BB3088)) mem_reg_0_0_i_176 (.I0(a_mux[0]), .I1(b_mux[1]), .I2(a_mux[1]), .I3(b_mux[0]), .I4(a_mux[2]), .O(mem_reg_0_0_i_176_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_177 (.I0(mem_reg_0_0_i_251_n_0), .I1(mem_reg_0_0_i_252_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_286_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_223_n_0), .O(mem_reg_0_0_i_177_n_0)); LUT4 #( .INIT(16'h80BC)) mem_reg_0_0_i_178 (.I0(ALUSel[1]), .I1(a_mux[6]), .I2(b_mux[6]), .I3(ALUSel[0]), .O(mem_reg_0_0_i_178_n_0)); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT5 #( .INIT(32'h30BB3088)) mem_reg_0_0_i_179 (.I0(mem_reg_0_0_i_285_n_0), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_253_n_0), .I3(b_mux[2]), .I4(mem_reg_0_0_i_254_n_0), .O(mem_reg_0_0_i_179_n_0)); LUT6 #( .INIT(64'h0000000000001000)) mem_reg_0_0_i_17__0 (.I0(ex_alu[30]), .I1(mem_reg_2_3), .I2(ex_alu[28]), .I3(MemRW[0]), .I4(ex_alu[0]), .I5(ex_alu[1]), .O(dmem_we[0])); LUT5 #( .INIT(32'hFFFF44F4)) mem_reg_0_0_i_18 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_95_n_0), .I2(\alu/data0 [15]), .I3(douta_reg_0_2), .I4(ALUSel[3]), .O(mem_reg_0_0_i_18_n_0)); LUT6 #( .INIT(64'hCFC0EFEFCFC0E0E0)) mem_reg_0_0_i_180 (.I0(mem_reg_0_0_i_285_n_0), .I1(mem_reg_0_0_i_299_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_253_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_254_n_0), .O(mem_reg_0_0_i_180_n_0)); LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_181 (.I0(Q[6]), .I1(BSel), .I2(fwd_b[6]), .O(b_mux[6])); LUT6 #( .INIT(64'h00B8FFFF00B80000)) mem_reg_0_0_i_182 (.I0(a_mux[0]), .I1(b_mux[0]), .I2(a_mux[1]), .I3(b_mux[1]), .I4(b_mux[2]), .I5(mem_reg_0_0_i_258_n_0), .O(mem_reg_0_0_i_182_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_183 (.I0(mem_reg_0_0_i_261_n_0), .I1(mem_reg_0_0_i_262_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_290_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_300_n_0), .O(mem_reg_0_0_i_183_n_0)); LUT4 #( .INIT(16'h80BC)) mem_reg_0_0_i_184 (.I0(ALUSel[1]), .I1(a_mux[5]), .I2(b_mux[5]), .I3(ALUSel[0]), .O(mem_reg_0_0_i_184_n_0)); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT5 #( .INIT(32'h30BB3088)) mem_reg_0_0_i_185 (.I0(mem_reg_0_0_i_289_n_0), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_263_n_0), .I3(b_mux[2]), .I4(mem_reg_0_0_i_264_n_0), .O(mem_reg_0_0_i_185_n_0)); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_186 (.I0(\wb_alu_reg[29]_i_5_0 [7]), .I1(ASel), .I2(wb_mux[7]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_60_1), .O(a_mux[7])); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_187 (.I0(\wb_alu_reg[29]_i_5_0 [6]), .I1(ASel), .I2(wb_mux[6]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_60_0), .O(a_mux[6])); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_188 (.I0(\wb_alu_reg[29]_i_5_0 [5]), .I1(ASel), .I2(wb_mux[5]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_31_1), .O(a_mux[5])); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_189 (.I0(\wb_alu_reg[29]_i_5_0 [4]), .I1(ASel), .I2(wb_mux[4]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_31_0), .O(a_mux[4])); LUT6 #( .INIT(64'hFFFFFFFF0000A808)) mem_reg_0_0_i_19 (.I0(ALUSel[0]), .I1(mem_reg_0_0_i_97_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_99_n_0), .I4(\f_ex_imm_reg[16] [1]), .I5(mem_reg_0_0_i_101_n_0), .O(mem_reg_0_0_i_19_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_190 (.I0(a_mux[7]), .I1(b_mux[7]), .O(mem_reg_0_0_i_190_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_191 (.I0(a_mux[6]), .I1(b_mux[6]), .O(mem_reg_0_0_i_191_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_192 (.I0(a_mux[5]), .I1(b_mux[5]), .O(mem_reg_0_0_i_192_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_193 (.I0(a_mux[4]), .I1(\f_ex_imm_reg[16] [1]), .O(mem_reg_0_0_i_193_n_0)); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_194 (.I0(Q[5]), .I1(BSel), .I2(fwd_b[5]), .O(b_mux[5])); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT5 #( .INIT(32'h74777444)) mem_reg_0_0_i_195 (.I0(mem_reg_0_0_i_305_n_0), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_263_n_0), .I3(b_mux[2]), .I4(mem_reg_0_0_i_264_n_0), .O(mem_reg_0_0_i_195_n_0)); LUT6 #( .INIT(64'h0000000022222E22)) mem_reg_0_0_i_196 (.I0(mem_reg_0_0_i_271_n_0), .I1(b_mux[2]), .I2(b_mux[1]), .I3(a_mux[0]), .I4(b_mux[0]), .I5(\f_ex_imm_reg[16] [0]), .O(mem_reg_0_0_i_196_n_0)); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT5 #( .INIT(32'h30BB3088)) mem_reg_0_0_i_197 (.I0(\wb_alu[0]_i_9_n_0 ), .I1(\f_ex_imm_reg[16] [0]), .I2(\wb_alu[0]_i_10_n_0 ), .I3(b_mux[2]), .I4(\wb_alu[0]_i_11_n_0 ), .O(mem_reg_0_0_i_197_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_198 (.I0(\wb_alu[0]_i_12_n_0 ), .I1(mem_reg_0_0_i_274_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_293_n_0), .I4(b_mux[2]), .I5(\wb_alu[0]_i_7_n_0 ), .O(mem_reg_0_0_i_198_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_199 (.I0(\wb_alu_reg[0]_i_18_1 ), .I1(\wb_alu[0]_i_9_n_0 ), .I2(\f_ex_imm_reg[16] [0]), .I3(\wb_alu[0]_i_10_n_0 ), .I4(b_mux[2]), .I5(\wb_alu[0]_i_11_n_0 ), .O(mem_reg_0_0_i_199_n_0)); LUT6 #( .INIT(64'h0000001000000000)) mem_reg_0_0_i_19__0 (.I0(ex_alu[30]), .I1(mem_reg_2_3), .I2(MemRW[0]), .I3(ex_alu[0]), .I4(ex_alu[1]), .I5(ex_alu[29]), .O(imem_wea[0])); LUT5 #( .INIT(32'hAE00AEAE)) mem_reg_0_0_i_1__0 (.I0(mem_reg_0_0_i_18_n_0), .I1(mem_reg_0_0_i_19_n_0), .I2(mem_reg_0_0_i_20__0_n_0), .I3(mem_reg_3_3_2), .I4(mem_reg_0_0_i_22_n_0), .O(ADDRARDADDR[13])); LUT6 #( .INIT(64'hAE00AE00AE00AEAE)) mem_reg_0_0_i_2 (.I0(mem_reg_0_0_i_23_n_0), .I1(mem_reg_0_0_i_24_n_0), .I2(mem_reg_0_0_i_25__0_n_0), .I3(mem_reg_3_3_3), .I4(mem_reg_0_0_i_27_n_0), .I5(mem_reg_0_0_i_28_n_0), .O(ex_alu[14])); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT3 #( .INIT(8'h04)) mem_reg_0_0_i_201 (.I0(b_mux[2]), .I1(mem_reg_0_0_i_166_n_0), .I2(\f_ex_imm_reg[16] [0]), .O(mem_reg_0_0_i_201_n_0)); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_202 (.CI(\<const0> ), .CO({mem_reg_0_0_i_202_n_0,mem_reg_0_0_i_202_n_1,mem_reg_0_0_i_202_n_2,mem_reg_0_0_i_202_n_3}), .CYINIT(\<const0> ), .DI(a_mux[3:0]), .O(\alu/data0 [3:0]), .S({mem_reg_0_0_i_306_n_0,mem_reg_0_0_i_307_n_0,mem_reg_0_0_i_308_n_0,mem_reg_0_0_i_309_n_0})); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_203 (.I0(mem_reg_0_0_i_282_n_0), .I1(mem_reg_0_0_i_239_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_240_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_236_n_0), .O(mem_reg_0_0_i_203_n_0)); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT4 #( .INIT(16'hAABE)) mem_reg_0_0_i_204 (.I0(ALUSel[1]), .I1(a_mux[3]), .I2(\f_ex_imm_reg[16] [0]), .I3(ALUSel[0]), .O(mem_reg_0_0_i_204_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_205 (.I0(mem_reg_0_0_i_237_n_0), .I1(mem_reg_0_0_i_281_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_298_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_310_n_0), .O(mem_reg_0_0_i_205_n_0)); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT5 #( .INIT(32'h2B00FFFF)) mem_reg_0_0_i_206 (.I0(ALUSel[0]), .I1(\f_ex_imm_reg[16] [0]), .I2(a_mux[3]), .I3(ALUSel[1]), .I4(ALUSel[2]), .O(mem_reg_0_0_i_206_n_0)); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_207 (.I0(\wb_alu_reg[29]_i_5_0 [3]), .I1(ASel), .I2(wb_mux[3]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_62_0), .O(a_mux[3])); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_208 (.I0(\wb_alu_reg[29]_i_5_0 [2]), .I1(ASel), .I2(wb_mux[2]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_32_0), .O(a_mux[2])); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_209 (.I0(\wb_alu_reg[29]_i_5_0 [1]), .I1(ASel), .I2(wb_mux[1]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_63_1), .O(a_mux[1])); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT5 #( .INIT(32'h2B00FFFF)) mem_reg_0_0_i_20__0 (.I0(ALUSel[0]), .I1(a_mux[15]), .I2(b_mux[15]), .I3(ALUSel[1]), .I4(ALUSel[2]), .O(mem_reg_0_0_i_20__0_n_0)); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_210 (.I0(\wb_alu_reg[29]_i_5_0 [0]), .I1(ASel), .I2(wb_mux[0]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_63_0), .O(a_mux[0])); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_211 (.I0(a_mux[3]), .I1(\f_ex_imm_reg[16] [0]), .O(mem_reg_0_0_i_211_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_212 (.I0(a_mux[2]), .I1(b_mux[2]), .O(mem_reg_0_0_i_212_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_213 (.I0(a_mux[1]), .I1(b_mux[1]), .O(mem_reg_0_0_i_213_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_214 (.I0(a_mux[0]), .I1(b_mux[0]), .O(mem_reg_0_0_i_214_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_215 (.I0(\wb_alu_reg[0]_i_18_1 ), .I1(mem_reg_0_0_i_239_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_240_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_236_n_0), .O(mem_reg_0_0_i_215_n_0)); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT3 #( .INIT(8'h5D)) mem_reg_0_0_i_216 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[2]), .O(mem_reg_0_0_i_216_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_217 (.I0(mem_reg_0_0_i_315_n_0), .I1(mem_reg_0_0_i_253_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_254_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_251_n_0), .O(mem_reg_0_0_i_217_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_218 (.I0(mem_reg_0_0_i_252_n_0), .I1(mem_reg_0_0_i_286_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_223_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_222_n_0), .O(mem_reg_0_0_i_218_n_0)); LUT6 #( .INIT(64'hAAAAAAAAFFFFABFB)) mem_reg_0_0_i_22 (.I0(mem_reg_0_0_i_105_n_0), .I1(mem_reg_0_0_i_97_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_99_n_0), .I4(\f_ex_imm_reg[16] [1]), .I5(\wb_alu_reg[22] ), .O(mem_reg_0_0_i_22_n_0)); LUT6 #( .INIT(64'h0000000033E200E2)) mem_reg_0_0_i_220 (.I0(a_mux[2]), .I1(b_mux[0]), .I2(a_mux[1]), .I3(b_mux[1]), .I4(a_mux[0]), .I5(b_mux[2]), .O(mem_reg_0_0_i_220_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_221 (.I0(mem_reg_0_0_i_285_n_0), .I1(mem_reg_0_0_i_253_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_254_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_251_n_0), .O(mem_reg_0_0_i_221_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_222 (.I0(a_mux[5]), .I1(a_mux[4]), .I2(b_mux[1]), .I3(a_mux[3]), .I4(b_mux[0]), .I5(a_mux[2]), .O(mem_reg_0_0_i_222_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_223 (.I0(a_mux[9]), .I1(a_mux[8]), .I2(b_mux[1]), .I3(a_mux[7]), .I4(b_mux[0]), .I5(a_mux[6]), .O(mem_reg_0_0_i_223_n_0)); LUT6 #( .INIT(64'h1F001F1F1F000000)) mem_reg_0_0_i_224 (.I0(\pprev_data_reg[0]_1 [2]), .I1(\pprev_data_reg[0]_1 [0]), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_0_5_i_28_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(mem_reg_0_0_i_316_n_0), .O(ld_data[1])); LUT6 #( .INIT(64'h1F001F1F1F000000)) mem_reg_0_0_i_227 (.I0(\pprev_data_reg[0]_1 [2]), .I1(\pprev_data_reg[0]_1 [0]), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_0_5_i_31_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(mem_reg_0_0_i_321_n_0), .O(ld_data[0])); LUT5 #( .INIT(32'hFFFF44F4)) mem_reg_0_0_i_23 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_107_n_0), .I2(\alu/data0 [14]), .I3(douta_reg_0_2), .I4(ALUSel[3]), .O(mem_reg_0_0_i_23_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_230 (.I0(a_mux[8]), .I1(a_mux[9]), .I2(b_mux[1]), .I3(a_mux[10]), .I4(b_mux[0]), .I5(a_mux[11]), .O(mem_reg_0_0_i_230_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_231 (.I0(a_mux[12]), .I1(a_mux[13]), .I2(b_mux[1]), .I3(a_mux[14]), .I4(b_mux[0]), .I5(a_mux[15]), .O(mem_reg_0_0_i_231_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_232 (.I0(b_mux[15]), .I1(a_mux[15]), .O(mem_reg_0_0_i_232_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_233 (.I0(a_mux[14]), .I1(b_mux[14]), .O(mem_reg_0_0_i_233_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_234 (.I0(a_mux[13]), .I1(b_mux[13]), .O(mem_reg_0_0_i_234_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_235 (.I0(a_mux[12]), .I1(b_mux[12]), .O(mem_reg_0_0_i_235_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_236 (.I0(a_mux[22]), .I1(a_mux[21]), .I2(b_mux[1]), .I3(a_mux[20]), .I4(b_mux[0]), .I5(a_mux[19]), .O(mem_reg_0_0_i_236_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_237 (.I0(a_mux[18]), .I1(a_mux[17]), .I2(b_mux[1]), .I3(a_mux[16]), .I4(b_mux[0]), .I5(a_mux[15]), .O(mem_reg_0_0_i_237_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_239 (.I0(a_mux[30]), .I1(a_mux[29]), .I2(b_mux[1]), .I3(a_mux[28]), .I4(b_mux[0]), .I5(a_mux[27]), .O(mem_reg_0_0_i_239_n_0)); LUT6 #( .INIT(64'hFFFFFFFF54040000)) mem_reg_0_0_i_24 (.I0(\f_ex_imm_reg[16] [1]), .I1(mem_reg_0_0_i_108_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_109_n_0), .I4(ALUSel[0]), .I5(mem_reg_0_0_i_110_n_0), .O(mem_reg_0_0_i_24_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_240 (.I0(a_mux[26]), .I1(a_mux[25]), .I2(b_mux[1]), .I3(a_mux[24]), .I4(b_mux[0]), .I5(a_mux[23]), .O(mem_reg_0_0_i_240_n_0)); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT5 #( .INIT(32'hFFFFFEFF)) mem_reg_0_0_i_241 (.I0(\f_ex_imm_reg[16] [0]), .I1(b_mux[2]), .I2(b_mux[1]), .I3(\wb_alu_reg[0]_i_18_1 ), .I4(b_mux[0]), .O(mem_reg_0_0_i_241_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_245 (.I0(a_mux[15]), .I1(b_mux[15]), .O(mem_reg_0_0_i_245_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_246 (.I0(a_mux[14]), .I1(b_mux[14]), .O(mem_reg_0_0_i_246_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_247 (.I0(a_mux[13]), .I1(b_mux[13]), .O(mem_reg_0_0_i_247_n_0)); LUT2 #( .INIT(4'h9)) mem_reg_0_0_i_248 (.I0(a_mux[12]), .I1(b_mux[12]), .O(mem_reg_0_0_i_248_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_249 (.I0(a_mux[7]), .I1(a_mux[8]), .I2(b_mux[1]), .I3(a_mux[9]), .I4(b_mux[0]), .I5(a_mux[10]), .O(mem_reg_0_0_i_249_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_250 (.I0(a_mux[11]), .I1(a_mux[12]), .I2(b_mux[1]), .I3(a_mux[13]), .I4(b_mux[0]), .I5(a_mux[14]), .O(mem_reg_0_0_i_250_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_251 (.I0(a_mux[21]), .I1(a_mux[20]), .I2(b_mux[1]), .I3(a_mux[19]), .I4(b_mux[0]), .I5(a_mux[18]), .O(mem_reg_0_0_i_251_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_252 (.I0(a_mux[17]), .I1(a_mux[16]), .I2(b_mux[1]), .I3(a_mux[15]), .I4(b_mux[0]), .I5(a_mux[14]), .O(mem_reg_0_0_i_252_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_253 (.I0(a_mux[29]), .I1(a_mux[28]), .I2(b_mux[1]), .I3(a_mux[27]), .I4(b_mux[0]), .I5(a_mux[26]), .O(mem_reg_0_0_i_253_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_254 (.I0(a_mux[25]), .I1(a_mux[24]), .I2(b_mux[1]), .I3(a_mux[23]), .I4(b_mux[0]), .I5(a_mux[22]), .O(mem_reg_0_0_i_254_n_0)); LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_256 (.I0(Q[0]), .I1(BSel), .I2(fwd_b[0]), .O(b_mux[0])); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT4 #( .INIT(16'hABFB)) mem_reg_0_0_i_257 (.I0(b_mux[1]), .I1(a_mux[1]), .I2(b_mux[0]), .I3(a_mux[0]), .O(mem_reg_0_0_i_257_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_258 (.I0(a_mux[2]), .I1(a_mux[3]), .I2(b_mux[1]), .I3(a_mux[4]), .I4(b_mux[0]), .I5(a_mux[5]), .O(mem_reg_0_0_i_258_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_259 (.I0(a_mux[6]), .I1(a_mux[7]), .I2(b_mux[1]), .I3(a_mux[8]), .I4(b_mux[0]), .I5(a_mux[9]), .O(mem_reg_0_0_i_259_n_0)); LUT5 #( .INIT(32'h2B00FFFF)) mem_reg_0_0_i_25__0 (.I0(ALUSel[0]), .I1(a_mux[14]), .I2(b_mux[14]), .I3(ALUSel[1]), .I4(ALUSel[2]), .O(mem_reg_0_0_i_25__0_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_260 (.I0(a_mux[10]), .I1(a_mux[11]), .I2(b_mux[1]), .I3(a_mux[12]), .I4(b_mux[0]), .I5(a_mux[13]), .O(mem_reg_0_0_i_260_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_261 (.I0(a_mux[20]), .I1(a_mux[19]), .I2(b_mux[1]), .I3(a_mux[18]), .I4(b_mux[0]), .I5(a_mux[17]), .O(mem_reg_0_0_i_261_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_262 (.I0(a_mux[16]), .I1(a_mux[15]), .I2(b_mux[1]), .I3(a_mux[14]), .I4(b_mux[0]), .I5(a_mux[13]), .O(mem_reg_0_0_i_262_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_263 (.I0(a_mux[28]), .I1(a_mux[27]), .I2(b_mux[1]), .I3(a_mux[26]), .I4(b_mux[0]), .I5(a_mux[25]), .O(mem_reg_0_0_i_263_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_264 (.I0(a_mux[24]), .I1(a_mux[23]), .I2(b_mux[1]), .I3(a_mux[22]), .I4(b_mux[0]), .I5(a_mux[21]), .O(mem_reg_0_0_i_264_n_0)); LUT6 #( .INIT(64'h0000000033E200E2)) mem_reg_0_0_i_265 (.I0(a_mux[29]), .I1(b_mux[0]), .I2(a_mux[30]), .I3(b_mux[1]), .I4(\wb_alu_reg[0]_i_18_1 ), .I5(b_mux[2]), .O(mem_reg_0_0_i_265_n_0)); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT5 #( .INIT(32'h54555444)) mem_reg_0_0_i_266 (.I0(ALUSel[0]), .I1(a_mux[13]), .I2(Q[13]), .I3(BSel), .I4(fwd_b[13]), .O(mem_reg_0_0_i_266_n_0)); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT4 #( .INIT(16'hE200)) mem_reg_0_0_i_267 (.I0(fwd_b[13]), .I1(BSel), .I2(Q[13]), .I3(a_mux[13]), .O(mem_reg_0_0_i_267_n_0)); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_269 (.I0(a_mux[30]), .I1(b_mux[0]), .I2(a_mux[29]), .O(mem_reg_0_0_i_269_n_0)); LUT6 #( .INIT(64'h00000000FF470047)) mem_reg_0_0_i_27 (.I0(mem_reg_0_0_i_109_n_0), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_108_n_0), .I3(\f_ex_imm_reg[16] [1]), .I4(mem_reg_0_0_i_113_n_0), .I5(ALUSel[1]), .O(mem_reg_0_0_i_27_n_0)); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT3 #( .INIT(8'h04)) mem_reg_0_0_i_270 (.I0(b_mux[0]), .I1(a_mux[0]), .I2(b_mux[1]), .O(mem_reg_0_0_i_270_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_271 (.I0(a_mux[1]), .I1(a_mux[2]), .I2(b_mux[1]), .I3(a_mux[3]), .I4(b_mux[0]), .I5(a_mux[4]), .O(mem_reg_0_0_i_271_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_272 (.I0(a_mux[5]), .I1(a_mux[6]), .I2(b_mux[1]), .I3(a_mux[7]), .I4(b_mux[0]), .I5(a_mux[8]), .O(mem_reg_0_0_i_272_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_273 (.I0(a_mux[9]), .I1(a_mux[10]), .I2(b_mux[1]), .I3(a_mux[11]), .I4(b_mux[0]), .I5(a_mux[12]), .O(mem_reg_0_0_i_273_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_274 (.I0(a_mux[15]), .I1(a_mux[14]), .I2(b_mux[1]), .I3(a_mux[13]), .I4(b_mux[0]), .I5(a_mux[12]), .O(mem_reg_0_0_i_274_n_0)); LUT6 #( .INIT(64'hAAAAAAAAABFBFEAE)) mem_reg_0_0_i_275 (.I0(ALUSel[1]), .I1(fwd_b[12]), .I2(BSel), .I3(Q[12]), .I4(a_mux[12]), .I5(ALUSel[0]), .O(mem_reg_0_0_i_275_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_277 (.I0(a_mux[11]), .I1(b_mux[11]), .O(mem_reg_0_0_i_277_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_278 (.I0(a_mux[10]), .I1(b_mux[10]), .O(mem_reg_0_0_i_278_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_279 (.I0(a_mux[9]), .I1(b_mux[9]), .O(mem_reg_0_0_i_279_n_0)); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT3 #( .INIT(8'h5D)) mem_reg_0_0_i_28 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[14]), .O(mem_reg_0_0_i_28_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_280 (.I0(a_mux[8]), .I1(b_mux[8]), .O(mem_reg_0_0_i_280_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_281 (.I0(a_mux[14]), .I1(a_mux[13]), .I2(b_mux[1]), .I3(a_mux[12]), .I4(b_mux[0]), .I5(a_mux[11]), .O(mem_reg_0_0_i_281_n_0)); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT3 #( .INIT(8'h04)) mem_reg_0_0_i_282 (.I0(b_mux[1]), .I1(\wb_alu_reg[0]_i_18_1 ), .I2(b_mux[0]), .O(mem_reg_0_0_i_282_n_0)); LUT6 #( .INIT(64'hAAAAAAAAABFBFEAE)) mem_reg_0_0_i_283 (.I0(ALUSel[1]), .I1(fwd_b[11]), .I2(BSel), .I3(Q[11]), .I4(a_mux[11]), .I5(ALUSel[0]), .O(mem_reg_0_0_i_283_n_0)); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT4 #( .INIT(16'h00E2)) mem_reg_0_0_i_285 (.I0(a_mux[30]), .I1(b_mux[0]), .I2(\wb_alu_reg[0]_i_18_1 ), .I3(b_mux[1]), .O(mem_reg_0_0_i_285_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_286 (.I0(a_mux[13]), .I1(a_mux[12]), .I2(b_mux[1]), .I3(a_mux[11]), .I4(b_mux[0]), .I5(a_mux[10]), .O(mem_reg_0_0_i_286_n_0)); LUT6 #( .INIT(64'hAAAAAAAAABFBFEAE)) mem_reg_0_0_i_287 (.I0(ALUSel[1]), .I1(fwd_b[10]), .I2(BSel), .I3(Q[10]), .I4(a_mux[10]), .I5(ALUSel[0]), .O(mem_reg_0_0_i_287_n_0)); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT5 #( .INIT(32'h30BB3088)) mem_reg_0_0_i_289 (.I0(\wb_alu_reg[0]_i_18_1 ), .I1(b_mux[1]), .I2(a_mux[30]), .I3(b_mux[0]), .I4(a_mux[29]), .O(mem_reg_0_0_i_289_n_0)); LUT5 #( .INIT(32'hFFFF44F4)) mem_reg_0_0_i_29 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_114_n_0), .I2(\alu/data0 [13]), .I3(douta_reg_0_2), .I4(ALUSel[3]), .O(mem_reg_0_0_i_29_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_290 (.I0(a_mux[12]), .I1(a_mux[11]), .I2(b_mux[1]), .I3(a_mux[10]), .I4(b_mux[0]), .I5(a_mux[9]), .O(mem_reg_0_0_i_290_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_293 (.I0(a_mux[11]), .I1(a_mux[10]), .I2(b_mux[1]), .I3(a_mux[9]), .I4(b_mux[0]), .I5(a_mux[8]), .O(mem_reg_0_0_i_293_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_294 (.I0(b_mux[7]), .I1(a_mux[7]), .O(mem_reg_0_0_i_294_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_295 (.I0(b_mux[6]), .I1(a_mux[6]), .O(mem_reg_0_0_i_295_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_296 (.I0(b_mux[5]), .I1(a_mux[5]), .O(mem_reg_0_0_i_296_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_297 (.I0(\f_ex_imm_reg[16] [1]), .I1(a_mux[4]), .O(mem_reg_0_0_i_297_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_298 (.I0(a_mux[10]), .I1(a_mux[9]), .I2(b_mux[1]), .I3(a_mux[8]), .I4(b_mux[0]), .I5(a_mux[7]), .O(mem_reg_0_0_i_298_n_0)); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT3 #( .INIT(8'hE0)) mem_reg_0_0_i_299 (.I0(b_mux[2]), .I1(b_mux[1]), .I2(\wb_alu_reg[0]_i_18_1 ), .O(mem_reg_0_0_i_299_n_0)); LUT6 #( .INIT(64'hAE00AE00AE00AEAE)) mem_reg_0_0_i_2__0 (.I0(mem_reg_0_0_i_23_n_0), .I1(mem_reg_0_0_i_24_n_0), .I2(mem_reg_0_0_i_25__0_n_0), .I3(mem_reg_3_3_3), .I4(mem_reg_0_0_i_27_n_0), .I5(mem_reg_0_0_i_28_n_0), .O(ADDRARDADDR[12])); LUT6 #( .INIT(64'hAE00AE00AE00AEAE)) mem_reg_0_0_i_3 (.I0(mem_reg_0_0_i_29_n_0), .I1(mem_reg_0_0_i_30_n_0), .I2(mem_reg_0_0_i_31__0_n_0), .I3(mem_reg_3_3_1), .I4(mem_reg_0_0_i_33_n_0), .I5(mem_reg_0_0_i_34_n_0), .O(ADDRARDADDR[11])); LUT6 #( .INIT(64'hFFFFFFFF54040000)) mem_reg_0_0_i_30 (.I0(\f_ex_imm_reg[16] [1]), .I1(mem_reg_0_0_i_115_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_116_n_0), .I4(ALUSel[0]), .I5(mem_reg_0_0_i_117_n_0), .O(mem_reg_0_0_i_30_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_300 (.I0(a_mux[8]), .I1(a_mux[7]), .I2(b_mux[1]), .I3(a_mux[6]), .I4(b_mux[0]), .I5(a_mux[5]), .O(mem_reg_0_0_i_300_n_0)); LUT6 #( .INIT(64'h5555555544477747)) mem_reg_0_0_i_305 (.I0(\wb_alu_reg[0]_i_18_1 ), .I1(b_mux[2]), .I2(a_mux[29]), .I3(b_mux[0]), .I4(a_mux[30]), .I5(b_mux[1]), .O(mem_reg_0_0_i_305_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_306 (.I0(\f_ex_imm_reg[16] [0]), .I1(a_mux[3]), .O(mem_reg_0_0_i_306_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_307 (.I0(b_mux[2]), .I1(a_mux[2]), .O(mem_reg_0_0_i_307_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_308 (.I0(b_mux[1]), .I1(a_mux[1]), .O(mem_reg_0_0_i_308_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_309 (.I0(a_mux[0]), .I1(b_mux[0]), .O(mem_reg_0_0_i_309_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_310 (.I0(a_mux[6]), .I1(a_mux[5]), .I2(b_mux[1]), .I3(a_mux[4]), .I4(b_mux[0]), .I5(a_mux[3]), .O(mem_reg_0_0_i_310_n_0)); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT4 #( .INIT(16'hFE04)) mem_reg_0_0_i_315 (.I0(b_mux[0]), .I1(a_mux[30]), .I2(b_mux[1]), .I3(\wb_alu_reg[0]_i_18_1 ), .O(mem_reg_0_0_i_315_n_0)); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_0_0_i_316 (.I0(mem_reg_r1_0_31_6_11_i_12_0), .I1(mem_reg_r1_0_31_6_11_i_49_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_reg_0_0_i_224_0), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_0_0_i_325_n_0), .O(mem_reg_0_0_i_316_n_0)); LUT5 #( .INIT(32'h2B00FFFF)) mem_reg_0_0_i_31__0 (.I0(ALUSel[0]), .I1(a_mux[13]), .I2(b_mux[13]), .I3(ALUSel[1]), .I4(ALUSel[2]), .O(mem_reg_0_0_i_31__0_n_0)); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_0_0_i_321 (.I0(mem_reg_r1_0_31_6_11_i_15_0), .I1(mem_reg_r1_0_31_6_11_i_52_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_reg_0_0_i_227_0), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_0_0_i_331_n_0), .O(mem_reg_0_0_i_321_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_0_0_i_325 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[1]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[1]), .O(mem_reg_0_0_i_325_n_0)); LUT6 #( .INIT(64'h00000000FF470047)) mem_reg_0_0_i_33 (.I0(mem_reg_0_0_i_116_n_0), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_115_n_0), .I3(\f_ex_imm_reg[16] [1]), .I4(mem_reg_0_0_i_120_n_0), .I5(ALUSel[1]), .O(mem_reg_0_0_i_33_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_0_0_i_331 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[0]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[0]), .O(mem_reg_0_0_i_331_n_0)); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT3 #( .INIT(8'h5D)) mem_reg_0_0_i_34 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[13]), .O(mem_reg_0_0_i_34_n_0)); LUT5 #( .INIT(32'hFFFF44F4)) mem_reg_0_0_i_35 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_121_n_0), .I2(\alu/data0 [12]), .I3(douta_reg_0_2), .I4(ALUSel[3]), .O(mem_reg_0_0_i_35_n_0)); LUT6 #( .INIT(64'hFFFFFFFF54040000)) mem_reg_0_0_i_36 (.I0(\f_ex_imm_reg[16] [1]), .I1(mem_reg_0_0_i_122_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_123_n_0), .I4(ALUSel[0]), .I5(mem_reg_0_0_i_124_n_0), .O(mem_reg_0_0_i_36_n_0)); LUT5 #( .INIT(32'h2B00FFFF)) mem_reg_0_0_i_37__0 (.I0(ALUSel[0]), .I1(a_mux[12]), .I2(b_mux[12]), .I3(ALUSel[1]), .I4(ALUSel[2]), .O(mem_reg_0_0_i_37__0_n_0)); LUT6 #( .INIT(64'h00000000FF470047)) mem_reg_0_0_i_39 (.I0(mem_reg_0_0_i_123_n_0), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_122_n_0), .I3(\f_ex_imm_reg[16] [1]), .I4(mem_reg_0_0_i_127_n_0), .I5(ALUSel[1]), .O(mem_reg_0_0_i_39_n_0)); LUT6 #( .INIT(64'h0E00EEEEEEEEEEEE)) mem_reg_0_0_i_3__0 (.I0(mem_reg_0_0_i_81_n_0), .I1(mem_reg_0_0_i_82_n_0), .I2(douta_reg_0_2), .I3(\alu/data8 [3]), .I4(ALUSel[3]), .I5(mem_reg_0_0_i_84_n_0), .O(ADDRARDADDR[1])); LUT6 #( .INIT(64'hAE00AE00AE00AEAE)) mem_reg_0_0_i_4 (.I0(mem_reg_0_0_i_35_n_0), .I1(mem_reg_0_0_i_36_n_0), .I2(mem_reg_0_0_i_37__0_n_0), .I3(douta_reg_0_6), .I4(mem_reg_0_0_i_39_n_0), .I5(mem_reg_0_0_i_40_n_0), .O(ex_alu[12])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT3 #( .INIT(8'h5D)) mem_reg_0_0_i_40 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[12]), .O(mem_reg_0_0_i_40_n_0)); LUT5 #( .INIT(32'hFFFF44F4)) mem_reg_0_0_i_41 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_128_n_0), .I2(\alu/data0 [11]), .I3(douta_reg_0_2), .I4(ALUSel[3]), .O(mem_reg_0_0_i_41_n_0)); LUT6 #( .INIT(64'hFFFFFFFF54040000)) mem_reg_0_0_i_42 (.I0(\f_ex_imm_reg[16] [1]), .I1(mem_reg_0_0_i_130_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_131_n_0), .I4(ALUSel[0]), .I5(mem_reg_0_0_i_132_n_0), .O(mem_reg_0_0_i_42_n_0)); LUT5 #( .INIT(32'h2B00FFFF)) mem_reg_0_0_i_43__0 (.I0(ALUSel[0]), .I1(a_mux[11]), .I2(b_mux[11]), .I3(ALUSel[1]), .I4(ALUSel[2]), .O(mem_reg_0_0_i_43__0_n_0)); LUT6 #( .INIT(64'h00000000FF470047)) mem_reg_0_0_i_45 (.I0(mem_reg_0_0_i_131_n_0), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_130_n_0), .I3(\f_ex_imm_reg[16] [1]), .I4(mem_reg_0_0_i_135_n_0), .I5(ALUSel[1]), .O(mem_reg_0_0_i_45_n_0)); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT3 #( .INIT(8'h5D)) mem_reg_0_0_i_46 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[11]), .O(mem_reg_0_0_i_46_n_0)); LUT6 #( .INIT(64'hFFFFFFFFBBB888B8)) mem_reg_0_0_i_48 (.I0(mem_reg_0_0_i_136_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(mem_reg_0_0_i_137_n_0), .I3(\f_ex_imm_reg[16] [0]), .I4(mem_reg_0_0_i_138_n_0), .I5(ALUSel[1]), .O(mem_reg_0_0_i_48_n_0)); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT3 #( .INIT(8'h5D)) mem_reg_0_0_i_49 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[10]), .O(mem_reg_0_0_i_49_n_0)); LUT6 #( .INIT(64'h88888888A8AAA8A8)) mem_reg_0_0_i_4__0 (.I0(mem_reg_0_0_i_85_n_0), .I1(mem_reg_0_0_i_86_n_0), .I2(mem_reg_0_0_i_87_n_0), .I3(mem_reg_0_0_i_88_n_0), .I4(ALUSel[0]), .I5(mem_reg_0_0_i_90_n_0), .O(ADDRARDADDR[0])); LUT6 #( .INIT(64'hAE00AE00AE00AEAE)) mem_reg_0_0_i_5 (.I0(mem_reg_0_0_i_41_n_0), .I1(mem_reg_0_0_i_42_n_0), .I2(mem_reg_0_0_i_43__0_n_0), .I3(douta_reg_0_5), .I4(mem_reg_0_0_i_45_n_0), .I5(mem_reg_0_0_i_46_n_0), .O(ex_alu[11])); LUT5 #( .INIT(32'hFFFF44F4)) mem_reg_0_0_i_50 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_140_n_0), .I2(\alu/data0 [10]), .I3(douta_reg_0_2), .I4(ALUSel[3]), .O(mem_reg_0_0_i_50_n_0)); LUT6 #( .INIT(64'h00000000DDDFFFDF)) mem_reg_0_0_i_51 (.I0(ALUSel[0]), .I1(\f_ex_imm_reg[16] [1]), .I2(mem_reg_0_0_i_137_n_0), .I3(\f_ex_imm_reg[16] [0]), .I4(mem_reg_0_0_i_138_n_0), .I5(mem_reg_0_0_i_141_n_0), .O(mem_reg_0_0_i_51_n_0)); LUT5 #( .INIT(32'h2B00FFFF)) mem_reg_0_0_i_52__0 (.I0(ALUSel[0]), .I1(a_mux[10]), .I2(b_mux[10]), .I3(ALUSel[1]), .I4(ALUSel[2]), .O(mem_reg_0_0_i_52__0_n_0)); LUT5 #( .INIT(32'hFFFF44F4)) mem_reg_0_0_i_53 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_143_n_0), .I2(\alu/data0 [9]), .I3(douta_reg_0_2), .I4(ALUSel[3]), .O(mem_reg_0_0_i_53_n_0)); LUT6 #( .INIT(64'h00000000FF70FF40)) mem_reg_0_0_i_54 (.I0(mem_reg_0_0_i_144_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(ALUSel[0]), .I3(mem_reg_0_0_i_145_n_0), .I4(mem_reg_0_0_i_146_n_0), .I5(mem_reg_0_0_i_147_n_0), .O(mem_reg_0_0_i_54_n_0)); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_56 (.CI(mem_reg_0_0_i_75_n_0), .CO({mem_reg_0_0_i_56_n_0,mem_reg_0_0_i_56_n_1,mem_reg_0_0_i_56_n_2,mem_reg_0_0_i_56_n_3}), .CYINIT(\<const0> ), .DI(a_mux[11:8]), .O({\f_ex_pc_reg[30]_0 [6:5],\alu/data8 [9:8]}), .S({mem_reg_0_0_i_150_n_0,mem_reg_0_0_i_151_n_0,mem_reg_0_0_i_152_n_0,mem_reg_0_0_i_153_n_0})); LUT6 #( .INIT(64'h00FF4747FFFFFFFF)) mem_reg_0_0_i_58 (.I0(mem_reg_0_0_i_155_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(mem_reg_0_0_i_146_n_0), .I3(b_mux[9]), .I4(ALUSel[1]), .I5(\wb_alu_reg[16] ), .O(mem_reg_0_0_i_58_n_0)); LUT5 #( .INIT(32'hFFFF44F4)) mem_reg_0_0_i_59 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_157_n_0), .I2(\alu/data0 [8]), .I3(douta_reg_0_2), .I4(ALUSel[3]), .O(mem_reg_0_0_i_59_n_0)); LUT6 #( .INIT(64'hAE00AE00AE00AEAE)) mem_reg_0_0_i_6 (.I0(douta_reg_0_9), .I1(mem_reg_0_0_i_48_n_0), .I2(mem_reg_0_0_i_49_n_0), .I3(mem_reg_0_0_i_50_n_0), .I4(mem_reg_0_0_i_51_n_0), .I5(mem_reg_0_0_i_52__0_n_0), .O(ex_alu[10])); LUT6 #( .INIT(64'h00000000FF70FF40)) mem_reg_0_0_i_60 (.I0(mem_reg_0_0_i_158_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(ALUSel[0]), .I3(mem_reg_0_0_i_159_n_0), .I4(mem_reg_0_0_i_160_n_0), .I5(mem_reg_0_0_i_161_n_0), .O(mem_reg_0_0_i_60_n_0)); LUT6 #( .INIT(64'h00FF4747FFFFFFFF)) mem_reg_0_0_i_61 (.I0(mem_reg_0_0_i_162_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(mem_reg_0_0_i_160_n_0), .I3(b_mux[8]), .I4(ALUSel[1]), .I5(\wb_alu_reg[16] ), .O(mem_reg_0_0_i_61_n_0)); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT4 #( .INIT(16'hFFFD)) mem_reg_0_0_i_62__0 (.I0(ALUSel[0]), .I1(\f_ex_imm_reg[16] [1]), .I2(ALUSel[2]), .I3(ALUSel[1]), .O(mem_reg_0_0_i_62__0_n_0)); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT4 #( .INIT(16'h00E2)) mem_reg_0_0_i_63 (.I0(mem_reg_0_0_i_164_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_166_n_0), .I3(\f_ex_imm_reg[16] [0]), .O(mem_reg_0_0_i_63_n_0)); LUT6 #( .INIT(64'hAAAAAA20AA20AA20)) mem_reg_0_0_i_65 (.I0(ALUSel[2]), .I1(mem_reg_0_0_i_168_n_0), .I2(mem_reg_0_0_i_169_n_0), .I3(mem_reg_0_0_i_170_n_0), .I4(mem_reg_0_0_i_171_n_0), .I5(mem_reg_0_0_i_172_n_0), .O(mem_reg_0_0_i_65_n_0)); LUT6 #( .INIT(64'h1013FFFFDCDFFFFF)) mem_reg_0_0_i_67 (.I0(mem_reg_0_0_i_173_n_0), .I1(ALUSel[1]), .I2(\f_ex_imm_reg[16] [1]), .I3(mem_reg_0_0_i_169_n_0), .I4(\wb_alu_reg[16] ), .I5(b_mux[7]), .O(mem_reg_0_0_i_67_n_0)); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT4 #( .INIT(16'h00E2)) mem_reg_0_0_i_68 (.I0(mem_reg_0_0_i_175_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_176_n_0), .I3(\f_ex_imm_reg[16] [0]), .O(mem_reg_0_0_i_68_n_0)); LUT6 #( .INIT(64'h0E00EEEEEEEEEEEE)) mem_reg_0_0_i_7 (.I0(mem_reg_0_0_i_53_n_0), .I1(mem_reg_0_0_i_54_n_0), .I2(douta_reg_0_2), .I3(\alu/data8 [9]), .I4(ALUSel[3]), .I5(mem_reg_0_0_i_58_n_0), .O(ex_alu[9])); LUT6 #( .INIT(64'hAAAAAA20AA20AA20)) mem_reg_0_0_i_70 (.I0(ALUSel[2]), .I1(mem_reg_0_0_i_168_n_0), .I2(mem_reg_0_0_i_177_n_0), .I3(mem_reg_0_0_i_178_n_0), .I4(mem_reg_0_0_i_179_n_0), .I5(mem_reg_0_0_i_172_n_0), .O(mem_reg_0_0_i_70_n_0)); LUT6 #( .INIT(64'h3F3F77333F3F77FF)) mem_reg_0_0_i_72 (.I0(mem_reg_0_0_i_180_n_0), .I1(\wb_alu_reg[16] ), .I2(b_mux[6]), .I3(\f_ex_imm_reg[16] [1]), .I4(ALUSel[1]), .I5(mem_reg_0_0_i_177_n_0), .O(mem_reg_0_0_i_72_n_0)); LUT6 #( .INIT(64'hFFFFFFFF0404FF04)) mem_reg_0_0_i_73 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_182_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(\alu/data0 [5]), .I4(douta_reg_0_2), .I5(ALUSel[3]), .O(mem_reg_0_0_i_73_n_0)); LUT6 #( .INIT(64'hAAAAAA20AA20AA20)) mem_reg_0_0_i_74 (.I0(ALUSel[2]), .I1(mem_reg_0_0_i_168_n_0), .I2(mem_reg_0_0_i_183_n_0), .I3(mem_reg_0_0_i_184_n_0), .I4(mem_reg_0_0_i_185_n_0), .I5(mem_reg_0_0_i_172_n_0), .O(mem_reg_0_0_i_74_n_0)); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_75 (.CI(mem_reg_0_0_i_83_n_0), .CO({mem_reg_0_0_i_75_n_0,mem_reg_0_0_i_75_n_1,mem_reg_0_0_i_75_n_2,mem_reg_0_0_i_75_n_3}), .CYINIT(\<const0> ), .DI(a_mux[7:4]), .O({\f_ex_pc_reg[30]_0 [4:3],\alu/data8 [5],\f_ex_pc_reg[30]_0 [2]}), .S({mem_reg_0_0_i_190_n_0,mem_reg_0_0_i_191_n_0,mem_reg_0_0_i_192_n_0,mem_reg_0_0_i_193_n_0})); LUT6 #( .INIT(64'h3F333F773FFF3F77)) mem_reg_0_0_i_76 (.I0(mem_reg_0_0_i_183_n_0), .I1(\wb_alu_reg[16] ), .I2(b_mux[5]), .I3(ALUSel[1]), .I4(\f_ex_imm_reg[16] [1]), .I5(mem_reg_0_0_i_195_n_0), .O(mem_reg_0_0_i_76_n_0)); LUT5 #( .INIT(32'hFFFF44F4)) mem_reg_0_0_i_77 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_196_n_0), .I2(\alu/data0 [4]), .I3(douta_reg_0_2), .I4(ALUSel[3]), .O(mem_reg_0_0_i_77_n_0)); LUT6 #( .INIT(64'h0F0053F0FF0F530F)) mem_reg_0_0_i_79 (.I0(mem_reg_0_0_i_197_n_0), .I1(mem_reg_0_0_i_198_n_0), .I2(\f_ex_imm_reg[16] [1]), .I3(ALUSel[0]), .I4(ALUSel[1]), .I5(a_mux[4]), .O(mem_reg_0_0_i_79_n_0)); LUT6 #( .INIT(64'h0E00EEEEEEEEEEEE)) mem_reg_0_0_i_8 (.I0(mem_reg_0_0_i_59_n_0), .I1(mem_reg_0_0_i_60_n_0), .I2(douta_reg_0_2), .I3(\alu/data8 [8]), .I4(ALUSel[3]), .I5(mem_reg_0_0_i_61_n_0), .O(ex_alu[8])); LUT6 #( .INIT(64'h000000005D7D5F7F)) mem_reg_0_0_i_80 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(\f_ex_imm_reg[16] [1]), .I3(mem_reg_0_0_i_199_n_0), .I4(mem_reg_0_0_i_198_n_0), .I5(douta_reg_1_1), .O(mem_reg_0_0_i_80_n_0)); LUT5 #( .INIT(32'hFFFF44F4)) mem_reg_0_0_i_81 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_201_n_0), .I2(\alu/data0 [3]), .I3(douta_reg_0_2), .I4(ALUSel[3]), .O(mem_reg_0_0_i_81_n_0)); LUT6 #( .INIT(64'h00000000FFC4FF80)) mem_reg_0_0_i_82 (.I0(\f_ex_imm_reg[16] [1]), .I1(ALUSel[0]), .I2(mem_reg_0_0_i_203_n_0), .I3(mem_reg_0_0_i_204_n_0), .I4(mem_reg_0_0_i_205_n_0), .I5(mem_reg_0_0_i_206_n_0), .O(mem_reg_0_0_i_82_n_0)); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_83 (.CI(\<const0> ), .CO({mem_reg_0_0_i_83_n_0,mem_reg_0_0_i_83_n_1,mem_reg_0_0_i_83_n_2,mem_reg_0_0_i_83_n_3}), .CYINIT(\<const1> ), .DI(a_mux[3:0]), .O({\alu/data8 [3],\f_ex_pc_reg[30]_0 [1:0],\alu/data8 [0]}), .S({mem_reg_0_0_i_211_n_0,mem_reg_0_0_i_212_n_0,mem_reg_0_0_i_213_n_0,mem_reg_0_0_i_214_n_0})); LUT6 #( .INIT(64'h010DFFFFF1FDFFFF)) mem_reg_0_0_i_84 (.I0(mem_reg_0_0_i_205_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(ALUSel[1]), .I3(mem_reg_0_0_i_215_n_0), .I4(\wb_alu_reg[16] ), .I5(\f_ex_imm_reg[16] [0]), .O(mem_reg_0_0_i_84_n_0)); LUT6 #( .INIT(64'hFFFFFFFF55554540)) mem_reg_0_0_i_85 (.I0(mem_reg_0_0_i_216_n_0), .I1(mem_reg_0_0_i_217_n_0), .I2(\f_ex_imm_reg[16] [1]), .I3(mem_reg_0_0_i_218_n_0), .I4(ALUSel[1]), .I5(mem_reg_2_2), .O(mem_reg_0_0_i_85_n_0)); LUT6 #( .INIT(64'hFFFFFFFF0202FF02)) mem_reg_0_0_i_86 (.I0(mem_reg_0_0_i_220_n_0), .I1(\f_ex_imm_reg[16] [0]), .I2(mem_reg_0_0_i_62__0_n_0), .I3(\alu/data0 [2]), .I4(douta_reg_0_2), .I5(ALUSel[3]), .O(mem_reg_0_0_i_86_n_0)); LUT6 #( .INIT(64'hFFFFFFFF888F8F88)) mem_reg_0_0_i_87 (.I0(\wb_alu[0]_i_3_n_0 ), .I1(mem_reg_0_0_i_221_n_0), .I2(ALUSel[0]), .I3(b_mux[2]), .I4(a_mux[2]), .I5(ALUSel[1]), .O(mem_reg_0_0_i_87_n_0)); LUT6 #( .INIT(64'hAAAAABFBFFFFABFB)) mem_reg_0_0_i_88 (.I0(\f_ex_imm_reg[16] [1]), .I1(mem_reg_0_0_i_222_n_0), .I2(b_mux[2]), .I3(mem_reg_0_0_i_223_n_0), .I4(\f_ex_imm_reg[16] [0]), .I5(mem_reg_0_0_i_137_n_0), .O(mem_reg_0_0_i_88_n_0)); LUT6 #( .INIT(64'hFFF40000FFF4FFF4)) mem_reg_0_0_i_9 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_63_n_0), .I2(douta_reg_0_3), .I3(mem_reg_0_0_i_65_n_0), .I4(douta_reg_0_4), .I5(mem_reg_0_0_i_67_n_0), .O(ex_alu[7])); LUT5 #( .INIT(32'h2B00FFFF)) mem_reg_0_0_i_90 (.I0(ALUSel[0]), .I1(b_mux[2]), .I2(a_mux[2]), .I3(ALUSel[1]), .I4(ALUSel[2]), .O(mem_reg_0_0_i_90_n_0)); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT5 #( .INIT(32'h00000F11)) mem_reg_0_0_i_91 (.I0(ex_alu[0]), .I1(ex_alu[1]), .I2(mem_reg_2_0[2]), .I3(mem_reg_2_0[3]), .I4(mem_reg_2_0[4]), .O(mem_reg_0_0_i_91_n_0)); LUT5 #( .INIT(32'hF4FFF400)) mem_reg_0_0_i_92 (.I0(\pprev_data_reg[0] ), .I1(ld_data[1]), .I2(\pprev_data_reg[1] ), .I3(mem_reg_1_0), .I4(mem_reg_1_0_1), .O(fwd_b[1])); LUT5 #( .INIT(32'hF4FFF400)) mem_reg_0_0_i_93 (.I0(\pprev_data_reg[0] ), .I1(ld_data[0]), .I2(\pprev_data_reg[0]_0 ), .I3(mem_reg_1_0), .I4(mem_reg_1_0_0), .O(fwd_b[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_0_0_i_95 (.I0(mem_reg_0_0_i_166_n_0), .I1(mem_reg_0_0_i_164_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_230_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_231_n_0), .O(mem_reg_0_0_i_95_n_0)); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_96 (.CI(mem_reg_0_0_i_129_n_0), .CO({mem_reg_0_0_i_96_n_0,mem_reg_0_0_i_96_n_1,mem_reg_0_0_i_96_n_2,mem_reg_0_0_i_96_n_3}), .CYINIT(\<const0> ), .DI(a_mux[15:12]), .O(\alu/data0 [15:12]), .S({mem_reg_0_0_i_232_n_0,mem_reg_0_0_i_233_n_0,mem_reg_0_0_i_234_n_0,mem_reg_0_0_i_235_n_0})); (* SOFT_HLUTNM = "soft_lutpair88" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_97 (.I0(mem_reg_0_0_i_236_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_237_n_0), .O(mem_reg_0_0_i_97_n_0)); LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_98 (.I0(Q[3]), .I1(BSel), .I2(fwd_b[3]), .O(\f_ex_imm_reg[16] [0])); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_0_i_99 (.I0(mem_reg_0_0_i_239_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_240_n_0), .O(mem_reg_0_0_i_99_n_0)); LUT2 #( .INIT(4'h8)) mem_reg_0_1_i_1 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[3]), .O(p_1_in[3])); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_0_1_i_10 (.I0(mem_reg_r1_0_31_6_11_i_21_0), .I1(mem_reg_r1_0_31_6_11_i_54_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_reg_0_1_i_7_0), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_r1_0_31_0_5_i_41_n_0), .O(mem_reg_0_1_i_10_n_0)); LUT2 #( .INIT(4'h8)) mem_reg_0_1_i_2 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[2]), .O(p_1_in[2])); LUT5 #( .INIT(32'hF4FFF400)) mem_reg_0_1_i_3 (.I0(\pprev_data_reg[0] ), .I1(ld_data[3]), .I2(\pprev_data_reg[3] ), .I3(mem_reg_1_0), .I4(mem_reg_1_1_0), .O(fwd_b[3])); LUT5 #( .INIT(32'hF4FFF400)) mem_reg_0_1_i_4 (.I0(\pprev_data_reg[0] ), .I1(ld_data[2]), .I2(\pprev_data_reg[2] ), .I3(mem_reg_1_0), .I4(mem_reg_1_1), .O(fwd_b[2])); LUT6 #( .INIT(64'h1F001F1F1F000000)) mem_reg_0_1_i_5 (.I0(\pprev_data_reg[0]_1 [2]), .I1(\pprev_data_reg[0]_1 [0]), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_0_5_i_34_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(mem_reg_0_1_i_9_n_0), .O(ld_data[3])); LUT6 #( .INIT(64'h1F001F1F1F000000)) mem_reg_0_1_i_7 (.I0(\pprev_data_reg[0]_1 [2]), .I1(\pprev_data_reg[0]_1 [0]), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_0_5_i_38_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(mem_reg_0_1_i_10_n_0), .O(ld_data[2])); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_0_1_i_9 (.I0(mem_reg_r1_0_31_6_11_i_18_0), .I1(mem_reg_r1_0_31_6_11_i_53_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_reg_0_1_i_5_0), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_r1_0_31_0_5_i_37_n_0), .O(mem_reg_0_1_i_9_n_0)); LUT6 #( .INIT(64'hAE00AE00AE00AEAE)) mem_reg_0_2_i_1 (.I0(mem_reg_0_0_i_29_n_0), .I1(mem_reg_0_0_i_30_n_0), .I2(mem_reg_0_0_i_31__0_n_0), .I3(mem_reg_3_3_1), .I4(mem_reg_0_0_i_33_n_0), .I5(mem_reg_0_0_i_34_n_0), .O(ex_alu[13])); LUT2 #( .INIT(4'h8)) mem_reg_0_2_i_2 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[5]), .O(p_1_in[5])); LUT2 #( .INIT(4'h8)) mem_reg_0_2_i_3 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[4]), .O(p_1_in[4])); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_2_i_4 (.I0(wb_mux[5]), .I1(mem_reg_1_0), .I2(mem_reg_1_2_0), .O(fwd_b[5])); LUT5 #( .INIT(32'hF4FFF400)) mem_reg_0_2_i_5 (.I0(\pprev_data_reg[0] ), .I1(ld_data[4]), .I2(\pprev_data_reg[4] ), .I3(mem_reg_1_0), .I4(mem_reg_1_2), .O(fwd_b[4])); LUT6 #( .INIT(64'h1F001F1F1F000000)) mem_reg_0_2_i_7 (.I0(\pprev_data_reg[0]_1 [2]), .I1(\pprev_data_reg[0]_1 [0]), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_0_5_i_46_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(mem_reg_0_2_i_9_n_0), .O(ld_data[4])); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_0_2_i_9 (.I0(mem_reg_r1_0_31_12_17_i_11_0), .I1(mem_reg_r1_0_31_12_17_i_31_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_reg_0_2_i_7_0), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_r1_0_31_0_5_i_49_n_0), .O(mem_reg_0_2_i_9_n_0)); LUT2 #( .INIT(4'h8)) mem_reg_0_3_i_1 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[7]), .O(p_1_in[7])); LUT2 #( .INIT(4'h8)) mem_reg_0_3_i_2 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[6]), .O(p_1_in[6])); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_3_i_3 (.I0(wb_mux[7]), .I1(mem_reg_1_0), .I2(mem_reg_1_3_0), .O(fwd_b[7])); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT3 #( .INIT(8'hB8)) mem_reg_0_3_i_4 (.I0(wb_mux[6]), .I1(mem_reg_1_0), .I2(mem_reg_1_3), .O(fwd_b[6])); LUT5 #( .INIT(32'hFF202020)) mem_reg_1_0_i_1 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(fwd_b[1]), .I3(fwd_b[9]), .I4(mem_reg_1_0_i_6_n_0), .O(p_1_in[9])); LUT5 #( .INIT(32'h00100000)) mem_reg_1_0_i_1__0 (.I0(ex_alu[30]), .I1(mem_reg_2_3), .I2(mem_reg_1_0_i_8_n_0), .I3(ex_alu[1]), .I4(ex_alu[29]), .O(imem_wea[1])); LUT5 #( .INIT(32'hFF202020)) mem_reg_1_0_i_2 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(fwd_b[0]), .I3(fwd_b[8]), .I4(mem_reg_1_0_i_6_n_0), .O(p_1_in[8])); LUT5 #( .INIT(32'h00001000)) mem_reg_1_0_i_3 (.I0(ex_alu[30]), .I1(mem_reg_2_3), .I2(ex_alu[28]), .I3(mem_reg_1_0_i_8_n_0), .I4(ex_alu[1]), .O(dmem_we[1])); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT3 #( .INIT(8'h10)) mem_reg_1_0_i_4 (.I0(mem_reg_2_0[4]), .I1(mem_reg_2_0[3]), .I2(ex_alu[0]), .O(mem_reg_1_0_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT3 #( .INIT(8'hB8)) mem_reg_1_0_i_5 (.I0(wb_mux[9]), .I1(mem_reg_1_0), .I2(mem_reg_1_0_3), .O(fwd_b[9])); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT5 #( .INIT(32'h00000F10)) mem_reg_1_0_i_6 (.I0(ex_alu[0]), .I1(ex_alu[1]), .I2(mem_reg_2_0[2]), .I3(mem_reg_2_0[3]), .I4(mem_reg_2_0[4]), .O(mem_reg_1_0_i_6_n_0)); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT3 #( .INIT(8'hB8)) mem_reg_1_0_i_7 (.I0(wb_mux[8]), .I1(mem_reg_1_0), .I2(mem_reg_1_0_2), .O(fwd_b[8])); LUT6 #( .INIT(64'h0000033200000000)) mem_reg_1_0_i_8 (.I0(ex_alu[0]), .I1(mem_reg_1_3_3), .I2(mem_reg_2_0[3]), .I3(mem_reg_2_0[2]), .I4(mem_reg_2_0[4]), .I5(mem_reg_3_3_5), .O(mem_reg_1_0_i_8_n_0)); LUT5 #( .INIT(32'hFF202020)) mem_reg_1_1_i_1 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(fwd_b[3]), .I3(fwd_b[11]), .I4(mem_reg_1_0_i_6_n_0), .O(p_1_in[11])); LUT5 #( .INIT(32'hFF202020)) mem_reg_1_1_i_2 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(fwd_b[2]), .I3(fwd_b[10]), .I4(mem_reg_1_0_i_6_n_0), .O(p_1_in[10])); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT3 #( .INIT(8'hB8)) mem_reg_1_1_i_3 (.I0(wb_mux[11]), .I1(mem_reg_1_0), .I2(mem_reg_1_1_2), .O(fwd_b[11])); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT3 #( .INIT(8'hB8)) mem_reg_1_1_i_4 (.I0(wb_mux[10]), .I1(mem_reg_1_0), .I2(mem_reg_1_1_1), .O(fwd_b[10])); LUT5 #( .INIT(32'hFF202020)) mem_reg_1_2_i_1 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(fwd_b[5]), .I3(fwd_b[13]), .I4(mem_reg_1_0_i_6_n_0), .O(p_1_in[13])); LUT5 #( .INIT(32'hFF202020)) mem_reg_1_2_i_2 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(fwd_b[4]), .I3(fwd_b[12]), .I4(mem_reg_1_0_i_6_n_0), .O(p_1_in[12])); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT3 #( .INIT(8'hB8)) mem_reg_1_2_i_3 (.I0(wb_mux[13]), .I1(mem_reg_1_0), .I2(mem_reg_1_2_2), .O(fwd_b[13])); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT3 #( .INIT(8'hB8)) mem_reg_1_2_i_4 (.I0(wb_mux[12]), .I1(mem_reg_1_0), .I2(mem_reg_1_2_1), .O(fwd_b[12])); LUT5 #( .INIT(32'hFF202020)) mem_reg_1_3_i_1 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(fwd_b[7]), .I3(fwd_b[15]), .I4(mem_reg_1_0_i_6_n_0), .O(p_1_in[15])); LUT5 #( .INIT(32'hFF202020)) mem_reg_1_3_i_2 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(fwd_b[6]), .I3(fwd_b[14]), .I4(mem_reg_1_0_i_6_n_0), .O(p_1_in[14])); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT3 #( .INIT(8'hB8)) mem_reg_1_3_i_3 (.I0(wb_mux[15]), .I1(mem_reg_1_0), .I2(mem_reg_1_3_2), .O(fwd_b[15])); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT3 #( .INIT(8'hB8)) mem_reg_1_3_i_4 (.I0(wb_mux[14]), .I1(mem_reg_1_0), .I2(mem_reg_1_3_1), .O(fwd_b[14])); LUT6 #( .INIT(64'hAE00AE00AE00AEAE)) mem_reg_2_0_i_1 (.I0(mem_reg_0_0_i_35_n_0), .I1(mem_reg_0_0_i_36_n_0), .I2(mem_reg_0_0_i_37__0_n_0), .I3(douta_reg_0_6), .I4(mem_reg_0_0_i_39_n_0), .I5(mem_reg_0_0_i_40_n_0), .O(ADDRARDADDR[10])); LUT5 #( .INIT(32'hF2F0F0F0)) mem_reg_2_0_i_10 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(mem_reg_2_0_i_13_n_0), .I3(fwd_b[9]), .I4(mem_reg_2_0[2]), .O(p_1_in[17])); LUT5 #( .INIT(32'hF2F0F0F0)) mem_reg_2_0_i_11 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(mem_reg_2_0_i_14_n_0), .I3(fwd_b[8]), .I4(mem_reg_2_0[2]), .O(p_1_in[16])); LUT4 #( .INIT(16'h0010)) mem_reg_2_0_i_12 (.I0(ex_alu[30]), .I1(mem_reg_2_3), .I2(ex_alu[28]), .I3(mem_reg_2_0_i_15_n_0), .O(dmem_we[2])); LUT6 #( .INIT(64'h8888888888F88888)) mem_reg_2_0_i_13 (.I0(fwd_b[1]), .I1(mem_reg_2_0_i_16_n_0), .I2(fwd_b[17]), .I3(mem_reg_2_0[2]), .I4(mem_reg_2_0[3]), .I5(mem_reg_2_0[4]), .O(mem_reg_2_0_i_13_n_0)); LUT6 #( .INIT(64'h8888888888F88888)) mem_reg_2_0_i_14 (.I0(fwd_b[0]), .I1(mem_reg_2_0_i_16_n_0), .I2(fwd_b[16]), .I3(mem_reg_2_0[2]), .I4(mem_reg_2_0[3]), .I5(mem_reg_2_0[4]), .O(mem_reg_2_0_i_14_n_0)); LUT5 #( .INIT(32'hF035FF35)) mem_reg_2_0_i_15 (.I0(MemRW[2]), .I1(MemRW[0]), .I2(ex_alu[1]), .I3(ex_alu[0]), .I4(MemRW[1]), .O(mem_reg_2_0_i_15_n_0)); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT4 #( .INIT(16'h0004)) mem_reg_2_0_i_16 (.I0(ex_alu[0]), .I1(ex_alu[1]), .I2(mem_reg_2_0[4]), .I3(mem_reg_2_0[3]), .O(mem_reg_2_0_i_16_n_0)); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT3 #( .INIT(8'hB8)) mem_reg_2_0_i_17 (.I0(wb_mux[17]), .I1(mem_reg_1_0), .I2(mem_reg_2_0_i_13_0), .O(fwd_b[17])); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT3 #( .INIT(8'hB8)) mem_reg_2_0_i_18 (.I0(wb_mux[16]), .I1(mem_reg_1_0), .I2(mem_reg_2_0_i_14_0), .O(fwd_b[16])); LUT4 #( .INIT(16'h0010)) mem_reg_2_0_i_1__0 (.I0(ex_alu[30]), .I1(mem_reg_2_3), .I2(ex_alu[29]), .I3(mem_reg_2_0_i_15_n_0), .O(imem_wea[2])); LUT6 #( .INIT(64'hAE00AE00AE00AEAE)) mem_reg_2_0_i_2 (.I0(mem_reg_0_0_i_41_n_0), .I1(mem_reg_0_0_i_42_n_0), .I2(mem_reg_0_0_i_43__0_n_0), .I3(douta_reg_0_5), .I4(mem_reg_0_0_i_45_n_0), .I5(mem_reg_0_0_i_46_n_0), .O(ADDRARDADDR[9])); LUT6 #( .INIT(64'hAE00AE00AE00AEAE)) mem_reg_2_0_i_3 (.I0(douta_reg_0_9), .I1(mem_reg_0_0_i_48_n_0), .I2(mem_reg_0_0_i_49_n_0), .I3(mem_reg_0_0_i_50_n_0), .I4(mem_reg_0_0_i_51_n_0), .I5(mem_reg_0_0_i_52__0_n_0), .O(ADDRARDADDR[8])); LUT6 #( .INIT(64'h0E00EEEEEEEEEEEE)) mem_reg_2_0_i_4 (.I0(mem_reg_0_0_i_53_n_0), .I1(mem_reg_0_0_i_54_n_0), .I2(douta_reg_0_2), .I3(\alu/data8 [9]), .I4(ALUSel[3]), .I5(mem_reg_0_0_i_58_n_0), .O(ADDRARDADDR[7])); LUT6 #( .INIT(64'h0E00EEEEEEEEEEEE)) mem_reg_2_0_i_5 (.I0(mem_reg_0_0_i_59_n_0), .I1(mem_reg_0_0_i_60_n_0), .I2(douta_reg_0_2), .I3(\alu/data8 [8]), .I4(ALUSel[3]), .I5(mem_reg_0_0_i_61_n_0), .O(ADDRARDADDR[6])); LUT6 #( .INIT(64'hFFF40000FFF4FFF4)) mem_reg_2_0_i_6 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_63_n_0), .I2(douta_reg_0_3), .I3(mem_reg_0_0_i_65_n_0), .I4(douta_reg_0_4), .I5(mem_reg_0_0_i_67_n_0), .O(ADDRARDADDR[5])); LUT6 #( .INIT(64'hFFF40000FFF4FFF4)) mem_reg_2_0_i_7 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(mem_reg_0_0_i_68_n_0), .I2(douta_reg_0_7), .I3(mem_reg_0_0_i_70_n_0), .I4(douta_reg_0_8), .I5(mem_reg_0_0_i_72_n_0), .O(ADDRARDADDR[4])); LUT6 #( .INIT(64'h0E00EEEEEEEEEEEE)) mem_reg_2_0_i_8 (.I0(mem_reg_0_0_i_73_n_0), .I1(mem_reg_0_0_i_74_n_0), .I2(douta_reg_0_2), .I3(\alu/data8 [5]), .I4(ALUSel[3]), .I5(mem_reg_0_0_i_76_n_0), .O(ADDRARDADDR[3])); LUT4 #( .INIT(16'h00AE)) mem_reg_2_0_i_9 (.I0(mem_reg_0_0_i_77_n_0), .I1(ALUSel[2]), .I2(mem_reg_0_0_i_79_n_0), .I3(mem_reg_0_0_i_80_n_0), .O(ADDRARDADDR[2])); LUT5 #( .INIT(32'hF2F0F0F0)) mem_reg_2_1_i_1 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(mem_reg_2_1_i_3_n_0), .I3(fwd_b[11]), .I4(mem_reg_2_0[2]), .O(p_1_in[19])); LUT5 #( .INIT(32'hF2F0F0F0)) mem_reg_2_1_i_2 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(mem_reg_2_1_i_4_n_0), .I3(fwd_b[10]), .I4(mem_reg_2_0[2]), .O(p_1_in[18])); LUT6 #( .INIT(64'h8888888888F88888)) mem_reg_2_1_i_3 (.I0(fwd_b[3]), .I1(mem_reg_2_0_i_16_n_0), .I2(fwd_b[19]), .I3(mem_reg_2_0[2]), .I4(mem_reg_2_0[3]), .I5(mem_reg_2_0[4]), .O(mem_reg_2_1_i_3_n_0)); LUT6 #( .INIT(64'h8888888888F88888)) mem_reg_2_1_i_4 (.I0(fwd_b[2]), .I1(mem_reg_2_0_i_16_n_0), .I2(fwd_b[18]), .I3(mem_reg_2_0[2]), .I4(mem_reg_2_0[3]), .I5(mem_reg_2_0[4]), .O(mem_reg_2_1_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT3 #( .INIT(8'hB8)) mem_reg_2_1_i_5 (.I0(wb_mux[19]), .I1(mem_reg_1_0), .I2(mem_reg_2_1_i_3_0), .O(fwd_b[19])); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT3 #( .INIT(8'hB8)) mem_reg_2_1_i_6 (.I0(wb_mux[18]), .I1(mem_reg_1_0), .I2(mem_reg_2_1_i_4_0), .O(fwd_b[18])); LUT6 #( .INIT(64'h0E00EEEEEEEEEEEE)) mem_reg_2_2_i_1 (.I0(mem_reg_0_0_i_81_n_0), .I1(mem_reg_0_0_i_82_n_0), .I2(douta_reg_0_2), .I3(\alu/data8 [3]), .I4(ALUSel[3]), .I5(mem_reg_0_0_i_84_n_0), .O(addra[1])); LUT6 #( .INIT(64'h0E00EEEEEEEEEEEE)) mem_reg_2_2_i_1__0 (.I0(mem_reg_0_0_i_81_n_0), .I1(mem_reg_0_0_i_82_n_0), .I2(douta_reg_0_2), .I3(\alu/data8 [3]), .I4(ALUSel[3]), .I5(mem_reg_0_0_i_84_n_0), .O(addr[1])); LUT6 #( .INIT(64'h88888888A8AAA8A8)) mem_reg_2_2_i_2 (.I0(mem_reg_0_0_i_85_n_0), .I1(mem_reg_0_0_i_86_n_0), .I2(mem_reg_0_0_i_87_n_0), .I3(mem_reg_0_0_i_88_n_0), .I4(ALUSel[0]), .I5(mem_reg_0_0_i_90_n_0), .O(addra[0])); LUT6 #( .INIT(64'h88888888A8AAA8A8)) mem_reg_2_2_i_2__0 (.I0(mem_reg_0_0_i_85_n_0), .I1(mem_reg_0_0_i_86_n_0), .I2(mem_reg_0_0_i_87_n_0), .I3(mem_reg_0_0_i_88_n_0), .I4(ALUSel[0]), .I5(mem_reg_0_0_i_90_n_0), .O(addr[0])); LUT5 #( .INIT(32'hF2F0F0F0)) mem_reg_2_2_i_3 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(mem_reg_2_2_i_5_n_0), .I3(fwd_b[13]), .I4(mem_reg_2_0[2]), .O(p_1_in[21])); LUT5 #( .INIT(32'hF2F0F0F0)) mem_reg_2_2_i_4 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(mem_reg_2_2_i_6_n_0), .I3(fwd_b[12]), .I4(mem_reg_2_0[2]), .O(p_1_in[20])); LUT6 #( .INIT(64'h8888888888F88888)) mem_reg_2_2_i_5 (.I0(fwd_b[5]), .I1(mem_reg_2_0_i_16_n_0), .I2(fwd_b[21]), .I3(mem_reg_2_0[2]), .I4(mem_reg_2_0[3]), .I5(mem_reg_2_0[4]), .O(mem_reg_2_2_i_5_n_0)); LUT6 #( .INIT(64'h8888888888F88888)) mem_reg_2_2_i_6 (.I0(fwd_b[4]), .I1(mem_reg_2_0_i_16_n_0), .I2(fwd_b[20]), .I3(mem_reg_2_0[2]), .I4(mem_reg_2_0[3]), .I5(mem_reg_2_0[4]), .O(mem_reg_2_2_i_6_n_0)); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT3 #( .INIT(8'hB8)) mem_reg_2_2_i_7 (.I0(wb_mux[21]), .I1(mem_reg_1_0), .I2(mem_reg_2_2_i_5_0), .O(fwd_b[21])); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT3 #( .INIT(8'hB8)) mem_reg_2_2_i_8 (.I0(wb_mux[20]), .I1(mem_reg_1_0), .I2(mem_reg_2_2_i_6_0), .O(fwd_b[20])); LUT5 #( .INIT(32'hF2F0F0F0)) mem_reg_2_3_i_1 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(mem_reg_2_3_i_3_n_0), .I3(fwd_b[15]), .I4(mem_reg_2_0[2]), .O(p_1_in[23])); LUT5 #( .INIT(32'hF2F0F0F0)) mem_reg_2_3_i_2 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .I2(mem_reg_2_3_i_4_n_0), .I3(fwd_b[14]), .I4(mem_reg_2_0[2]), .O(p_1_in[22])); LUT6 #( .INIT(64'h8888888888F88888)) mem_reg_2_3_i_3 (.I0(fwd_b[7]), .I1(mem_reg_2_0_i_16_n_0), .I2(fwd_b[23]), .I3(mem_reg_2_0[2]), .I4(mem_reg_2_0[3]), .I5(mem_reg_2_0[4]), .O(mem_reg_2_3_i_3_n_0)); LUT6 #( .INIT(64'h8888888888F88888)) mem_reg_2_3_i_4 (.I0(fwd_b[6]), .I1(mem_reg_2_0_i_16_n_0), .I2(fwd_b[22]), .I3(mem_reg_2_0[2]), .I4(mem_reg_2_0[3]), .I5(mem_reg_2_0[4]), .O(mem_reg_2_3_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT3 #( .INIT(8'hB8)) mem_reg_2_3_i_5 (.I0(wb_mux[23]), .I1(mem_reg_1_0), .I2(mem_reg_2_3_i_3_0), .O(fwd_b[23])); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT3 #( .INIT(8'hB8)) mem_reg_2_3_i_6 (.I0(wb_mux[22]), .I1(mem_reg_1_0), .I2(mem_reg_2_3_i_4_0), .O(fwd_b[22])); LUT6 #( .INIT(64'hFFFFF888F888F888)) mem_reg_3_0_i_1 (.I0(mem_reg_3_0_1), .I1(fwd_b[25]), .I2(mem_reg_3_0_i_6_n_0), .I3(fwd_b[9]), .I4(fwd_b[1]), .I5(mem_reg_3_0_i_7_n_0), .O(p_1_in[25])); LUT4 #( .INIT(16'h1000)) mem_reg_3_0_i_1__0 (.I0(ex_alu[30]), .I1(mem_reg_2_3), .I2(ex_alu[29]), .I3(mem_reg_3_0_i_9_n_0), .O(imem_wea[3])); LUT6 #( .INIT(64'hFFFFF888F888F888)) mem_reg_3_0_i_2 (.I0(mem_reg_3_0_1), .I1(fwd_b[24]), .I2(mem_reg_3_0_i_6_n_0), .I3(fwd_b[8]), .I4(fwd_b[0]), .I5(mem_reg_3_0_i_7_n_0), .O(p_1_in[24])); LUT4 #( .INIT(16'h1000)) mem_reg_3_0_i_3 (.I0(ex_alu[30]), .I1(mem_reg_2_3), .I2(ex_alu[28]), .I3(mem_reg_3_0_i_9_n_0), .O(dmem_we[3])); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT3 #( .INIT(8'hB8)) mem_reg_3_0_i_5 (.I0(wb_mux[25]), .I1(mem_reg_1_0), .I2(mem_reg_3_0_0), .O(fwd_b[25])); LUT2 #( .INIT(4'h8)) mem_reg_3_0_i_6 (.I0(mem_reg_2_0_i_16_n_0), .I1(mem_reg_2_0[2]), .O(mem_reg_3_0_i_6_n_0)); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT2 #( .INIT(4'h8)) mem_reg_3_0_i_7 (.I0(mem_reg_1_0_i_4_n_0), .I1(ex_alu[1]), .O(mem_reg_3_0_i_7_n_0)); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT3 #( .INIT(8'hB8)) mem_reg_3_0_i_8 (.I0(wb_mux[24]), .I1(mem_reg_1_0), .I2(mem_reg_3_0), .O(fwd_b[24])); LUT6 #( .INIT(64'h888B888888888888)) mem_reg_3_0_i_9 (.I0(mem_reg_1_0_i_8_n_0), .I1(ex_alu[1]), .I2(mem_reg_2_0[0]), .I3(mem_reg_2_0[1]), .I4(mem_reg_3_3_4), .I5(mem_reg_3_3_5), .O(mem_reg_3_0_i_9_n_0)); LUT6 #( .INIT(64'hFFFFF888F888F888)) mem_reg_3_1_i_1 (.I0(mem_reg_3_0_1), .I1(fwd_b[27]), .I2(mem_reg_3_0_i_6_n_0), .I3(fwd_b[11]), .I4(fwd_b[3]), .I5(mem_reg_3_0_i_7_n_0), .O(p_1_in[27])); LUT6 #( .INIT(64'hFFFFF888F888F888)) mem_reg_3_1_i_2 (.I0(mem_reg_3_0_1), .I1(fwd_b[26]), .I2(mem_reg_3_0_i_6_n_0), .I3(fwd_b[10]), .I4(fwd_b[2]), .I5(mem_reg_3_0_i_7_n_0), .O(p_1_in[26])); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT3 #( .INIT(8'hB8)) mem_reg_3_1_i_3 (.I0(wb_mux[27]), .I1(mem_reg_1_0), .I2(mem_reg_3_1_0), .O(fwd_b[27])); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT3 #( .INIT(8'hB8)) mem_reg_3_1_i_4 (.I0(wb_mux[26]), .I1(mem_reg_1_0), .I2(mem_reg_3_1), .O(fwd_b[26])); LUT6 #( .INIT(64'hFFFFF888F888F888)) mem_reg_3_2_i_1 (.I0(mem_reg_3_0_1), .I1(fwd_b[29]), .I2(mem_reg_3_0_i_6_n_0), .I3(fwd_b[13]), .I4(fwd_b[5]), .I5(mem_reg_3_0_i_7_n_0), .O(p_1_in[29])); LUT6 #( .INIT(64'hFFFFF888F888F888)) mem_reg_3_2_i_2 (.I0(mem_reg_3_0_1), .I1(fwd_b[28]), .I2(mem_reg_3_0_i_6_n_0), .I3(fwd_b[12]), .I4(fwd_b[4]), .I5(mem_reg_3_0_i_7_n_0), .O(p_1_in[28])); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT3 #( .INIT(8'hB8)) mem_reg_3_2_i_3 (.I0(wb_mux[29]), .I1(mem_reg_1_0), .I2(mem_reg_3_2_0), .O(fwd_b[29])); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT3 #( .INIT(8'hB8)) mem_reg_3_2_i_4 (.I0(wb_mux[28]), .I1(mem_reg_1_0), .I2(mem_reg_3_2), .O(fwd_b[28])); LUT6 #( .INIT(64'hFFFFF888F888F888)) mem_reg_3_3_i_1 (.I0(mem_reg_3_0_1), .I1(mem_reg_3_3), .I2(mem_reg_3_0_i_6_n_0), .I3(fwd_b[15]), .I4(fwd_b[7]), .I5(mem_reg_3_0_i_7_n_0), .O(p_1_in[31])); LUT6 #( .INIT(64'hFFFFF888F888F888)) mem_reg_3_3_i_2 (.I0(mem_reg_3_0_1), .I1(fwd_b[30]), .I2(mem_reg_3_0_i_6_n_0), .I3(fwd_b[14]), .I4(fwd_b[6]), .I5(mem_reg_3_0_i_7_n_0), .O(p_1_in[30])); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT3 #( .INIT(8'hB8)) mem_reg_3_3_i_4 (.I0(wb_mux[30]), .I1(mem_reg_1_0), .I2(mem_reg_3_3_0), .O(fwd_b[30])); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_r1_0_31_0_5_i_14 (.I0(mem_reg_r1_0_31_0_5_i_28_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_wb_mux[4]), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .I4(mem_wb_mux[1]), .O(\ld/in [1])); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_r1_0_31_0_5_i_16 (.I0(mem_reg_r1_0_31_0_5_i_31_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_wb_mux[3]), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .I4(mem_wb_mux[0]), .O(\ld/in [0])); LUT6 #( .INIT(64'hB8BBB8BBB8BBB888)) mem_reg_r1_0_31_0_5_i_18 (.I0(mem_reg_r1_0_31_0_5_i_34_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_wb_mux[6]), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .I4(\pprev_data_reg[3]_0 ), .I5(mem_reg_r1_0_31_0_5_i_37_n_0), .O(\ld/in [3])); LUT6 #( .INIT(64'hFFFFFFFF01550000)) mem_reg_r1_0_31_0_5_i_2 (.I0(\pprev_data_reg[0] ), .I1(\pprev_data_reg[0]_1 [2]), .I2(\pprev_data_reg[0]_1 [0]), .I3(\pprev_data_reg[0]_1 [1]), .I4(\ld/in [1]), .I5(\pprev_data_reg[1] ), .O(wb_mux[1])); LUT6 #( .INIT(64'hB8BBB8BBB8BBB888)) mem_reg_r1_0_31_0_5_i_20 (.I0(mem_reg_r1_0_31_0_5_i_38_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_wb_mux[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .I4(\pprev_data_reg[2]_0 ), .I5(mem_reg_r1_0_31_0_5_i_41_n_0), .O(\ld/in [2])); LUT6 #( .INIT(64'hB8BBB8BBB8BBB888)) mem_reg_r1_0_31_0_5_i_22 (.I0(mem_reg_r1_0_31_0_5_i_42_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_wb_mux[8]), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .I4(\pprev_data_reg[5] ), .I5(mem_reg_r1_0_31_0_5_i_45_n_0), .O(\ld/in [5])); LUT6 #( .INIT(64'hB8BBB8BBB8BBB888)) mem_reg_r1_0_31_0_5_i_24 (.I0(mem_reg_r1_0_31_0_5_i_46_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_wb_mux[7]), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .I4(\pprev_data_reg[4]_0 ), .I5(mem_reg_r1_0_31_0_5_i_49_n_0), .O(\ld/in [4])); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_r1_0_31_0_5_i_28 (.I0(mem_reg_r1_0_31_12_17_i_19_0), .I1(mem_reg_r1_0_31_0_5_i_51_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_reg_0_0_i_224_1), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_r1_0_31_0_5_i_54_n_0), .O(mem_reg_r1_0_31_0_5_i_28_n_0)); LUT6 #( .INIT(64'hFFFFFFFF01550000)) mem_reg_r1_0_31_0_5_i_3 (.I0(\pprev_data_reg[0] ), .I1(\pprev_data_reg[0]_1 [2]), .I2(\pprev_data_reg[0]_1 [0]), .I3(\pprev_data_reg[0]_1 [1]), .I4(\ld/in [0]), .I5(\pprev_data_reg[0]_0 ), .O(wb_mux[0])); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_r1_0_31_0_5_i_31 (.I0(mem_reg_r1_0_31_12_17_i_21_0), .I1(mem_reg_r1_0_31_0_5_i_60_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_reg_0_0_i_227_1), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_r1_0_31_0_5_i_62_n_0), .O(mem_reg_r1_0_31_0_5_i_31_n_0)); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_r1_0_31_0_5_i_34 (.I0(mem_reg_r1_0_31_18_23_i_7_0), .I1(mem_reg_r1_0_31_0_5_i_66_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_reg_0_1_i_5_1), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_r1_0_31_0_5_i_68_n_0), .O(mem_reg_r1_0_31_0_5_i_34_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_37 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(doutb_reg[3]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[3]), .O(mem_reg_r1_0_31_0_5_i_37_n_0)); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_r1_0_31_0_5_i_38 (.I0(mem_reg_r1_0_31_18_23_i_9_0), .I1(mem_reg_r1_0_31_0_5_i_74_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_reg_0_1_i_7_1), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_r1_0_31_0_5_i_76_n_0), .O(mem_reg_r1_0_31_0_5_i_38_n_0)); LUT6 #( .INIT(64'hFFFFFFFF01550000)) mem_reg_r1_0_31_0_5_i_4 (.I0(\pprev_data_reg[0] ), .I1(\pprev_data_reg[0]_1 [2]), .I2(\pprev_data_reg[0]_1 [0]), .I3(\pprev_data_reg[0]_1 [1]), .I4(\ld/in [3]), .I5(\pprev_data_reg[3] ), .O(wb_mux[3])); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_41 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(doutb_reg[2]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[2]), .O(mem_reg_r1_0_31_0_5_i_41_n_0)); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_r1_0_31_0_5_i_42 (.I0(mem_reg_r1_0_31_18_23_i_11_0), .I1(mem_reg_r1_0_31_0_5_i_80_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_reg_r1_0_31_0_5_i_22_0), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_r1_0_31_0_5_i_82_n_0), .O(mem_reg_r1_0_31_0_5_i_42_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_45 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(doutb_reg[5]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[5]), .O(mem_reg_r1_0_31_0_5_i_45_n_0)); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_r1_0_31_0_5_i_46 (.I0(mem_reg_r1_0_31_18_23_i_13_0), .I1(mem_reg_r1_0_31_0_5_i_86_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_reg_0_2_i_7_1), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_r1_0_31_0_5_i_88_n_0), .O(mem_reg_r1_0_31_0_5_i_46_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_49 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(doutb_reg[4]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[4]), .O(mem_reg_r1_0_31_0_5_i_49_n_0)); LUT6 #( .INIT(64'hFFFFFFFF01550000)) mem_reg_r1_0_31_0_5_i_5 (.I0(\pprev_data_reg[0] ), .I1(\pprev_data_reg[0]_1 [2]), .I2(\pprev_data_reg[0]_1 [0]), .I3(\pprev_data_reg[0]_1 [1]), .I4(\ld/in [2]), .I5(\pprev_data_reg[2] ), .O(wb_mux[2])); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_51 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[13]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[25]), .O(mem_reg_r1_0_31_0_5_i_51_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_54 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(doutb_reg[9]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[9]), .O(mem_reg_r1_0_31_0_5_i_54_n_0)); LUT6 #( .INIT(64'hFFFFFFFF01550000)) mem_reg_r1_0_31_0_5_i_6 (.I0(\pprev_data_reg[0] ), .I1(\pprev_data_reg[0]_1 [2]), .I2(\pprev_data_reg[0]_1 [0]), .I3(\pprev_data_reg[0]_1 [1]), .I4(\ld/in [5]), .I5(\pprev_data_reg[5]_0 ), .O(wb_mux[5])); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_60 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[12]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[24]), .O(mem_reg_r1_0_31_0_5_i_60_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_62 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(doutb_reg[8]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[8]), .O(mem_reg_r1_0_31_0_5_i_62_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_66 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[15]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[27]), .O(mem_reg_r1_0_31_0_5_i_66_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_68 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(doutb_reg[11]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[11]), .O(mem_reg_r1_0_31_0_5_i_68_n_0)); LUT6 #( .INIT(64'hFFFFFFFF01550000)) mem_reg_r1_0_31_0_5_i_7 (.I0(\pprev_data_reg[0] ), .I1(\pprev_data_reg[0]_1 [2]), .I2(\pprev_data_reg[0]_1 [0]), .I3(\pprev_data_reg[0]_1 [1]), .I4(\ld/in [4]), .I5(\pprev_data_reg[4] ), .O(wb_mux[4])); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_74 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[14]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[26]), .O(mem_reg_r1_0_31_0_5_i_74_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_76 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(doutb_reg[10]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[10]), .O(mem_reg_r1_0_31_0_5_i_76_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_80 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[17]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[29]), .O(mem_reg_r1_0_31_0_5_i_80_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_82 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(doutb_reg[13]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[13]), .O(mem_reg_r1_0_31_0_5_i_82_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_86 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[16]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[28]), .O(mem_reg_r1_0_31_0_5_i_86_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_0_5_i_88 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(doutb_reg[12]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[12]), .O(mem_reg_r1_0_31_0_5_i_88_n_0)); LUT6 #( .INIT(64'hFFFFFFFF40404540)) mem_reg_r1_0_31_12_17_i_1 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_12_17_i_7_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(mem_reg_r1_0_31_12_17_i_8_n_0), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[13] ), .O(wb_mux[13])); LUT5 #( .INIT(32'h00002E22)) mem_reg_r1_0_31_12_17_i_10 (.I0(mem_reg_r1_0_31_0_5_i_46_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_wb_mux[7]), .I4(\pprev_data_reg[0]_1 [1]), .O(mem_reg_r1_0_31_12_17_i_10_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_12_17_i_11 (.I0(mem_reg_r1_0_31_12_17_i_24_n_0), .I1(mem_reg_r1_0_31_0_5_i_46_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_12_17_i_11_n_0)); LUT5 #( .INIT(32'h00002E22)) mem_reg_r1_0_31_12_17_i_13 (.I0(mem_reg_r1_0_31_6_11_i_23_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_wb_mux[10]), .I4(\pprev_data_reg[0]_1 [1]), .O(\wb_alu_reg[0] )); LUT6 #( .INIT(64'h4D48ED4D4D48E848)) mem_reg_r1_0_31_12_17_i_14 (.I0(\pprev_data_reg[0]_1 [1]), .I1(mem_reg_r1_0_31_6_11_i_23_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[0]), .I3(mem_wb_mux[10]), .I4(mem_reg_r1_0_31_6_11_i_23_0[1]), .I5(mem_wb_mux[2]), .O(mem_reg_r1_0_31_12_17_i_14_n_0)); LUT5 #( .INIT(32'h00002E22)) mem_reg_r1_0_31_12_17_i_16 (.I0(mem_reg_r1_0_31_6_11_i_27_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_wb_mux[9]), .I4(\pprev_data_reg[0]_1 [1]), .O(mem_reg_r1_0_31_12_17_i_16_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_12_17_i_17 (.I0(mem_reg_r1_0_31_12_17_i_26_n_0), .I1(mem_reg_r1_0_31_6_11_i_27_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_12_17_i_17_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_12_17_i_19 (.I0(mem_reg_r1_0_31_12_17_i_27_n_0), .I1(mem_reg_r1_0_31_6_11_i_31_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_12_17_i_19_n_0)); LUT6 #( .INIT(64'hFFFFFFFF40404540)) mem_reg_r1_0_31_12_17_i_2 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_12_17_i_10_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(mem_reg_r1_0_31_12_17_i_11_n_0), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[12] ), .O(wb_mux[12])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_12_17_i_21 (.I0(mem_reg_r1_0_31_12_17_i_29_n_0), .I1(mem_reg_r1_0_31_6_11_i_33_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_12_17_i_21_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_12_17_i_23 (.I0(mem_reg_r1_0_31_12_17_i_30_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_12_17_i_8_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_12_17_i_23_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_12_17_i_24 (.I0(mem_reg_r1_0_31_12_17_i_31_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_12_17_i_11_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_12_17_i_24_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_12_17_i_26 (.I0(mem_reg_r1_0_31_12_17_i_32_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_12_17_i_17_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_12_17_i_26_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_12_17_i_27 (.I0(mem_reg_r1_0_31_0_5_i_51_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_12_17_i_19_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_12_17_i_27_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_12_17_i_29 (.I0(mem_reg_r1_0_31_0_5_i_60_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_12_17_i_21_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_12_17_i_29_n_0)); LUT6 #( .INIT(64'hFFFFFFFF40404540)) mem_reg_r1_0_31_12_17_i_3 (.I0(\pprev_data_reg[0] ), .I1(\wb_alu_reg[0] ), .I2(\pprev_data_reg[0]_1 [0]), .I3(mem_reg_r1_0_31_12_17_i_14_n_0), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[15] ), .O(wb_mux[15])); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_12_17_i_30 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[9]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[21]), .O(mem_reg_r1_0_31_12_17_i_30_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_12_17_i_31 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[8]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[20]), .O(mem_reg_r1_0_31_12_17_i_31_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_12_17_i_32 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[10]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[22]), .O(mem_reg_r1_0_31_12_17_i_32_n_0)); LUT6 #( .INIT(64'hFFFFFFFF40404540)) mem_reg_r1_0_31_12_17_i_4 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_12_17_i_16_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(mem_reg_r1_0_31_12_17_i_17_n_0), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[14] ), .O(wb_mux[14])); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_12_17_i_5 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_12_17_i_19_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[17] ), .O(wb_mux[17])); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_12_17_i_6 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_12_17_i_21_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[16] ), .O(wb_mux[16])); LUT5 #( .INIT(32'h00002E22)) mem_reg_r1_0_31_12_17_i_7 (.I0(mem_reg_r1_0_31_0_5_i_42_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_wb_mux[8]), .I4(\pprev_data_reg[0]_1 [1]), .O(mem_reg_r1_0_31_12_17_i_7_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_12_17_i_8 (.I0(mem_reg_r1_0_31_12_17_i_23_n_0), .I1(mem_reg_r1_0_31_0_5_i_42_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_12_17_i_8_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_18_23_i_1 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_18_23_i_7_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[19] ), .O(wb_mux[19])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_18_23_i_11 (.I0(mem_reg_r1_0_31_18_23_i_21_n_0), .I1(mem_reg_r1_0_31_12_17_i_23_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_18_23_i_11_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_18_23_i_13 (.I0(mem_reg_r1_0_31_18_23_i_23_n_0), .I1(mem_reg_r1_0_31_12_17_i_24_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_18_23_i_13_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_18_23_i_15 (.I0(mem_reg_r1_0_31_18_23_i_24_n_0), .I1(mem_reg_r1_0_31_18_23_i_25_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_18_23_i_15_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_18_23_i_17 (.I0(mem_reg_r1_0_31_18_23_i_26_n_0), .I1(mem_reg_r1_0_31_12_17_i_26_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_18_23_i_17_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_18_23_i_19 (.I0(mem_reg_r1_0_31_0_5_i_66_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_18_23_i_7_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_18_23_i_19_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_18_23_i_2 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_18_23_i_9_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[18] ), .O(wb_mux[18])); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_18_23_i_20 (.I0(mem_reg_r1_0_31_0_5_i_74_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_18_23_i_9_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_18_23_i_20_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_18_23_i_21 (.I0(mem_reg_r1_0_31_0_5_i_80_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_18_23_i_11_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_18_23_i_21_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_18_23_i_23 (.I0(mem_reg_r1_0_31_0_5_i_86_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_18_23_i_13_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_18_23_i_23_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_18_23_i_24 (.I0(mem_reg_r1_0_31_6_11_i_37_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_18_23_i_15_2), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_18_23_i_24_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_18_23_i_25 (.I0(mem_reg_r1_0_31_6_11_i_50_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_18_23_i_15_1), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_18_23_i_25_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_18_23_i_26 (.I0(mem_reg_r1_0_31_6_11_i_44_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_18_23_i_17_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_18_23_i_26_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_18_23_i_3 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_18_23_i_11_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[21] ), .O(wb_mux[21])); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_18_23_i_4 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_18_23_i_13_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[20] ), .O(wb_mux[20])); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_18_23_i_5 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_18_23_i_15_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[23] ), .O(wb_mux[23])); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_18_23_i_6 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_18_23_i_17_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[22] ), .O(wb_mux[22])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_18_23_i_7 (.I0(mem_reg_r1_0_31_18_23_i_19_n_0), .I1(mem_reg_r1_0_31_6_11_i_34_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_18_23_i_7_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_18_23_i_9 (.I0(mem_reg_r1_0_31_18_23_i_20_n_0), .I1(mem_reg_r1_0_31_6_11_i_35_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_18_23_i_9_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_24_29_i_1 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_24_29_i_7_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[25] ), .O(wb_mux[25])); LUT6 #( .INIT(64'h0F004F4F0F004040)) mem_reg_r1_0_31_24_29_i_11 (.I0(mem_reg_r1_0_31_6_11_i_23_0[1]), .I1(mem_wb_mux[14]), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_24_29_i_11_n_0)); LUT6 #( .INIT(64'h0F004F4F0F004040)) mem_reg_r1_0_31_24_29_i_13 (.I0(mem_reg_r1_0_31_6_11_i_23_0[1]), .I1(mem_wb_mux[13]), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_24_29_i_13_n_0)); LUT6 #( .INIT(64'h0F004F4F0F004040)) mem_reg_r1_0_31_24_29_i_15 (.I0(mem_reg_r1_0_31_6_11_i_23_0[1]), .I1(mem_wb_mux[16]), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_24_29_i_15_n_0)); LUT6 #( .INIT(64'h0F004F4F0F004040)) mem_reg_r1_0_31_24_29_i_17 (.I0(mem_reg_r1_0_31_6_11_i_23_0[1]), .I1(mem_wb_mux[15]), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_24_29_i_17_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_24_29_i_2 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_24_29_i_9_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[24] ), .O(wb_mux[24])); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_24_29_i_3 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_24_29_i_11_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[27] ), .O(wb_mux[27])); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_24_29_i_4 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_24_29_i_13_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[26] ), .O(wb_mux[26])); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_24_29_i_5 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_24_29_i_15_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[29] ), .O(wb_mux[29])); LUT6 #( .INIT(64'hFFFFFFFF00005404)) mem_reg_r1_0_31_24_29_i_6 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_24_29_i_17_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[28] ), .O(wb_mux[28])); LUT6 #( .INIT(64'h0F004F4F0F004040)) mem_reg_r1_0_31_24_29_i_7 (.I0(mem_reg_r1_0_31_6_11_i_23_0[1]), .I1(mem_wb_mux[12]), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_24_29_i_7_n_0)); LUT6 #( .INIT(64'h0F004F4F0F004040)) mem_reg_r1_0_31_24_29_i_9 (.I0(mem_reg_r1_0_31_6_11_i_23_0[1]), .I1(mem_wb_mux[11]), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_24_29_i_9_n_0)); LUT6 #( .INIT(64'hFFFFFFFF01550000)) mem_reg_r1_0_31_6_11_i_1 (.I0(\pprev_data_reg[0] ), .I1(\pprev_data_reg[0]_1 [2]), .I2(\pprev_data_reg[0]_1 [0]), .I3(\pprev_data_reg[0]_1 [1]), .I4(\ld/in [7]), .I5(\pprev_data_reg[7]_0 ), .O(wb_mux[7])); LUT5 #( .INIT(32'h00002E22)) mem_reg_r1_0_31_6_11_i_11 (.I0(mem_reg_r1_0_31_0_5_i_28_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_wb_mux[4]), .I4(\pprev_data_reg[0]_1 [1]), .O(mem_reg_r1_0_31_6_11_i_11_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_6_11_i_12 (.I0(mem_reg_r1_0_31_6_11_i_31_n_0), .I1(mem_reg_r1_0_31_0_5_i_28_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_6_11_i_12_n_0)); LUT5 #( .INIT(32'h00002E22)) mem_reg_r1_0_31_6_11_i_14 (.I0(mem_reg_r1_0_31_0_5_i_31_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_wb_mux[3]), .I4(\pprev_data_reg[0]_1 [1]), .O(mem_reg_r1_0_31_6_11_i_14_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_6_11_i_15 (.I0(mem_reg_r1_0_31_6_11_i_33_n_0), .I1(mem_reg_r1_0_31_0_5_i_31_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_6_11_i_15_n_0)); LUT5 #( .INIT(32'h00002E22)) mem_reg_r1_0_31_6_11_i_17 (.I0(mem_reg_r1_0_31_0_5_i_34_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_wb_mux[6]), .I4(\pprev_data_reg[0]_1 [1]), .O(mem_reg_r1_0_31_6_11_i_17_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_6_11_i_18 (.I0(mem_reg_r1_0_31_6_11_i_34_n_0), .I1(mem_reg_r1_0_31_0_5_i_34_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_6_11_i_18_n_0)); LUT6 #( .INIT(64'hFFFFFFFF01550000)) mem_reg_r1_0_31_6_11_i_2 (.I0(\pprev_data_reg[0] ), .I1(\pprev_data_reg[0]_1 [2]), .I2(\pprev_data_reg[0]_1 [0]), .I3(\pprev_data_reg[0]_1 [1]), .I4(\ld/in [6]), .I5(\pprev_data_reg[6]_0 ), .O(wb_mux[6])); LUT5 #( .INIT(32'h00002E22)) mem_reg_r1_0_31_6_11_i_20 (.I0(mem_reg_r1_0_31_0_5_i_38_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_wb_mux[5]), .I4(\pprev_data_reg[0]_1 [1]), .O(mem_reg_r1_0_31_6_11_i_20_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) mem_reg_r1_0_31_6_11_i_21 (.I0(mem_reg_r1_0_31_6_11_i_35_n_0), .I1(mem_reg_r1_0_31_0_5_i_38_n_0), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(mem_reg_r1_0_31_6_11_i_21_n_0)); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_r1_0_31_6_11_i_23 (.I0(mem_reg_r1_0_31_18_23_i_15_2), .I1(mem_reg_r1_0_31_6_11_i_37_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_reg_r1_0_31_6_11_i_15_1), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_r1_0_31_6_11_i_39_n_0), .O(mem_reg_r1_0_31_6_11_i_23_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_6_11_i_26 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[2]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[7]), .O(mem_reg_r1_0_31_6_11_i_26_n_0)); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_r1_0_31_6_11_i_27 (.I0(mem_reg_r1_0_31_18_23_i_17_0), .I1(mem_reg_r1_0_31_6_11_i_44_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(mem_reg_r1_0_31_6_11_i_9_0), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_r1_0_31_6_11_i_46_n_0), .O(mem_reg_r1_0_31_6_11_i_27_n_0)); LUT6 #( .INIT(64'hFFFFFFFF40404540)) mem_reg_r1_0_31_6_11_i_3 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_6_11_i_11_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(mem_reg_r1_0_31_6_11_i_12_n_0), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[9] ), .O(wb_mux[9])); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_6_11_i_30 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(doutb_reg[6]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[6]), .O(mem_reg_r1_0_31_6_11_i_30_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_6_11_i_31 (.I0(mem_reg_r1_0_31_6_11_i_49_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_6_11_i_12_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_6_11_i_31_n_0)); LUT6 #( .INIT(64'hDFDFCFCFD0DFC0C0)) mem_reg_r1_0_31_6_11_i_32 (.I0(mem_reg_r1_0_31_18_23_i_15_1), .I1(mem_reg_r1_0_31_6_11_i_50_n_0), .I2(mem_reg_r1_0_31_6_11_i_23_0[1]), .I3(\pprev_data[31]_i_2 ), .I4(mem_reg_r1_0_31_18_23_i_15_0), .I5(mem_reg_r1_0_31_6_11_i_26_n_0), .O(\wb_alu_reg[1] )); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_6_11_i_33 (.I0(mem_reg_r1_0_31_6_11_i_52_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_6_11_i_15_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_6_11_i_33_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_6_11_i_34 (.I0(mem_reg_r1_0_31_6_11_i_53_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_6_11_i_18_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_6_11_i_34_n_0)); LUT4 #( .INIT(16'h00AE)) mem_reg_r1_0_31_6_11_i_35 (.I0(mem_reg_r1_0_31_6_11_i_54_n_0), .I1(mem_reg_r1_0_31_18_23_i_15_0), .I2(mem_reg_r1_0_31_6_11_i_21_0), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .O(mem_reg_r1_0_31_6_11_i_35_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_6_11_i_37 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[19]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[31]), .O(mem_reg_r1_0_31_6_11_i_37_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_6_11_i_39 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[3]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[15]), .O(mem_reg_r1_0_31_6_11_i_39_n_0)); LUT6 #( .INIT(64'hFFFFFFFF40404540)) mem_reg_r1_0_31_6_11_i_4 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_6_11_i_14_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(mem_reg_r1_0_31_6_11_i_15_n_0), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[8] ), .O(wb_mux[8])); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_6_11_i_44 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[18]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[30]), .O(mem_reg_r1_0_31_6_11_i_44_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_6_11_i_46 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(doutb_reg[14]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[14]), .O(mem_reg_r1_0_31_6_11_i_46_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_6_11_i_49 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[5]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[17]), .O(mem_reg_r1_0_31_6_11_i_49_n_0)); LUT6 #( .INIT(64'hFFFFFFFF40404540)) mem_reg_r1_0_31_6_11_i_5 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_6_11_i_17_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(mem_reg_r1_0_31_6_11_i_18_n_0), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[11] ), .O(wb_mux[11])); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_6_11_i_50 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[11]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[23]), .O(mem_reg_r1_0_31_6_11_i_50_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_6_11_i_52 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[4]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[16]), .O(mem_reg_r1_0_31_6_11_i_52_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_6_11_i_53 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[7]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[19]), .O(mem_reg_r1_0_31_6_11_i_53_n_0)); LUT6 #( .INIT(64'h00040F0000040000)) mem_reg_r1_0_31_6_11_i_54 (.I0(mem_reg_r1_0_31_6_11_i_23_0[3]), .I1(douta_reg_1_0[6]), .I2(mem_reg_r1_0_31_6_11_i_23_0[5]), .I3(mem_reg_r1_0_31_6_11_i_23_0[2]), .I4(mem_reg_r1_0_31_6_11_i_23_0[4]), .I5(dout[18]), .O(mem_reg_r1_0_31_6_11_i_54_n_0)); LUT6 #( .INIT(64'hFFFFFFFF40404540)) mem_reg_r1_0_31_6_11_i_6 (.I0(\pprev_data_reg[0] ), .I1(mem_reg_r1_0_31_6_11_i_20_n_0), .I2(\pprev_data_reg[0]_1 [0]), .I3(mem_reg_r1_0_31_6_11_i_21_n_0), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[10] ), .O(wb_mux[10])); LUT6 #( .INIT(64'hB8BBB8BBB8BBB888)) mem_reg_r1_0_31_6_11_i_7 (.I0(mem_reg_r1_0_31_6_11_i_23_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_wb_mux[10]), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .I4(\pprev_data_reg[7] ), .I5(mem_reg_r1_0_31_6_11_i_26_n_0), .O(\ld/in [7])); LUT6 #( .INIT(64'hB8BBB8BBB8BBB888)) mem_reg_r1_0_31_6_11_i_9 (.I0(mem_reg_r1_0_31_6_11_i_27_n_0), .I1(mem_reg_r1_0_31_6_11_i_23_0[0]), .I2(mem_wb_mux[9]), .I3(mem_reg_r1_0_31_6_11_i_23_0[1]), .I4(\pprev_data_reg[6] ), .I5(mem_reg_r1_0_31_6_11_i_30_n_0), .O(\ld/in [6])); LUT6 #( .INIT(64'hFFFFFFFF00005404)) \pprev_data[30]_i_1 (.I0(\pprev_data_reg[0] ), .I1(\pprev_data[30]_i_2_n_0 ), .I2(\pprev_data_reg[0]_1 [0]), .I3(\wb_alu_reg[0] ), .I4(\pprev_data_reg[0]_1 [2]), .I5(\pprev_data_reg[30] ), .O(wb_mux[30])); LUT6 #( .INIT(64'h0F004F4F0F004040)) \pprev_data[30]_i_2 (.I0(mem_reg_r1_0_31_6_11_i_23_0[1]), .I1(mem_wb_mux[17]), .I2(\pprev_data_reg[0]_1 [1]), .I3(mem_reg_r1_0_31_6_11_i_23_n_0), .I4(mem_reg_r1_0_31_6_11_i_23_0[0]), .I5(\wb_alu_reg[1] ), .O(\pprev_data[30]_i_2_n_0 )); LUT4 #( .INIT(16'h8F80)) \tx_shift[1]_i_1 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[0]), .I2(start), .I3(tx_shift[0]), .O(p_1_in_0[0])); LUT4 #( .INIT(16'h8F80)) \tx_shift[2]_i_1 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[1]), .I2(start), .I3(tx_shift[1]), .O(p_1_in_0[1])); LUT4 #( .INIT(16'h8F80)) \tx_shift[3]_i_1 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[2]), .I2(start), .I3(tx_shift[2]), .O(p_1_in_0[2])); LUT4 #( .INIT(16'h8F80)) \tx_shift[4]_i_1 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[3]), .I2(start), .I3(tx_shift[3]), .O(p_1_in_0[3])); LUT4 #( .INIT(16'h8F80)) \tx_shift[5]_i_1 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[4]), .I2(start), .I3(tx_shift[4]), .O(p_1_in_0[4])); LUT4 #( .INIT(16'h8F80)) \tx_shift[6]_i_1 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[5]), .I2(start), .I3(tx_shift[5]), .O(p_1_in_0[5])); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT2 #( .INIT(4'hE)) \tx_shift[7]_i_1 (.I0(start), .I1(symbol_edge__7), .O(\clock_counter_reg[0] )); LUT4 #( .INIT(16'h8F80)) \tx_shift[7]_i_2 (.I0(mem_reg_0_0_i_91_n_0), .I1(fwd_b[6]), .I2(start), .I3(tx_shift[6]), .O(p_1_in_0[6])); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT5 #( .INIT(32'hC0FFC0AA)) \uatransmit/tx_shift[8]_i_1 (.I0(tx_shift[6]), .I1(fwd_b[7]), .I2(mem_reg_0_0_i_91_n_0), .I3(start), .I4(symbol_edge__7), .O(\tx_shift_reg[8] )); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_10 (.I0(fwd_a[27]), .I1(fwd_b[27]), .I2(fwd_b[29]), .I3(fwd_a[29]), .I4(fwd_b[28]), .I5(fwd_a[28]), .O(wb_BrEq_i_10_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_11 (.I0(fwd_a[24]), .I1(fwd_b[24]), .I2(fwd_b[26]), .I3(fwd_a[26]), .I4(fwd_b[25]), .I5(fwd_a[25]), .O(wb_BrEq_i_11_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_13 (.I0(fwd_a[21]), .I1(fwd_b[21]), .I2(fwd_b[23]), .I3(fwd_a[23]), .I4(fwd_b[22]), .I5(fwd_a[22]), .O(wb_BrEq_i_13_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_14 (.I0(fwd_a[18]), .I1(fwd_b[18]), .I2(fwd_b[20]), .I3(fwd_a[20]), .I4(fwd_b[19]), .I5(fwd_a[19]), .O(wb_BrEq_i_14_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_15 (.I0(fwd_a[15]), .I1(fwd_b[15]), .I2(fwd_b[17]), .I3(fwd_a[17]), .I4(fwd_b[16]), .I5(fwd_a[16]), .O(wb_BrEq_i_15_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_16 (.I0(fwd_a[12]), .I1(fwd_b[12]), .I2(fwd_b[14]), .I3(fwd_a[14]), .I4(fwd_b[13]), .I5(fwd_a[13]), .O(wb_BrEq_i_16_n_0)); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_18 (.I0(wb_mux[27]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_7_0), .O(fwd_a[27])); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_19 (.I0(wb_mux[29]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_6_1), .O(fwd_a[29])); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_20 (.I0(wb_mux[28]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_6_0), .O(fwd_a[28])); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_21 (.I0(wb_mux[24]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_8_0), .O(fwd_a[24])); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_22 (.I0(wb_mux[26]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_7_1), .O(fwd_a[26])); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_23 (.I0(wb_mux[25]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_8_1), .O(fwd_a[25])); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_25 (.I0(fwd_a[21]), .I1(fwd_b[21]), .I2(fwd_b[23]), .I3(fwd_a[23]), .I4(fwd_b[22]), .I5(fwd_a[22]), .O(wb_BrEq_i_25_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_26 (.I0(fwd_a[18]), .I1(fwd_b[18]), .I2(fwd_b[20]), .I3(fwd_a[20]), .I4(fwd_b[19]), .I5(fwd_a[19]), .O(wb_BrEq_i_26_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_27 (.I0(fwd_a[15]), .I1(fwd_b[15]), .I2(fwd_b[17]), .I3(fwd_a[17]), .I4(fwd_b[16]), .I5(fwd_a[16]), .O(wb_BrEq_i_27_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_28 (.I0(fwd_a[12]), .I1(fwd_b[12]), .I2(fwd_b[14]), .I3(fwd_a[14]), .I4(fwd_b[13]), .I5(fwd_a[13]), .O(wb_BrEq_i_28_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_29 (.I0(fwd_a[9]), .I1(fwd_b[9]), .I2(fwd_b[11]), .I3(fwd_a[11]), .I4(fwd_b[10]), .I5(fwd_a[10]), .O(wb_BrEq_i_29_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_30 (.I0(fwd_a[6]), .I1(fwd_b[6]), .I2(fwd_b[8]), .I3(fwd_a[8]), .I4(fwd_b[7]), .I5(fwd_a[7]), .O(wb_BrEq_i_30_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_31 (.I0(fwd_a[3]), .I1(fwd_b[3]), .I2(fwd_b[5]), .I3(fwd_a[5]), .I4(fwd_b[4]), .I5(fwd_a[4]), .O(wb_BrEq_i_31_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_32 (.I0(fwd_a[0]), .I1(fwd_b[0]), .I2(fwd_b[2]), .I3(fwd_a[2]), .I4(fwd_b[1]), .I5(fwd_a[1]), .O(wb_BrEq_i_32_n_0)); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_33 (.I0(wb_mux[21]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_24_0), .O(fwd_a[21])); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_34 (.I0(wb_mux[23]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_13_1), .O(fwd_a[23])); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_35 (.I0(wb_mux[22]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_13_0), .O(fwd_a[22])); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_36 (.I0(wb_mux[18]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_25_0), .O(fwd_a[18])); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_37 (.I0(wb_mux[20]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_14_0), .O(fwd_a[20])); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_38 (.I0(wb_mux[19]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_25_1), .O(fwd_a[19])); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_39 (.I0(wb_mux[15]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_43_0), .O(fwd_a[15])); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_40 (.I0(wb_mux[17]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_15_1), .O(fwd_a[17])); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_41 (.I0(wb_mux[16]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_15_0), .O(fwd_a[16])); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_42 (.I0(wb_mux[12]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_44_0), .O(fwd_a[12])); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_43 (.I0(wb_mux[14]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_16_0), .O(fwd_a[14])); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_44 (.I0(wb_mux[13]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_44_1), .O(fwd_a[13])); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_45 (.I0(fwd_a[9]), .I1(fwd_b[9]), .I2(fwd_b[11]), .I3(fwd_a[11]), .I4(fwd_b[10]), .I5(fwd_a[10]), .O(wb_BrEq_i_45_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_46 (.I0(fwd_a[6]), .I1(fwd_b[6]), .I2(fwd_b[8]), .I3(fwd_a[8]), .I4(fwd_b[7]), .I5(fwd_a[7]), .O(wb_BrEq_i_46_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_47 (.I0(fwd_a[3]), .I1(fwd_b[3]), .I2(fwd_b[5]), .I3(fwd_a[5]), .I4(fwd_b[4]), .I5(fwd_a[4]), .O(wb_BrEq_i_47_n_0)); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_48 (.I0(fwd_a[0]), .I1(fwd_b[0]), .I2(fwd_b[2]), .I3(fwd_a[2]), .I4(fwd_b[1]), .I5(fwd_a[1]), .O(wb_BrEq_i_48_n_0)); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_49 (.I0(wb_mux[9]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_46_0), .O(fwd_a[9])); LUT5 #( .INIT(32'hB8470000)) wb_BrEq_i_5 (.I0(wb_mux[30]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_reg_i_2_1), .I3(fwd_b[30]), .I4(wb_BrLt_reg_i_3_0), .O(wb_BrEq_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_50 (.I0(wb_mux[11]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_29_1), .O(fwd_a[11])); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_51 (.I0(wb_mux[10]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_29_0), .O(fwd_a[10])); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_52 (.I0(wb_mux[6]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_60_0), .O(fwd_a[6])); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_53 (.I0(wb_mux[8]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_30_0), .O(fwd_a[8])); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_54 (.I0(wb_mux[7]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_60_1), .O(fwd_a[7])); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_55 (.I0(wb_mux[3]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_62_0), .O(fwd_a[3])); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_56 (.I0(wb_mux[5]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_31_1), .O(fwd_a[5])); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_57 (.I0(wb_mux[4]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_31_0), .O(fwd_a[4])); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_58 (.I0(wb_mux[0]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_63_0), .O(fwd_a[0])); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_59 (.I0(wb_mux[2]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrEq_i_32_0), .O(fwd_a[2])); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_6 (.I0(fwd_a[27]), .I1(fwd_b[27]), .I2(fwd_b[29]), .I3(fwd_a[29]), .I4(fwd_b[28]), .I5(fwd_a[28]), .O(wb_BrEq_i_6_n_0)); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT3 #( .INIT(8'hB8)) wb_BrEq_i_60 (.I0(wb_mux[1]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_i_63_1), .O(fwd_a[1])); LUT6 #( .INIT(64'h9009000000009009)) wb_BrEq_i_7 (.I0(fwd_a[24]), .I1(fwd_b[24]), .I2(fwd_b[26]), .I3(fwd_a[26]), .I4(fwd_b[25]), .I5(fwd_a[25]), .O(wb_BrEq_i_7_n_0)); LUT5 #( .INIT(32'hB8470000)) wb_BrEq_i_9 (.I0(wb_mux[30]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_reg_i_2_1), .I3(fwd_b[30]), .I4(wb_BrLt_reg_i_3_0), .O(wb_BrEq_i_9_n_0)); CARRY4 wb_BrEq_reg_i_12 (.CI(\<const0> ), .CO({wb_BrEq_reg_i_12_n_0,wb_BrEq_reg_i_12_n_1,wb_BrEq_reg_i_12_n_2,wb_BrEq_reg_i_12_n_3}), .CYINIT(\<const1> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .S({wb_BrEq_i_29_n_0,wb_BrEq_i_30_n_0,wb_BrEq_i_31_n_0,wb_BrEq_i_32_n_0})); CARRY4 wb_BrEq_reg_i_2 (.CI(wb_BrEq_reg_i_4_n_0), .CO({wb_BrEq_i_7_0,wb_BrEq_reg_i_2_n_2,wb_BrEq_reg_i_2_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .S({\<const0> ,wb_BrEq_i_5_n_0,wb_BrEq_i_6_n_0,wb_BrEq_i_7_n_0})); CARRY4 wb_BrEq_reg_i_24 (.CI(\<const0> ), .CO({wb_BrEq_reg_i_24_n_0,wb_BrEq_reg_i_24_n_1,wb_BrEq_reg_i_24_n_2,wb_BrEq_reg_i_24_n_3}), .CYINIT(\<const1> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .S({wb_BrEq_i_45_n_0,wb_BrEq_i_46_n_0,wb_BrEq_i_47_n_0,wb_BrEq_i_48_n_0})); CARRY4 wb_BrEq_reg_i_3 (.CI(wb_BrEq_reg_i_8_n_0), .CO({CO,wb_BrEq_reg_i_3_n_2,wb_BrEq_reg_i_3_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .S({\<const0> ,wb_BrEq_i_9_n_0,wb_BrEq_i_10_n_0,wb_BrEq_i_11_n_0})); CARRY4 wb_BrEq_reg_i_4 (.CI(wb_BrEq_reg_i_12_n_0), .CO({wb_BrEq_reg_i_4_n_0,wb_BrEq_reg_i_4_n_1,wb_BrEq_reg_i_4_n_2,wb_BrEq_reg_i_4_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .S({wb_BrEq_i_13_n_0,wb_BrEq_i_14_n_0,wb_BrEq_i_15_n_0,wb_BrEq_i_16_n_0})); CARRY4 wb_BrEq_reg_i_8 (.CI(wb_BrEq_reg_i_24_n_0), .CO({wb_BrEq_reg_i_8_n_0,wb_BrEq_reg_i_8_n_1,wb_BrEq_reg_i_8_n_2,wb_BrEq_reg_i_8_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .S({wb_BrEq_i_25_n_0,wb_BrEq_i_26_n_0,wb_BrEq_i_27_n_0,wb_BrEq_i_28_n_0})); LUT3 #( .INIT(8'hB8)) wb_BrLt_i_1 (.I0(wb_BrLt_reg_i_2_n_0), .I1(mem_reg_2_0[3]), .I2(wb_BrLt_reg_i_3_n_0), .O(BrLt)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_10 (.I0(fwd_a[29]), .I1(fwd_b[29]), .I2(fwd_b[28]), .I3(fwd_a[28]), .O(wb_BrLt_i_10_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_11 (.I0(fwd_a[27]), .I1(fwd_b[27]), .I2(fwd_b[26]), .I3(fwd_a[26]), .O(wb_BrLt_i_11_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_12 (.I0(fwd_a[25]), .I1(fwd_b[25]), .I2(fwd_b[24]), .I3(fwd_a[24]), .O(wb_BrLt_i_12_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_15 (.I0(fwd_b[28]), .I1(fwd_a[28]), .I2(fwd_a[29]), .I3(fwd_b[29]), .O(wb_BrLt_i_15_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_16 (.I0(fwd_b[26]), .I1(fwd_a[26]), .I2(fwd_a[27]), .I3(fwd_b[27]), .O(wb_BrLt_i_16_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_17 (.I0(fwd_b[24]), .I1(fwd_a[24]), .I2(fwd_a[25]), .I3(fwd_b[25]), .O(wb_BrLt_i_17_n_0)); LUT5 #( .INIT(32'hB8470000)) wb_BrLt_i_18 (.I0(wb_mux[30]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_reg_i_2_1), .I3(fwd_b[30]), .I4(wb_BrLt_reg_i_3_0), .O(wb_BrLt_i_18_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_19 (.I0(fwd_a[29]), .I1(fwd_b[29]), .I2(fwd_b[28]), .I3(fwd_a[28]), .O(wb_BrLt_i_19_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_20 (.I0(fwd_a[27]), .I1(fwd_b[27]), .I2(fwd_b[26]), .I3(fwd_a[26]), .O(wb_BrLt_i_20_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_21 (.I0(fwd_a[25]), .I1(fwd_b[25]), .I2(fwd_b[24]), .I3(fwd_a[24]), .O(wb_BrLt_i_21_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_23 (.I0(fwd_b[22]), .I1(fwd_a[22]), .I2(fwd_a[23]), .I3(fwd_b[23]), .O(wb_BrLt_i_23_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_24 (.I0(fwd_b[20]), .I1(fwd_a[20]), .I2(fwd_a[21]), .I3(fwd_b[21]), .O(wb_BrLt_i_24_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_25 (.I0(fwd_b[18]), .I1(fwd_a[18]), .I2(fwd_a[19]), .I3(fwd_b[19]), .O(wb_BrLt_i_25_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_26 (.I0(fwd_b[16]), .I1(fwd_a[16]), .I2(fwd_a[17]), .I3(fwd_b[17]), .O(wb_BrLt_i_26_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_27 (.I0(fwd_a[23]), .I1(fwd_b[23]), .I2(fwd_b[22]), .I3(fwd_a[22]), .O(wb_BrLt_i_27_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_28 (.I0(fwd_a[21]), .I1(fwd_b[21]), .I2(fwd_b[20]), .I3(fwd_a[20]), .O(wb_BrLt_i_28_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_29 (.I0(fwd_a[19]), .I1(fwd_b[19]), .I2(fwd_b[18]), .I3(fwd_a[18]), .O(wb_BrLt_i_29_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_30 (.I0(fwd_a[17]), .I1(fwd_b[17]), .I2(fwd_b[16]), .I3(fwd_a[16]), .O(wb_BrLt_i_30_n_0)); LUT4 #( .INIT(16'h4700)) wb_BrLt_i_31 (.I0(wb_mux[30]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_reg_i_2_1), .I3(fwd_b[30]), .O(\ex_wb_inst_reg[12] )); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_34 (.I0(fwd_b[22]), .I1(fwd_a[22]), .I2(fwd_a[23]), .I3(fwd_b[23]), .O(wb_BrLt_i_34_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_35 (.I0(fwd_b[20]), .I1(fwd_a[20]), .I2(fwd_a[21]), .I3(fwd_b[21]), .O(wb_BrLt_i_35_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_36 (.I0(fwd_b[18]), .I1(fwd_a[18]), .I2(fwd_a[19]), .I3(fwd_b[19]), .O(wb_BrLt_i_36_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_37 (.I0(fwd_b[16]), .I1(fwd_a[16]), .I2(fwd_a[17]), .I3(fwd_b[17]), .O(wb_BrLt_i_37_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_38 (.I0(fwd_a[23]), .I1(fwd_b[23]), .I2(fwd_b[22]), .I3(fwd_a[22]), .O(wb_BrLt_i_38_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_39 (.I0(fwd_a[21]), .I1(fwd_b[21]), .I2(fwd_b[20]), .I3(fwd_a[20]), .O(wb_BrLt_i_39_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_40 (.I0(fwd_a[19]), .I1(fwd_b[19]), .I2(fwd_b[18]), .I3(fwd_a[18]), .O(wb_BrLt_i_40_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_41 (.I0(fwd_a[17]), .I1(fwd_b[17]), .I2(fwd_b[16]), .I3(fwd_a[16]), .O(wb_BrLt_i_41_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_43 (.I0(fwd_b[14]), .I1(fwd_a[14]), .I2(fwd_a[15]), .I3(fwd_b[15]), .O(wb_BrLt_i_43_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_44 (.I0(fwd_b[12]), .I1(fwd_a[12]), .I2(fwd_a[13]), .I3(fwd_b[13]), .O(wb_BrLt_i_44_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_45 (.I0(fwd_b[10]), .I1(fwd_a[10]), .I2(fwd_a[11]), .I3(fwd_b[11]), .O(wb_BrLt_i_45_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_46 (.I0(fwd_b[8]), .I1(fwd_a[8]), .I2(fwd_a[9]), .I3(fwd_b[9]), .O(wb_BrLt_i_46_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_47 (.I0(fwd_a[15]), .I1(fwd_b[15]), .I2(fwd_b[14]), .I3(fwd_a[14]), .O(wb_BrLt_i_47_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_48 (.I0(fwd_a[13]), .I1(fwd_b[13]), .I2(fwd_b[12]), .I3(fwd_a[12]), .O(wb_BrLt_i_48_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_49 (.I0(fwd_a[11]), .I1(fwd_b[11]), .I2(fwd_b[10]), .I3(fwd_a[10]), .O(wb_BrLt_i_49_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_50 (.I0(fwd_a[9]), .I1(fwd_b[9]), .I2(fwd_b[8]), .I3(fwd_a[8]), .O(wb_BrLt_i_50_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_52 (.I0(fwd_b[14]), .I1(fwd_a[14]), .I2(fwd_a[15]), .I3(fwd_b[15]), .O(wb_BrLt_i_52_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_53 (.I0(fwd_b[12]), .I1(fwd_a[12]), .I2(fwd_a[13]), .I3(fwd_b[13]), .O(wb_BrLt_i_53_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_54 (.I0(fwd_b[10]), .I1(fwd_a[10]), .I2(fwd_a[11]), .I3(fwd_b[11]), .O(wb_BrLt_i_54_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_55 (.I0(fwd_b[8]), .I1(fwd_a[8]), .I2(fwd_a[9]), .I3(fwd_b[9]), .O(wb_BrLt_i_55_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_56 (.I0(fwd_a[15]), .I1(fwd_b[15]), .I2(fwd_b[14]), .I3(fwd_a[14]), .O(wb_BrLt_i_56_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_57 (.I0(fwd_a[13]), .I1(fwd_b[13]), .I2(fwd_b[12]), .I3(fwd_a[12]), .O(wb_BrLt_i_57_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_58 (.I0(fwd_a[11]), .I1(fwd_b[11]), .I2(fwd_b[10]), .I3(fwd_a[10]), .O(wb_BrLt_i_58_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_59 (.I0(fwd_a[9]), .I1(fwd_b[9]), .I2(fwd_b[8]), .I3(fwd_a[8]), .O(wb_BrLt_i_59_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_6 (.I0(fwd_b[28]), .I1(fwd_a[28]), .I2(fwd_a[29]), .I3(fwd_b[29]), .O(wb_BrLt_i_6_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_60 (.I0(fwd_b[6]), .I1(fwd_a[6]), .I2(fwd_a[7]), .I3(fwd_b[7]), .O(wb_BrLt_i_60_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_61 (.I0(fwd_b[4]), .I1(fwd_a[4]), .I2(fwd_a[5]), .I3(fwd_b[5]), .O(wb_BrLt_i_61_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_62 (.I0(fwd_b[2]), .I1(fwd_a[2]), .I2(fwd_a[3]), .I3(fwd_b[3]), .O(wb_BrLt_i_62_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_63 (.I0(fwd_b[0]), .I1(fwd_a[0]), .I2(fwd_a[1]), .I3(fwd_b[1]), .O(wb_BrLt_i_63_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_64 (.I0(fwd_a[7]), .I1(fwd_b[7]), .I2(fwd_b[6]), .I3(fwd_a[6]), .O(wb_BrLt_i_64_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_65 (.I0(fwd_a[5]), .I1(fwd_b[5]), .I2(fwd_b[4]), .I3(fwd_a[4]), .O(wb_BrLt_i_65_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_66 (.I0(fwd_a[3]), .I1(fwd_b[3]), .I2(fwd_b[2]), .I3(fwd_a[2]), .O(wb_BrLt_i_66_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_67 (.I0(fwd_a[1]), .I1(fwd_b[1]), .I2(fwd_b[0]), .I3(fwd_a[0]), .O(wb_BrLt_i_67_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_68 (.I0(fwd_b[6]), .I1(fwd_a[6]), .I2(fwd_a[7]), .I3(fwd_b[7]), .O(wb_BrLt_i_68_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_69 (.I0(fwd_b[4]), .I1(fwd_a[4]), .I2(fwd_a[5]), .I3(fwd_b[5]), .O(wb_BrLt_i_69_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_7 (.I0(fwd_b[26]), .I1(fwd_a[26]), .I2(fwd_a[27]), .I3(fwd_b[27]), .O(wb_BrLt_i_7_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_70 (.I0(fwd_b[2]), .I1(fwd_a[2]), .I2(fwd_a[3]), .I3(fwd_b[3]), .O(wb_BrLt_i_70_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_71 (.I0(fwd_b[0]), .I1(fwd_a[0]), .I2(fwd_a[1]), .I3(fwd_b[1]), .O(wb_BrLt_i_71_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_72 (.I0(fwd_a[7]), .I1(fwd_b[7]), .I2(fwd_b[6]), .I3(fwd_a[6]), .O(wb_BrLt_i_72_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_73 (.I0(fwd_a[5]), .I1(fwd_b[5]), .I2(fwd_b[4]), .I3(fwd_a[4]), .O(wb_BrLt_i_73_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_74 (.I0(fwd_a[3]), .I1(fwd_b[3]), .I2(fwd_b[2]), .I3(fwd_a[2]), .O(wb_BrLt_i_74_n_0)); LUT4 #( .INIT(16'h9009)) wb_BrLt_i_75 (.I0(fwd_a[1]), .I1(fwd_b[1]), .I2(fwd_b[0]), .I3(fwd_a[0]), .O(wb_BrLt_i_75_n_0)); LUT4 #( .INIT(16'h2F02)) wb_BrLt_i_8 (.I0(fwd_b[24]), .I1(fwd_a[24]), .I2(fwd_a[25]), .I3(fwd_b[25]), .O(wb_BrLt_i_8_n_0)); LUT5 #( .INIT(32'hB8470000)) wb_BrLt_i_9 (.I0(wb_mux[30]), .I1(wb_BrLt_reg_i_2_0), .I2(wb_BrLt_reg_i_2_1), .I3(fwd_b[30]), .I4(wb_BrLt_reg_i_2_2), .O(wb_BrLt_i_9_n_0)); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 wb_BrLt_reg_i_13 (.CI(wb_BrLt_reg_i_33_n_0), .CO({wb_BrLt_reg_i_13_n_0,wb_BrLt_reg_i_13_n_1,wb_BrLt_reg_i_13_n_2,wb_BrLt_reg_i_13_n_3}), .CYINIT(\<const0> ), .DI({wb_BrLt_i_34_n_0,wb_BrLt_i_35_n_0,wb_BrLt_i_36_n_0,wb_BrLt_i_37_n_0}), .S({wb_BrLt_i_38_n_0,wb_BrLt_i_39_n_0,wb_BrLt_i_40_n_0,wb_BrLt_i_41_n_0})); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 wb_BrLt_reg_i_2 (.CI(wb_BrLt_reg_i_4_n_0), .CO({wb_BrLt_reg_i_2_n_0,wb_BrLt_reg_i_2_n_1,wb_BrLt_reg_i_2_n_2,wb_BrLt_reg_i_2_n_3}), .CYINIT(\<const0> ), .DI({wb_BrLt_reg,wb_BrLt_i_6_n_0,wb_BrLt_i_7_n_0,wb_BrLt_i_8_n_0}), .S({wb_BrLt_i_9_n_0,wb_BrLt_i_10_n_0,wb_BrLt_i_11_n_0,wb_BrLt_i_12_n_0})); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 wb_BrLt_reg_i_22 (.CI(wb_BrLt_reg_i_42_n_0), .CO({wb_BrLt_reg_i_22_n_0,wb_BrLt_reg_i_22_n_1,wb_BrLt_reg_i_22_n_2,wb_BrLt_reg_i_22_n_3}), .CYINIT(\<const0> ), .DI({wb_BrLt_i_43_n_0,wb_BrLt_i_44_n_0,wb_BrLt_i_45_n_0,wb_BrLt_i_46_n_0}), .S({wb_BrLt_i_47_n_0,wb_BrLt_i_48_n_0,wb_BrLt_i_49_n_0,wb_BrLt_i_50_n_0})); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 wb_BrLt_reg_i_3 (.CI(wb_BrLt_reg_i_13_n_0), .CO({wb_BrLt_reg_i_3_n_0,wb_BrLt_reg_i_3_n_1,wb_BrLt_reg_i_3_n_2,wb_BrLt_reg_i_3_n_3}), .CYINIT(\<const0> ), .DI({DI,wb_BrLt_i_15_n_0,wb_BrLt_i_16_n_0,wb_BrLt_i_17_n_0}), .S({wb_BrLt_i_18_n_0,wb_BrLt_i_19_n_0,wb_BrLt_i_20_n_0,wb_BrLt_i_21_n_0})); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 wb_BrLt_reg_i_33 (.CI(wb_BrLt_reg_i_51_n_0), .CO({wb_BrLt_reg_i_33_n_0,wb_BrLt_reg_i_33_n_1,wb_BrLt_reg_i_33_n_2,wb_BrLt_reg_i_33_n_3}), .CYINIT(\<const0> ), .DI({wb_BrLt_i_52_n_0,wb_BrLt_i_53_n_0,wb_BrLt_i_54_n_0,wb_BrLt_i_55_n_0}), .S({wb_BrLt_i_56_n_0,wb_BrLt_i_57_n_0,wb_BrLt_i_58_n_0,wb_BrLt_i_59_n_0})); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 wb_BrLt_reg_i_4 (.CI(wb_BrLt_reg_i_22_n_0), .CO({wb_BrLt_reg_i_4_n_0,wb_BrLt_reg_i_4_n_1,wb_BrLt_reg_i_4_n_2,wb_BrLt_reg_i_4_n_3}), .CYINIT(\<const0> ), .DI({wb_BrLt_i_23_n_0,wb_BrLt_i_24_n_0,wb_BrLt_i_25_n_0,wb_BrLt_i_26_n_0}), .S({wb_BrLt_i_27_n_0,wb_BrLt_i_28_n_0,wb_BrLt_i_29_n_0,wb_BrLt_i_30_n_0})); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 wb_BrLt_reg_i_42 (.CI(\<const0> ), .CO({wb_BrLt_reg_i_42_n_0,wb_BrLt_reg_i_42_n_1,wb_BrLt_reg_i_42_n_2,wb_BrLt_reg_i_42_n_3}), .CYINIT(\<const0> ), .DI({wb_BrLt_i_60_n_0,wb_BrLt_i_61_n_0,wb_BrLt_i_62_n_0,wb_BrLt_i_63_n_0}), .S({wb_BrLt_i_64_n_0,wb_BrLt_i_65_n_0,wb_BrLt_i_66_n_0,wb_BrLt_i_67_n_0})); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 wb_BrLt_reg_i_51 (.CI(\<const0> ), .CO({wb_BrLt_reg_i_51_n_0,wb_BrLt_reg_i_51_n_1,wb_BrLt_reg_i_51_n_2,wb_BrLt_reg_i_51_n_3}), .CYINIT(\<const0> ), .DI({wb_BrLt_i_68_n_0,wb_BrLt_i_69_n_0,wb_BrLt_i_70_n_0,wb_BrLt_i_71_n_0}), .S({wb_BrLt_i_72_n_0,wb_BrLt_i_73_n_0,wb_BrLt_i_74_n_0,wb_BrLt_i_75_n_0})); LUT6 #( .INIT(64'hFFFFFFFF54440000)) \wb_alu[0]_i_1 (.I0(ALUSel[1]), .I1(\wb_alu[0]_i_2_n_0 ), .I2(\wb_alu[0]_i_3_n_0 ), .I3(\wb_alu[0]_i_4_n_0 ), .I4(ALUSel[2]), .I5(\wb_alu[0]_i_5_n_0 ), .O(ex_alu[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[0]_i_10 (.I0(a_mux[27]), .I1(a_mux[26]), .I2(b_mux[1]), .I3(a_mux[25]), .I4(b_mux[0]), .I5(a_mux[24]), .O(\wb_alu[0]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[0]_i_11 (.I0(a_mux[23]), .I1(a_mux[22]), .I2(b_mux[1]), .I3(a_mux[21]), .I4(b_mux[0]), .I5(a_mux[20]), .O(\wb_alu[0]_i_11_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[0]_i_12 (.I0(a_mux[19]), .I1(a_mux[18]), .I2(b_mux[1]), .I3(a_mux[17]), .I4(b_mux[0]), .I5(a_mux[16]), .O(\wb_alu[0]_i_12_n_0 )); LUT6 #( .INIT(64'hBFFFAAAAABEBAAAA)) \wb_alu[0]_i_13 (.I0(ALUSel[3]), .I1(a_mux[0]), .I2(b_mux[0]), .I3(ALUSel[1]), .I4(ALUSel[2]), .I5(ALUSel[0]), .O(\wb_alu[0]_i_13_n_0 )); LUT5 #( .INIT(32'hA0A0CFC0)) \wb_alu[0]_i_14 (.I0(\alu/data3 ), .I1(\alu/data2 ), .I2(ALUSel[1]), .I3(\alu/data0 [0]), .I4(ALUSel[0]), .O(\wb_alu[0]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT5 #( .INIT(32'hFFFFFEFF)) \wb_alu[0]_i_15 (.I0(\f_ex_imm_reg[16] [0]), .I1(b_mux[2]), .I2(b_mux[0]), .I3(a_mux[0]), .I4(b_mux[1]), .O(\wb_alu[0]_i_15_n_0 )); LUT6 #( .INIT(64'h8003000080000000)) \wb_alu[0]_i_16 (.I0(b_mux[0]), .I1(ALUSel[1]), .I2(ALUSel[2]), .I3(ALUSel[0]), .I4(ALUSel[3]), .I5(\alu/data8 [0]), .O(\wb_alu[0]_i_16_n_0 )); LUT6 #( .INIT(64'h00000000FFE200E2)) \wb_alu[0]_i_2 (.I0(\wb_alu[0]_i_6_n_0 ), .I1(b_mux[2]), .I2(\wb_alu[0]_i_7_n_0 ), .I3(\f_ex_imm_reg[16] [0]), .I4(\wb_alu[0]_i_8_n_0 ), .I5(\wb_alu[31]_i_9_n_0 ), .O(\wb_alu[0]_i_2_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_20 (.I0(a_mux[30]), .I1(b_mux[30]), .I2(\wb_alu_reg[0]_i_18_1 ), .I3(\wb_alu_reg[0]_i_18_0 ), .O(\wb_alu[0]_i_20_n_0 )); LUT6 #( .INIT(64'h00B80000B8FFB8B8)) \wb_alu[0]_i_21 (.I0(Q[29]), .I1(BSel), .I2(fwd_b[29]), .I3(a_mux[28]), .I4(b_mux[28]), .I5(a_mux[29]), .O(\wb_alu[0]_i_21_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_22 (.I0(a_mux[26]), .I1(b_mux[26]), .I2(a_mux[27]), .I3(b_mux[27]), .O(\wb_alu[0]_i_22_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_23 (.I0(a_mux[24]), .I1(b_mux[24]), .I2(a_mux[25]), .I3(b_mux[25]), .O(\wb_alu[0]_i_23_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_24 (.I0(a_mux[30]), .I1(b_mux[30]), .I2(\wb_alu_reg[0]_i_18_0 ), .I3(\wb_alu_reg[0]_i_18_1 ), .O(\wb_alu[0]_i_24_n_0 )); LUT6 #( .INIT(64'hB84700000000B847)) \wb_alu[0]_i_25 (.I0(Q[29]), .I1(BSel), .I2(fwd_b[29]), .I3(a_mux[29]), .I4(b_mux[28]), .I5(a_mux[28]), .O(\wb_alu[0]_i_25_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_26 (.I0(a_mux[27]), .I1(b_mux[27]), .I2(b_mux[26]), .I3(a_mux[26]), .O(\wb_alu[0]_i_26_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_27 (.I0(a_mux[25]), .I1(b_mux[25]), .I2(b_mux[24]), .I3(a_mux[24]), .O(\wb_alu[0]_i_27_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_29 (.I0(a_mux[30]), .I1(b_mux[30]), .I2(\wb_alu_reg[0]_i_18_0 ), .I3(\wb_alu_reg[0]_i_18_1 ), .O(\wb_alu[0]_i_29_n_0 )); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT2 #( .INIT(4'h8)) \wb_alu[0]_i_3 (.I0(\f_ex_imm_reg[16] [1]), .I1(ALUSel[0]), .O(\wb_alu[0]_i_3_n_0 )); LUT6 #( .INIT(64'h00B80000B8FFB8B8)) \wb_alu[0]_i_30 (.I0(Q[29]), .I1(BSel), .I2(fwd_b[29]), .I3(a_mux[28]), .I4(b_mux[28]), .I5(a_mux[29]), .O(\wb_alu[0]_i_30_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_31 (.I0(a_mux[26]), .I1(b_mux[26]), .I2(a_mux[27]), .I3(b_mux[27]), .O(\wb_alu[0]_i_31_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_32 (.I0(a_mux[24]), .I1(b_mux[24]), .I2(a_mux[25]), .I3(b_mux[25]), .O(\wb_alu[0]_i_32_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_33 (.I0(a_mux[30]), .I1(b_mux[30]), .I2(\wb_alu_reg[0]_i_18_0 ), .I3(\wb_alu_reg[0]_i_18_1 ), .O(\wb_alu[0]_i_33_n_0 )); LUT6 #( .INIT(64'hB84700000000B847)) \wb_alu[0]_i_34 (.I0(Q[29]), .I1(BSel), .I2(fwd_b[29]), .I3(a_mux[29]), .I4(b_mux[28]), .I5(a_mux[28]), .O(\wb_alu[0]_i_34_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_35 (.I0(a_mux[27]), .I1(b_mux[27]), .I2(b_mux[26]), .I3(a_mux[26]), .O(\wb_alu[0]_i_35_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_36 (.I0(a_mux[25]), .I1(b_mux[25]), .I2(b_mux[24]), .I3(a_mux[24]), .O(\wb_alu[0]_i_36_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_38 (.I0(a_mux[22]), .I1(b_mux[22]), .I2(a_mux[23]), .I3(b_mux[23]), .O(\wb_alu[0]_i_38_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_39 (.I0(a_mux[20]), .I1(b_mux[20]), .I2(a_mux[21]), .I3(b_mux[21]), .O(\wb_alu[0]_i_39_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[0]_i_4 (.I0(\wb_alu[0]_i_9_n_0 ), .I1(\wb_alu[0]_i_10_n_0 ), .I2(\f_ex_imm_reg[16] [0]), .I3(\wb_alu[0]_i_11_n_0 ), .I4(b_mux[2]), .I5(\wb_alu[0]_i_12_n_0 ), .O(\wb_alu[0]_i_4_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_40 (.I0(a_mux[18]), .I1(b_mux[18]), .I2(a_mux[19]), .I3(b_mux[19]), .O(\wb_alu[0]_i_40_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_41 (.I0(a_mux[16]), .I1(\f_ex_imm_reg[16] [2]), .I2(a_mux[17]), .I3(b_mux[17]), .O(\wb_alu[0]_i_41_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_42 (.I0(a_mux[22]), .I1(b_mux[22]), .I2(a_mux[23]), .I3(b_mux[23]), .O(\wb_alu[0]_i_42_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_43 (.I0(a_mux[20]), .I1(b_mux[20]), .I2(a_mux[21]), .I3(b_mux[21]), .O(\wb_alu[0]_i_43_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_44 (.I0(a_mux[18]), .I1(b_mux[18]), .I2(a_mux[19]), .I3(b_mux[19]), .O(\wb_alu[0]_i_44_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_45 (.I0(a_mux[16]), .I1(\f_ex_imm_reg[16] [2]), .I2(a_mux[17]), .I3(b_mux[17]), .O(\wb_alu[0]_i_45_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_47 (.I0(a_mux[22]), .I1(b_mux[22]), .I2(a_mux[23]), .I3(b_mux[23]), .O(\wb_alu[0]_i_47_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_48 (.I0(a_mux[20]), .I1(b_mux[20]), .I2(a_mux[21]), .I3(b_mux[21]), .O(\wb_alu[0]_i_48_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_49 (.I0(a_mux[18]), .I1(b_mux[18]), .I2(a_mux[19]), .I3(b_mux[19]), .O(\wb_alu[0]_i_49_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF54545455)) \wb_alu[0]_i_5 (.I0(\wb_alu[0]_i_13_n_0 ), .I1(ALUSel[2]), .I2(\wb_alu[0]_i_14_n_0 ), .I3(mem_reg_0_0_i_168_n_0), .I4(\wb_alu[0]_i_15_n_0 ), .I5(\wb_alu[0]_i_16_n_0 ), .O(\wb_alu[0]_i_5_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_50 (.I0(a_mux[16]), .I1(\f_ex_imm_reg[16] [2]), .I2(a_mux[17]), .I3(b_mux[17]), .O(\wb_alu[0]_i_50_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_52 (.I0(a_mux[14]), .I1(b_mux[14]), .I2(a_mux[15]), .I3(b_mux[15]), .O(\wb_alu[0]_i_52_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_53 (.I0(a_mux[12]), .I1(b_mux[12]), .I2(a_mux[13]), .I3(b_mux[13]), .O(\wb_alu[0]_i_53_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_54 (.I0(a_mux[10]), .I1(b_mux[10]), .I2(a_mux[11]), .I3(b_mux[11]), .O(\wb_alu[0]_i_54_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_55 (.I0(a_mux[8]), .I1(b_mux[8]), .I2(a_mux[9]), .I3(b_mux[9]), .O(\wb_alu[0]_i_55_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_56 (.I0(a_mux[14]), .I1(b_mux[14]), .I2(b_mux[15]), .I3(a_mux[15]), .O(\wb_alu[0]_i_56_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_57 (.I0(a_mux[12]), .I1(b_mux[12]), .I2(a_mux[13]), .I3(b_mux[13]), .O(\wb_alu[0]_i_57_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_58 (.I0(a_mux[10]), .I1(b_mux[10]), .I2(a_mux[11]), .I3(b_mux[11]), .O(\wb_alu[0]_i_58_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_59 (.I0(a_mux[8]), .I1(b_mux[8]), .I2(a_mux[9]), .I3(b_mux[9]), .O(\wb_alu[0]_i_59_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[0]_i_6 (.I0(a_mux[3]), .I1(a_mux[2]), .I2(b_mux[1]), .I3(a_mux[1]), .I4(b_mux[0]), .I5(a_mux[0]), .O(\wb_alu[0]_i_6_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_61 (.I0(a_mux[14]), .I1(b_mux[14]), .I2(b_mux[15]), .I3(a_mux[15]), .O(\wb_alu[0]_i_61_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_62 (.I0(a_mux[12]), .I1(b_mux[12]), .I2(a_mux[13]), .I3(b_mux[13]), .O(\wb_alu[0]_i_62_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_63 (.I0(a_mux[10]), .I1(b_mux[10]), .I2(a_mux[11]), .I3(b_mux[11]), .O(\wb_alu[0]_i_63_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_64 (.I0(a_mux[8]), .I1(b_mux[8]), .I2(a_mux[9]), .I3(b_mux[9]), .O(\wb_alu[0]_i_64_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_65 (.I0(a_mux[6]), .I1(b_mux[6]), .I2(a_mux[7]), .I3(b_mux[7]), .O(\wb_alu[0]_i_65_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_66 (.I0(a_mux[4]), .I1(\f_ex_imm_reg[16] [1]), .I2(a_mux[5]), .I3(b_mux[5]), .O(\wb_alu[0]_i_66_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_67 (.I0(a_mux[2]), .I1(b_mux[2]), .I2(a_mux[3]), .I3(\f_ex_imm_reg[16] [0]), .O(\wb_alu[0]_i_67_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_68 (.I0(a_mux[0]), .I1(b_mux[0]), .I2(a_mux[1]), .I3(b_mux[1]), .O(\wb_alu[0]_i_68_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_69 (.I0(b_mux[7]), .I1(a_mux[7]), .I2(a_mux[6]), .I3(b_mux[6]), .O(\wb_alu[0]_i_69_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[0]_i_7 (.I0(a_mux[7]), .I1(a_mux[6]), .I2(b_mux[1]), .I3(a_mux[5]), .I4(b_mux[0]), .I5(a_mux[4]), .O(\wb_alu[0]_i_7_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_70 (.I0(b_mux[5]), .I1(a_mux[5]), .I2(a_mux[4]), .I3(\f_ex_imm_reg[16] [1]), .O(\wb_alu[0]_i_70_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_71 (.I0(a_mux[3]), .I1(\f_ex_imm_reg[16] [0]), .I2(a_mux[2]), .I3(b_mux[2]), .O(\wb_alu[0]_i_71_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_72 (.I0(a_mux[0]), .I1(b_mux[0]), .I2(a_mux[1]), .I3(b_mux[1]), .O(\wb_alu[0]_i_72_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_73 (.I0(a_mux[6]), .I1(b_mux[6]), .I2(a_mux[7]), .I3(b_mux[7]), .O(\wb_alu[0]_i_73_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_74 (.I0(a_mux[4]), .I1(\f_ex_imm_reg[16] [1]), .I2(a_mux[5]), .I3(b_mux[5]), .O(\wb_alu[0]_i_74_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_75 (.I0(a_mux[2]), .I1(b_mux[2]), .I2(a_mux[3]), .I3(\f_ex_imm_reg[16] [0]), .O(\wb_alu[0]_i_75_n_0 )); LUT4 #( .INIT(16'h4F04)) \wb_alu[0]_i_76 (.I0(a_mux[0]), .I1(b_mux[0]), .I2(a_mux[1]), .I3(b_mux[1]), .O(\wb_alu[0]_i_76_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_77 (.I0(b_mux[7]), .I1(a_mux[7]), .I2(a_mux[6]), .I3(b_mux[6]), .O(\wb_alu[0]_i_77_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_78 (.I0(b_mux[5]), .I1(a_mux[5]), .I2(a_mux[4]), .I3(\f_ex_imm_reg[16] [1]), .O(\wb_alu[0]_i_78_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_79 (.I0(a_mux[3]), .I1(\f_ex_imm_reg[16] [0]), .I2(a_mux[2]), .I3(b_mux[2]), .O(\wb_alu[0]_i_79_n_0 )); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT3 #( .INIT(8'hB8)) \wb_alu[0]_i_8 (.I0(mem_reg_0_0_i_274_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_293_n_0), .O(\wb_alu[0]_i_8_n_0 )); LUT4 #( .INIT(16'h9009)) \wb_alu[0]_i_80 (.I0(a_mux[0]), .I1(b_mux[0]), .I2(a_mux[1]), .I3(b_mux[1]), .O(\wb_alu[0]_i_80_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[0]_i_9 (.I0(\wb_alu_reg[0]_i_18_1 ), .I1(a_mux[30]), .I2(b_mux[1]), .I3(a_mux[29]), .I4(b_mux[0]), .I5(a_mux[28]), .O(\wb_alu[0]_i_9_n_0 )); LUT6 #( .INIT(64'hFF40FF40FFFFFF40)) \wb_alu[16]_i_1 (.I0(ALUSel[3]), .I1(\wb_alu_reg[29] ), .I2(\wb_alu[16]_i_2_n_0 ), .I3(\wb_alu[16]_i_3_n_0 ), .I4(\wb_alu_reg[16] ), .I5(\wb_alu[16]_i_5_n_0 ), .O(ex_alu[16])); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[16]_i_10 (.I0(Q[16]), .I1(BSel), .I2(wb_mux[16]), .I3(mem_reg_1_0), .I4(mem_reg_2_0_i_14_0), .O(\f_ex_imm_reg[16] [2])); LUT6 #( .INIT(64'hFFFFFFFF20222000)) \wb_alu[16]_i_2 (.I0(ALUSel[0]), .I1(\f_ex_imm_reg[16] [1]), .I2(\wb_alu[16]_i_6_n_0 ), .I3(\f_ex_imm_reg[16] [0]), .I4(\wb_alu[16]_i_7_n_0 ), .I5(\wb_alu[16]_i_8_n_0 ), .O(\wb_alu[16]_i_2_n_0 )); LUT5 #( .INIT(32'h404F4040)) \wb_alu[16]_i_3 (.I0(douta_reg_0_2), .I1(\alu/data8 [16]), .I2(ALUSel[3]), .I3(\wb_alu[16]_i_9_n_0 ), .I4(ALUSel[2]), .O(\wb_alu[16]_i_3_n_0 )); LUT6 #( .INIT(64'h0F00FFDDFFDDFFDD)) \wb_alu[16]_i_5 (.I0(\wb_alu[0]_i_4_n_0 ), .I1(\f_ex_imm_reg[16] [1]), .I2(\f_ex_imm_reg[16] [2]), .I3(ALUSel[1]), .I4(ALUSel[3]), .I5(\wb_alu_reg[22] ), .O(\wb_alu[16]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT3 #( .INIT(8'hB8)) \wb_alu[16]_i_6 (.I0(mem_reg_0_0_i_271_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_272_n_0), .O(\wb_alu[16]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT3 #( .INIT(8'hB8)) \wb_alu[16]_i_7 (.I0(mem_reg_0_0_i_273_n_0), .I1(b_mux[2]), .I2(\wb_alu[28]_i_11_n_0 ), .O(\wb_alu[16]_i_7_n_0 )); LUT4 #( .INIT(16'h4F44)) \wb_alu[16]_i_8 (.I0(ALUSel[0]), .I1(\alu/data0 [16]), .I2(\wb_alu[0]_i_15_n_0 ), .I3(\wb_alu[0]_i_3_n_0 ), .O(\wb_alu[16]_i_8_n_0 )); LUT4 #( .INIT(16'h7F43)) \wb_alu[16]_i_9 (.I0(ALUSel[1]), .I1(\f_ex_imm_reg[16] [2]), .I2(a_mux[16]), .I3(ALUSel[0]), .O(\wb_alu[16]_i_9_n_0 )); LUT6 #( .INIT(64'hBAFFBAFFBAFFBA00)) \wb_alu[17]_i_1 (.I0(\wb_alu[17]_i_2_n_0 ), .I1(douta_reg_0_2), .I2(\alu/data8 [17]), .I3(ALUSel[3]), .I4(\wb_alu[17]_i_3_n_0 ), .I5(\wb_alu[17]_i_4_n_0 ), .O(ex_alu[17])); LUT4 #( .INIT(16'h80BC)) \wb_alu[17]_i_10 (.I0(ALUSel[1]), .I1(a_mux[17]), .I2(b_mux[17]), .I3(ALUSel[0]), .O(\wb_alu[17]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT3 #( .INIT(8'hB8)) \wb_alu[17]_i_11 (.I0(mem_reg_0_0_i_264_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_261_n_0), .O(\wb_alu[17]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[17]_i_12 (.I0(\wb_alu_reg[0]_i_18_1 ), .I1(b_mux[1]), .I2(a_mux[30]), .I3(b_mux[0]), .I4(a_mux[29]), .O(\wb_alu[17]_i_12_n_0 )); LUT6 #( .INIT(64'hF200F2F200000000)) \wb_alu[17]_i_2 (.I0(\wb_alu[17]_i_5_n_0 ), .I1(\f_ex_imm_reg[16] [1]), .I2(\wb_alu_reg[22] ), .I3(b_mux[17]), .I4(ALUSel[1]), .I5(\wb_alu_reg[16] ), .O(\wb_alu[17]_i_2_n_0 )); LUT6 #( .INIT(64'h88888888A8AAA888)) \wb_alu[17]_i_3 (.I0(\wb_alu_reg[29] ), .I1(\wb_alu[17]_i_7_n_0 ), .I2(\wb_alu[17]_i_8_n_0 ), .I3(\f_ex_imm_reg[16] [0]), .I4(\wb_alu[17]_i_9_n_0 ), .I5(\wb_alu[31]_i_9_n_0 ), .O(\wb_alu[17]_i_3_n_0 )); LUT6 #( .INIT(64'h8A8A8A8888888A88)) \wb_alu[17]_i_4 (.I0(ALUSel[2]), .I1(\wb_alu[17]_i_10_n_0 ), .I2(mem_reg_0_0_i_168_n_0), .I3(\wb_alu[17]_i_11_n_0 ), .I4(\f_ex_imm_reg[16] [0]), .I5(\wb_alu[25]_i_7_n_0 ), .O(\wb_alu[17]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[17]_i_5 (.I0(\wb_alu[17]_i_12_n_0 ), .I1(mem_reg_0_0_i_263_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_264_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_261_n_0), .O(\wb_alu[17]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT3 #( .INIT(8'hB8)) \wb_alu[17]_i_6 (.I0(Q[17]), .I1(BSel), .I2(fwd_b[17]), .O(b_mux[17])); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT4 #( .INIT(16'hF444)) \wb_alu[17]_i_7 (.I0(ALUSel[0]), .I1(\alu/data0 [17]), .I2(\wb_alu[0]_i_3_n_0 ), .I3(\wb_alu[1]_i_5_n_0 ), .O(\wb_alu[17]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT3 #( .INIT(8'hB8)) \wb_alu[17]_i_8 (.I0(mem_reg_0_0_i_258_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_259_n_0), .O(\wb_alu[17]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT3 #( .INIT(8'hB8)) \wb_alu[17]_i_9 (.I0(mem_reg_0_0_i_260_n_0), .I1(b_mux[2]), .I2(\wb_alu[29]_i_28_n_0 ), .O(\wb_alu[17]_i_9_n_0 )); LUT6 #( .INIT(64'h8B8B8B8B888888BB)) \wb_alu[18]_i_1 (.I0(\wb_alu[18]_i_2_n_0 ), .I1(ALUSel[3]), .I2(\wb_alu[18]_i_3_n_0 ), .I3(\wb_alu[18]_i_4_n_0 ), .I4(ALUSel[1]), .I5(ALUSel[2]), .O(ex_alu[18])); LUT6 #( .INIT(64'h4544FFFF45444544)) \wb_alu[18]_i_2 (.I0(\wb_alu[18]_i_5_n_0 ), .I1(\wb_alu_reg[22] ), .I2(\f_ex_imm_reg[16] [1]), .I3(mem_reg_0_0_i_217_n_0), .I4(douta_reg_0_2), .I5(\alu/data8 [18]), .O(\wb_alu[18]_i_2_n_0 )); LUT6 #( .INIT(64'h0DDDDDDD0D0000DD)) \wb_alu[18]_i_3 (.I0(mem_reg_0_0_i_221_n_0), .I1(mem_reg_0_0_i_168_n_0), .I2(ALUSel[1]), .I3(b_mux[18]), .I4(a_mux[18]), .I5(ALUSel[0]), .O(\wb_alu[18]_i_3_n_0 )); LUT6 #( .INIT(64'h00000000FF47FFFF)) \wb_alu[18]_i_4 (.I0(\wb_alu[18]_i_7_n_0 ), .I1(\f_ex_imm_reg[16] [0]), .I2(\wb_alu[18]_i_8_n_0 ), .I3(\f_ex_imm_reg[16] [1]), .I4(ALUSel[0]), .I5(\wb_alu[18]_i_9_n_0 ), .O(\wb_alu[18]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT3 #( .INIT(8'h5D)) \wb_alu[18]_i_5 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[18]), .O(\wb_alu[18]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT3 #( .INIT(8'hB8)) \wb_alu[18]_i_6 (.I0(Q[18]), .I1(BSel), .I2(fwd_b[18]), .O(b_mux[18])); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT3 #( .INIT(8'hB8)) \wb_alu[18]_i_7 (.I0(mem_reg_0_0_i_175_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_249_n_0), .O(\wb_alu[18]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT3 #( .INIT(8'hB8)) \wb_alu[18]_i_8 (.I0(mem_reg_0_0_i_250_n_0), .I1(b_mux[2]), .I2(\wb_alu[30]_i_13_n_0 ), .O(\wb_alu[18]_i_8_n_0 )); LUT5 #( .INIT(32'h4444F444)) \wb_alu[18]_i_9 (.I0(ALUSel[0]), .I1(\alu/data0 [18]), .I2(\wb_alu[0]_i_3_n_0 ), .I3(mem_reg_0_0_i_220_n_0), .I4(\f_ex_imm_reg[16] [0]), .O(\wb_alu[18]_i_9_n_0 )); LUT6 #( .INIT(64'hBAFFBAFFBAFFBA00)) \wb_alu[19]_i_1 (.I0(\wb_alu[19]_i_2_n_0 ), .I1(douta_reg_0_2), .I2(\alu/data8 [19]), .I3(ALUSel[3]), .I4(\wb_alu[19]_i_4_n_0 ), .I5(\wb_alu[19]_i_5_n_0 ), .O(ex_alu[19])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[19]_i_10 (.I0(\wb_alu_reg[29]_i_5_0 [16]), .I1(ASel), .I2(wb_mux[16]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_15_0), .O(a_mux[16])); LUT2 #( .INIT(4'h9)) \wb_alu[19]_i_11 (.I0(a_mux[19]), .I1(b_mux[19]), .O(\wb_alu[19]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \wb_alu[19]_i_12 (.I0(a_mux[18]), .I1(b_mux[18]), .O(\wb_alu[19]_i_12_n_0 )); LUT2 #( .INIT(4'h9)) \wb_alu[19]_i_13 (.I0(a_mux[17]), .I1(b_mux[17]), .O(\wb_alu[19]_i_13_n_0 )); LUT2 #( .INIT(4'h9)) \wb_alu[19]_i_14 (.I0(a_mux[16]), .I1(\f_ex_imm_reg[16] [2]), .O(\wb_alu[19]_i_14_n_0 )); LUT6 #( .INIT(64'h4444444444F44444)) \wb_alu[19]_i_15 (.I0(ALUSel[0]), .I1(\alu/data0 [19]), .I2(\wb_alu[0]_i_3_n_0 ), .I3(b_mux[2]), .I4(mem_reg_0_0_i_166_n_0), .I5(\f_ex_imm_reg[16] [0]), .O(\wb_alu[19]_i_15_n_0 )); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT3 #( .INIT(8'hB8)) \wb_alu[19]_i_16 (.I0(mem_reg_0_0_i_231_n_0), .I1(b_mux[2]), .I2(\wb_alu[31]_i_19_n_0 ), .O(\wb_alu[19]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT3 #( .INIT(8'hB8)) \wb_alu[19]_i_17 (.I0(mem_reg_0_0_i_164_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_230_n_0), .O(\wb_alu[19]_i_17_n_0 )); LUT4 #( .INIT(16'h80BC)) \wb_alu[19]_i_18 (.I0(ALUSel[1]), .I1(a_mux[19]), .I2(b_mux[19]), .I3(ALUSel[0]), .O(\wb_alu[19]_i_18_n_0 )); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT5 #( .INIT(32'h04FF0400)) \wb_alu[19]_i_19 (.I0(b_mux[1]), .I1(\wb_alu_reg[0]_i_18_1 ), .I2(b_mux[0]), .I3(b_mux[2]), .I4(mem_reg_0_0_i_239_n_0), .O(\wb_alu[19]_i_19_n_0 )); LUT6 #( .INIT(64'hF200F2F200000000)) \wb_alu[19]_i_2 (.I0(mem_reg_0_0_i_215_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(\wb_alu_reg[22] ), .I3(b_mux[19]), .I4(ALUSel[1]), .I5(\wb_alu_reg[16] ), .O(\wb_alu[19]_i_2_n_0 )); LUT2 #( .INIT(4'h6)) \wb_alu[19]_i_25 (.I0(a_mux[19]), .I1(b_mux[19]), .O(\wb_alu[19]_i_25_n_0 )); LUT2 #( .INIT(4'h6)) \wb_alu[19]_i_26 (.I0(a_mux[18]), .I1(b_mux[18]), .O(\wb_alu[19]_i_26_n_0 )); LUT2 #( .INIT(4'h6)) \wb_alu[19]_i_27 (.I0(a_mux[17]), .I1(b_mux[17]), .O(\wb_alu[19]_i_27_n_0 )); LUT2 #( .INIT(4'h6)) \wb_alu[19]_i_28 (.I0(a_mux[16]), .I1(\f_ex_imm_reg[16] [2]), .O(\wb_alu[19]_i_28_n_0 )); LUT6 #( .INIT(64'h8A8A8A88888A8888)) \wb_alu[19]_i_4 (.I0(\wb_alu_reg[29] ), .I1(\wb_alu[19]_i_15_n_0 ), .I2(\wb_alu[31]_i_9_n_0 ), .I3(\f_ex_imm_reg[16] [0]), .I4(\wb_alu[19]_i_16_n_0 ), .I5(\wb_alu[19]_i_17_n_0 ), .O(\wb_alu[19]_i_4_n_0 )); LUT6 #( .INIT(64'h8A8A8A8888888A88)) \wb_alu[19]_i_5 (.I0(ALUSel[2]), .I1(\wb_alu[19]_i_18_n_0 ), .I2(mem_reg_0_0_i_168_n_0), .I3(mem_reg_0_0_i_131_n_0), .I4(\f_ex_imm_reg[16] [0]), .I5(\wb_alu[19]_i_19_n_0 ), .O(\wb_alu[19]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT3 #( .INIT(8'hB8)) \wb_alu[19]_i_6 (.I0(Q[19]), .I1(BSel), .I2(fwd_b[19]), .O(b_mux[19])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[19]_i_7 (.I0(\wb_alu_reg[29]_i_5_0 [19]), .I1(ASel), .I2(wb_mux[19]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_25_1), .O(a_mux[19])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[19]_i_8 (.I0(\wb_alu_reg[29]_i_5_0 [18]), .I1(ASel), .I2(wb_mux[18]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_25_0), .O(a_mux[18])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[19]_i_9 (.I0(\wb_alu_reg[29]_i_5_0 [17]), .I1(ASel), .I2(wb_mux[17]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_15_1), .O(a_mux[17])); LUT6 #( .INIT(64'h0E00EEEEEEEEEEEE)) \wb_alu[1]_i_1 (.I0(\wb_alu[1]_i_2_n_0 ), .I1(\wb_alu[1]_i_3_n_0 ), .I2(douta_reg_0_2), .I3(\f_ex_pc_reg[30]_0 [0]), .I4(ALUSel[3]), .I5(\wb_alu[1]_i_4_n_0 ), .O(ex_alu[1])); LUT3 #( .INIT(8'hB8)) \wb_alu[1]_i_10 (.I0(Q[1]), .I1(BSel), .I2(fwd_b[1]), .O(b_mux[1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[1]_i_11 (.I0(a_mux[4]), .I1(a_mux[3]), .I2(b_mux[1]), .I3(a_mux[2]), .I4(b_mux[0]), .I5(a_mux[1]), .O(\wb_alu[1]_i_11_n_0 )); LUT5 #( .INIT(32'hFFFF44F4)) \wb_alu[1]_i_2 (.I0(mem_reg_0_0_i_62__0_n_0), .I1(\wb_alu[1]_i_5_n_0 ), .I2(\alu/data0 [1]), .I3(douta_reg_0_2), .I4(ALUSel[3]), .O(\wb_alu[1]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000FFC4FF80)) \wb_alu[1]_i_3 (.I0(\f_ex_imm_reg[16] [1]), .I1(ALUSel[0]), .I2(\wb_alu[1]_i_6_n_0 ), .I3(\wb_alu[1]_i_7_n_0 ), .I4(\wb_alu[1]_i_8_n_0 ), .I5(\wb_alu[1]_i_9_n_0 ), .O(\wb_alu[1]_i_3_n_0 )); LUT6 #( .INIT(64'h010DFFFFF1FDFFFF)) \wb_alu[1]_i_4 (.I0(\wb_alu[1]_i_8_n_0 ), .I1(\f_ex_imm_reg[16] [1]), .I2(ALUSel[1]), .I3(\wb_alu[17]_i_5_n_0 ), .I4(\wb_alu_reg[16] ), .I5(b_mux[1]), .O(\wb_alu[1]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000000005404)) \wb_alu[1]_i_5 (.I0(b_mux[1]), .I1(a_mux[1]), .I2(b_mux[0]), .I3(a_mux[0]), .I4(b_mux[2]), .I5(\f_ex_imm_reg[16] [0]), .O(\wb_alu[1]_i_5_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[1]_i_6 (.I0(mem_reg_0_0_i_289_n_0), .I1(mem_reg_0_0_i_263_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_264_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_261_n_0), .O(\wb_alu[1]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT4 #( .INIT(16'hAABE)) \wb_alu[1]_i_7 (.I0(ALUSel[1]), .I1(a_mux[1]), .I2(b_mux[1]), .I3(ALUSel[0]), .O(\wb_alu[1]_i_7_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[1]_i_8 (.I0(mem_reg_0_0_i_262_n_0), .I1(mem_reg_0_0_i_290_n_0), .I2(\f_ex_imm_reg[16] [0]), .I3(mem_reg_0_0_i_300_n_0), .I4(b_mux[2]), .I5(\wb_alu[1]_i_11_n_0 ), .O(\wb_alu[1]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT5 #( .INIT(32'h2B00FFFF)) \wb_alu[1]_i_9 (.I0(ALUSel[0]), .I1(b_mux[1]), .I2(a_mux[1]), .I3(ALUSel[1]), .I4(ALUSel[2]), .O(\wb_alu[1]_i_9_n_0 )); LUT6 #( .INIT(64'hBAFFBAFFBAFFBA00)) \wb_alu[20]_i_1 (.I0(\wb_alu[20]_i_2_n_0 ), .I1(douta_reg_0_2), .I2(\alu/data8 [20]), .I3(ALUSel[3]), .I4(\wb_alu[20]_i_3_n_0 ), .I5(\wb_alu[20]_i_4_n_0 ), .O(ex_alu[20])); LUT6 #( .INIT(64'hF200F2F200000000)) \wb_alu[20]_i_2 (.I0(mem_reg_0_0_i_199_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(\wb_alu_reg[22] ), .I3(b_mux[20]), .I4(ALUSel[1]), .I5(\wb_alu_reg[16] ), .O(\wb_alu[20]_i_2_n_0 )); LUT6 #( .INIT(64'h8A8A8A8888888A88)) \wb_alu[20]_i_3 (.I0(ALUSel[2]), .I1(\wb_alu[20]_i_6_n_0 ), .I2(mem_reg_0_0_i_168_n_0), .I3(mem_reg_0_0_i_123_n_0), .I4(\f_ex_imm_reg[16] [0]), .I5(\wb_alu[20]_i_7_n_0 ), .O(\wb_alu[20]_i_3_n_0 )); LUT6 #( .INIT(64'h8A8A8A8888888A88)) \wb_alu[20]_i_4 (.I0(\wb_alu_reg[29] ), .I1(\wb_alu[20]_i_8_n_0 ), .I2(\wb_alu[31]_i_9_n_0 ), .I3(\wb_alu[28]_i_9_n_0 ), .I4(\f_ex_imm_reg[16] [0]), .I5(\wb_alu[20]_i_9_n_0 ), .O(\wb_alu[20]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT3 #( .INIT(8'hB8)) \wb_alu[20]_i_5 (.I0(Q[20]), .I1(BSel), .I2(fwd_b[20]), .O(b_mux[20])); LUT4 #( .INIT(16'hD414)) \wb_alu[20]_i_6 (.I0(ALUSel[0]), .I1(a_mux[20]), .I2(b_mux[20]), .I3(ALUSel[1]), .O(\wb_alu[20]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT2 #( .INIT(4'h2)) \wb_alu[20]_i_7 (.I0(\wb_alu[0]_i_9_n_0 ), .I1(b_mux[2]), .O(\wb_alu[20]_i_7_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAEEEAAAEA)) \wb_alu[20]_i_8 (.I0(\wb_alu[20]_i_4_0 ), .I1(\wb_alu[0]_i_3_n_0 ), .I2(mem_reg_0_0_i_271_n_0), .I3(b_mux[2]), .I4(mem_reg_0_0_i_270_n_0), .I5(\f_ex_imm_reg[16] [0]), .O(\wb_alu[20]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT3 #( .INIT(8'hB8)) \wb_alu[20]_i_9 (.I0(mem_reg_0_0_i_272_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_273_n_0), .O(\wb_alu[20]_i_9_n_0 )); LUT6 #( .INIT(64'h8888BBBB888B888B)) \wb_alu[21]_i_1 (.I0(\wb_alu[21]_i_2_n_0 ), .I1(ALUSel[3]), .I2(\wb_alu[21]_i_3_n_0 ), .I3(ALUSel[1]), .I4(\wb_alu[21]_i_5_n_0 ), .I5(ALUSel[2]), .O(ex_alu[21])); LUT6 #( .INIT(64'h4544FFFF45444544)) \wb_alu[21]_i_2 (.I0(\wb_alu[21]_i_6_n_0 ), .I1(\wb_alu_reg[22] ), .I2(\f_ex_imm_reg[16] [1]), .I3(mem_reg_0_0_i_195_n_0), .I4(douta_reg_0_2), .I5(\alu/data8 [21]), .O(\wb_alu[21]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000FF47FFFF)) \wb_alu[21]_i_3 (.I0(\wb_alu[21]_i_7_n_0 ), .I1(\f_ex_imm_reg[16] [0]), .I2(\wb_alu[29]_i_18_n_0 ), .I3(\f_ex_imm_reg[16] [1]), .I4(ALUSel[0]), .I5(\wb_alu[21]_i_8_n_0 ), .O(\wb_alu[21]_i_3_n_0 )); LUT6 #( .INIT(64'h00D0D0DDDDD0D0DD)) \wb_alu[21]_i_5 (.I0(mem_reg_0_0_i_185_n_0), .I1(mem_reg_0_0_i_168_n_0), .I2(ALUSel[0]), .I3(a_mux[21]), .I4(b_mux[21]), .I5(ALUSel[1]), .O(\wb_alu[21]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT3 #( .INIT(8'h5D)) \wb_alu[21]_i_6 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[21]), .O(\wb_alu[21]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT3 #( .INIT(8'hB8)) \wb_alu[21]_i_7 (.I0(mem_reg_0_0_i_259_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_260_n_0), .O(\wb_alu[21]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF000008A8)) \wb_alu[21]_i_8 (.I0(\wb_alu[0]_i_3_n_0 ), .I1(mem_reg_0_0_i_258_n_0), .I2(b_mux[2]), .I3(mem_reg_0_0_i_257_n_0), .I4(\f_ex_imm_reg[16] [0]), .I5(\wb_alu[21]_i_3_0 ), .O(\wb_alu[21]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT3 #( .INIT(8'hB8)) \wb_alu[21]_i_9 (.I0(Q[21]), .I1(BSel), .I2(fwd_b[21]), .O(b_mux[21])); LUT6 #( .INIT(64'hBAFFBAFFBAFFBA00)) \wb_alu[22]_i_1 (.I0(\wb_alu[22]_i_2_n_0 ), .I1(douta_reg_0_2), .I2(\alu/data8 [22]), .I3(ALUSel[3]), .I4(\wb_alu[22]_i_3_n_0 ), .I5(\wb_alu[22]_i_4_n_0 ), .O(ex_alu[22])); LUT6 #( .INIT(64'hF200F2F200000000)) \wb_alu[22]_i_2 (.I0(mem_reg_0_0_i_180_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(\wb_alu_reg[22] ), .I3(b_mux[22]), .I4(ALUSel[1]), .I5(\wb_alu_reg[16] ), .O(\wb_alu[22]_i_2_n_0 )); LUT6 #( .INIT(64'h88888888A8AAA888)) \wb_alu[22]_i_3 (.I0(\wb_alu_reg[29] ), .I1(\wb_alu[22]_i_6_n_0 ), .I2(\wb_alu[22]_i_7_n_0 ), .I3(\f_ex_imm_reg[16] [0]), .I4(\wb_alu[30]_i_8_n_0 ), .I5(\wb_alu[31]_i_9_n_0 ), .O(\wb_alu[22]_i_3_n_0 )); LUT6 #( .INIT(64'h8A8A8A8888888A88)) \wb_alu[22]_i_4 (.I0(ALUSel[2]), .I1(\wb_alu[22]_i_8_n_0 ), .I2(mem_reg_0_0_i_168_n_0), .I3(mem_reg_0_0_i_109_n_0), .I4(\f_ex_imm_reg[16] [0]), .I5(\wb_alu[22]_i_9_n_0 ), .O(\wb_alu[22]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT3 #( .INIT(8'hB8)) \wb_alu[22]_i_5 (.I0(Q[22]), .I1(BSel), .I2(fwd_b[22]), .O(b_mux[22])); LUT6 #( .INIT(64'hFFFFFFFF0000A808)) \wb_alu[22]_i_6 (.I0(\wb_alu[0]_i_3_n_0 ), .I1(mem_reg_0_0_i_175_n_0), .I2(b_mux[2]), .I3(mem_reg_0_0_i_176_n_0), .I4(\f_ex_imm_reg[16] [0]), .I5(\wb_alu[22]_i_3_0 ), .O(\wb_alu[22]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT3 #( .INIT(8'hB8)) \wb_alu[22]_i_7 (.I0(mem_reg_0_0_i_249_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_250_n_0), .O(\wb_alu[22]_i_7_n_0 )); LUT4 #( .INIT(16'h80BC)) \wb_alu[22]_i_8 (.I0(ALUSel[1]), .I1(a_mux[22]), .I2(b_mux[22]), .I3(ALUSel[0]), .O(\wb_alu[22]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT5 #( .INIT(32'h00005404)) \wb_alu[22]_i_9 (.I0(b_mux[2]), .I1(a_mux[30]), .I2(b_mux[0]), .I3(\wb_alu_reg[0]_i_18_1 ), .I4(b_mux[1]), .O(\wb_alu[22]_i_9_n_0 )); LUT6 #( .INIT(64'hBAFFBAFFBAFFBA00)) \wb_alu[23]_i_1 (.I0(\wb_alu[23]_i_2_n_0 ), .I1(douta_reg_0_2), .I2(\alu/data8 [23]), .I3(ALUSel[3]), .I4(\wb_alu[23]_i_4_n_0 ), .I5(\wb_alu[23]_i_5_n_0 ), .O(ex_alu[23])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[23]_i_10 (.I0(\wb_alu_reg[29]_i_5_0 [20]), .I1(ASel), .I2(wb_mux[20]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_14_0), .O(a_mux[20])); LUT2 #( .INIT(4'h9)) \wb_alu[23]_i_11 (.I0(a_mux[23]), .I1(b_mux[23]), .O(\wb_alu[23]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \wb_alu[23]_i_12 (.I0(a_mux[22]), .I1(b_mux[22]), .O(\wb_alu[23]_i_12_n_0 )); LUT2 #( .INIT(4'h9)) \wb_alu[23]_i_13 (.I0(a_mux[21]), .I1(b_mux[21]), .O(\wb_alu[23]_i_13_n_0 )); LUT2 #( .INIT(4'h9)) \wb_alu[23]_i_14 (.I0(a_mux[20]), .I1(b_mux[20]), .O(\wb_alu[23]_i_14_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAEEEAAAEA)) \wb_alu[23]_i_15 (.I0(\wb_alu[23]_i_4_0 ), .I1(\wb_alu[0]_i_3_n_0 ), .I2(mem_reg_0_0_i_164_n_0), .I3(b_mux[2]), .I4(mem_reg_0_0_i_166_n_0), .I5(\f_ex_imm_reg[16] [0]), .O(\wb_alu[23]_i_15_n_0 )); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT3 #( .INIT(8'hB8)) \wb_alu[23]_i_16 (.I0(mem_reg_0_0_i_230_n_0), .I1(b_mux[2]), .I2(mem_reg_0_0_i_231_n_0), .O(\wb_alu[23]_i_16_n_0 )); LUT4 #( .INIT(16'h80BC)) \wb_alu[23]_i_17 (.I0(ALUSel[1]), .I1(a_mux[23]), .I2(b_mux[23]), .I3(ALUSel[0]), .O(\wb_alu[23]_i_17_n_0 )); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT4 #( .INIT(16'h0004)) \wb_alu[23]_i_18 (.I0(b_mux[0]), .I1(\wb_alu_reg[0]_i_18_1 ), .I2(b_mux[1]), .I3(b_mux[2]), .O(\wb_alu[23]_i_18_n_0 )); LUT6 #( .INIT(64'hF200F2F200000000)) \wb_alu[23]_i_2 (.I0(mem_reg_0_0_i_173_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(\wb_alu_reg[22] ), .I3(b_mux[23]), .I4(ALUSel[1]), .I5(\wb_alu_reg[16] ), .O(\wb_alu[23]_i_2_n_0 )); LUT6 #( .INIT(64'h88888888A8AAA888)) \wb_alu[23]_i_4 (.I0(\wb_alu_reg[29] ), .I1(\wb_alu[23]_i_15_n_0 ), .I2(\wb_alu[23]_i_16_n_0 ), .I3(\f_ex_imm_reg[16] [0]), .I4(\wb_alu[31]_i_10_n_0 ), .I5(\wb_alu[31]_i_9_n_0 ), .O(\wb_alu[23]_i_4_n_0 )); LUT6 #( .INIT(64'h8A8A8A8888888A88)) \wb_alu[23]_i_5 (.I0(ALUSel[2]), .I1(\wb_alu[23]_i_17_n_0 ), .I2(mem_reg_0_0_i_168_n_0), .I3(mem_reg_0_0_i_99_n_0), .I4(\f_ex_imm_reg[16] [0]), .I5(\wb_alu[23]_i_18_n_0 ), .O(\wb_alu[23]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT3 #( .INIT(8'hB8)) \wb_alu[23]_i_6 (.I0(Q[23]), .I1(BSel), .I2(fwd_b[23]), .O(b_mux[23])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[23]_i_7 (.I0(\wb_alu_reg[29]_i_5_0 [23]), .I1(ASel), .I2(wb_mux[23]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_13_1), .O(a_mux[23])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[23]_i_8 (.I0(\wb_alu_reg[29]_i_5_0 [22]), .I1(ASel), .I2(wb_mux[22]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_13_0), .O(a_mux[22])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[23]_i_9 (.I0(\wb_alu_reg[29]_i_5_0 [21]), .I1(ASel), .I2(wb_mux[21]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_24_0), .O(a_mux[21])); LUT6 #( .INIT(64'hF4FFF400F4FFF4FF)) \wb_alu[24]_i_1 (.I0(douta_reg_0_2), .I1(\f_ex_pc_reg[30]_0 [11]), .I2(\wb_alu[24]_i_2_n_0 ), .I3(ALUSel[3]), .I4(\wb_alu[24]_i_3_n_0 ), .I5(\wb_alu[24]_i_4_n_0 ), .O(ex_alu[24])); LUT6 #( .INIT(64'hF200F2F200000000)) \wb_alu[24]_i_2 (.I0(mem_reg_0_0_i_162_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(\wb_alu_reg[22] ), .I3(b_mux[24]), .I4(ALUSel[1]), .I5(\wb_alu_reg[16] ), .O(\wb_alu[24]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT4 #( .INIT(16'h888A)) \wb_alu[24]_i_3 (.I0(ALUSel[2]), .I1(\wb_alu[24]_i_6_n_0 ), .I2(mem_reg_0_0_i_168_n_0), .I3(mem_reg_0_0_i_158_n_0), .O(\wb_alu[24]_i_3_n_0 )); LUT6 #( .INIT(64'h575757F7F7F757F7)) \wb_alu[24]_i_4 (.I0(\wb_alu_reg[29] ), .I1(\alu/data0 [24]), .I2(ALUSel[0]), .I3(\wb_alu[24]_i_7_n_0 ), .I4(\f_ex_imm_reg[16] [1]), .I5(mem_reg_0_0_i_157_n_0), .O(\wb_alu[24]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT3 #( .INIT(8'hB8)) \wb_alu[24]_i_5 (.I0(Q[24]), .I1(BSel), .I2(fwd_b[24]), .O(b_mux[24])); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT4 #( .INIT(16'hA330)) \wb_alu[24]_i_6 (.I0(ALUSel[1]), .I1(ALUSel[0]), .I2(b_mux[24]), .I3(a_mux[24]), .O(\wb_alu[24]_i_6_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[24]_i_7 (.I0(mem_reg_0_0_i_273_n_0), .I1(\wb_alu[28]_i_11_n_0 ), .I2(\f_ex_imm_reg[16] [0]), .I3(\wb_alu[28]_i_12_n_0 ), .I4(b_mux[2]), .I5(\wb_alu[28]_i_13_n_0 ), .O(\wb_alu[24]_i_7_n_0 )); LUT6 #( .INIT(64'hF4FFF400F4FFF4FF)) \wb_alu[25]_i_1 (.I0(douta_reg_0_2), .I1(\f_ex_pc_reg[30]_0 [12]), .I2(\wb_alu[25]_i_2_n_0 ), .I3(ALUSel[3]), .I4(\wb_alu[25]_i_3_n_0 ), .I5(\wb_alu[25]_i_4_n_0 ), .O(ex_alu[25])); LUT6 #( .INIT(64'hF200F2F200000000)) \wb_alu[25]_i_2 (.I0(mem_reg_0_0_i_155_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(\wb_alu_reg[22] ), .I3(b_mux[25]), .I4(ALUSel[1]), .I5(\wb_alu_reg[16] ), .O(\wb_alu[25]_i_2_n_0 )); LUT5 #( .INIT(32'h88888A88)) \wb_alu[25]_i_3 (.I0(ALUSel[2]), .I1(\wb_alu[25]_i_6_n_0 ), .I2(mem_reg_0_0_i_168_n_0), .I3(\wb_alu[25]_i_7_n_0 ), .I4(\f_ex_imm_reg[16] [0]), .O(\wb_alu[25]_i_3_n_0 )); LUT6 #( .INIT(64'h575757F7F7F757F7)) \wb_alu[25]_i_4 (.I0(\wb_alu_reg[29] ), .I1(\alu/data0 [25]), .I2(ALUSel[0]), .I3(\wb_alu[25]_i_8_n_0 ), .I4(\f_ex_imm_reg[16] [1]), .I5(mem_reg_0_0_i_143_n_0), .O(\wb_alu[25]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT3 #( .INIT(8'hB8)) \wb_alu[25]_i_5 (.I0(Q[25]), .I1(BSel), .I2(fwd_b[25]), .O(b_mux[25])); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT4 #( .INIT(16'hA330)) \wb_alu[25]_i_6 (.I0(ALUSel[1]), .I1(ALUSel[0]), .I2(b_mux[25]), .I3(a_mux[25]), .O(\wb_alu[25]_i_6_n_0 )); LUT6 #( .INIT(64'h2F20FFFF2F200000)) \wb_alu[25]_i_7 (.I0(\wb_alu_reg[0]_i_18_1 ), .I1(b_mux[0]), .I2(b_mux[1]), .I3(mem_reg_0_0_i_269_n_0), .I4(b_mux[2]), .I5(mem_reg_0_0_i_263_n_0), .O(\wb_alu[25]_i_7_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[25]_i_8 (.I0(mem_reg_0_0_i_260_n_0), .I1(\wb_alu[29]_i_28_n_0 ), .I2(\f_ex_imm_reg[16] [0]), .I3(\wb_alu[29]_i_29_n_0 ), .I4(b_mux[2]), .I5(\wb_alu[29]_i_30_n_0 ), .O(\wb_alu[25]_i_8_n_0 )); LUT6 #( .INIT(64'hF4FFF400F4FFF4FF)) \wb_alu[26]_i_1 (.I0(douta_reg_0_2), .I1(\f_ex_pc_reg[30]_0 [13]), .I2(\wb_alu[26]_i_2_n_0 ), .I3(ALUSel[3]), .I4(\wb_alu[26]_i_3_n_0 ), .I5(\wb_alu[26]_i_4_n_0 ), .O(ex_alu[26])); LUT6 #( .INIT(64'hF200F2F200000000)) \wb_alu[26]_i_2 (.I0(mem_reg_0_0_i_136_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(\wb_alu_reg[22] ), .I3(b_mux[26]), .I4(ALUSel[1]), .I5(\wb_alu_reg[16] ), .O(\wb_alu[26]_i_2_n_0 )); LUT4 #( .INIT(16'h888A)) \wb_alu[26]_i_3 (.I0(ALUSel[2]), .I1(\wb_alu[26]_i_6_n_0 ), .I2(mem_reg_0_0_i_168_n_0), .I3(\wb_alu[26]_i_7_n_0 ), .O(\wb_alu[26]_i_3_n_0 )); LUT6 #( .INIT(64'h575757F7F7F757F7)) \wb_alu[26]_i_4 (.I0(\wb_alu_reg[29] ), .I1(\alu/data0 [26]), .I2(ALUSel[0]), .I3(\wb_alu[26]_i_8_n_0 ), .I4(\f_ex_imm_reg[16] [1]), .I5(mem_reg_0_0_i_140_n_0), .O(\wb_alu[26]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT3 #( .INIT(8'hB8)) \wb_alu[26]_i_5 (.I0(Q[26]), .I1(BSel), .I2(fwd_b[26]), .O(b_mux[26])); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT4 #( .INIT(16'hA330)) \wb_alu[26]_i_6 (.I0(ALUSel[1]), .I1(ALUSel[0]), .I2(b_mux[26]), .I3(a_mux[26]), .O(\wb_alu[26]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT4 #( .INIT(16'hABFB)) \wb_alu[26]_i_7 (.I0(\f_ex_imm_reg[16] [0]), .I1(mem_reg_0_0_i_253_n_0), .I2(b_mux[2]), .I3(mem_reg_0_0_i_285_n_0), .O(\wb_alu[26]_i_7_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[26]_i_8 (.I0(mem_reg_0_0_i_250_n_0), .I1(\wb_alu[30]_i_13_n_0 ), .I2(\f_ex_imm_reg[16] [0]), .I3(\wb_alu[30]_i_14_n_0 ), .I4(b_mux[2]), .I5(\wb_alu[30]_i_10_n_0 ), .O(\wb_alu[26]_i_8_n_0 )); LUT6 #( .INIT(64'hF4FFF400F4FFF4FF)) \wb_alu[27]_i_1 (.I0(douta_reg_0_2), .I1(\f_ex_pc_reg[30]_0 [14]), .I2(\wb_alu[27]_i_3_n_0 ), .I3(ALUSel[3]), .I4(\wb_alu[27]_i_4_n_0 ), .I5(\wb_alu[27]_i_5_n_0 ), .O(ex_alu[27])); LUT2 #( .INIT(4'h9)) \wb_alu[27]_i_10 (.I0(a_mux[27]), .I1(b_mux[27]), .O(\wb_alu[27]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \wb_alu[27]_i_11 (.I0(a_mux[26]), .I1(b_mux[26]), .O(\wb_alu[27]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \wb_alu[27]_i_12 (.I0(a_mux[25]), .I1(b_mux[25]), .O(\wb_alu[27]_i_12_n_0 )); LUT2 #( .INIT(4'h9)) \wb_alu[27]_i_13 (.I0(a_mux[24]), .I1(b_mux[24]), .O(\wb_alu[27]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT3 #( .INIT(8'hB8)) \wb_alu[27]_i_14 (.I0(Q[27]), .I1(BSel), .I2(fwd_b[27]), .O(b_mux[27])); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT4 #( .INIT(16'hA330)) \wb_alu[27]_i_15 (.I0(ALUSel[1]), .I1(ALUSel[0]), .I2(b_mux[27]), .I3(a_mux[27]), .O(\wb_alu[27]_i_15_n_0 )); LUT6 #( .INIT(64'hFBFBFBFBFBABFBFB)) \wb_alu[27]_i_16 (.I0(\f_ex_imm_reg[16] [0]), .I1(mem_reg_0_0_i_239_n_0), .I2(b_mux[2]), .I3(b_mux[0]), .I4(\wb_alu_reg[0]_i_18_1 ), .I5(b_mux[1]), .O(\wb_alu[27]_i_16_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[27]_i_17 (.I0(mem_reg_0_0_i_231_n_0), .I1(\wb_alu[31]_i_19_n_0 ), .I2(\f_ex_imm_reg[16] [0]), .I3(\wb_alu[31]_i_20_n_0 ), .I4(b_mux[2]), .I5(\wb_alu[31]_i_12_n_0 ), .O(\wb_alu[27]_i_17_n_0 )); LUT6 #( .INIT(64'hF100F1F100000000)) \wb_alu[27]_i_3 (.I0(\f_ex_imm_reg[16] [1]), .I1(mem_reg_0_0_i_135_n_0), .I2(\wb_alu_reg[22] ), .I3(b_mux[27]), .I4(ALUSel[1]), .I5(\wb_alu_reg[16] ), .O(\wb_alu[27]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT4 #( .INIT(16'h888A)) \wb_alu[27]_i_4 (.I0(ALUSel[2]), .I1(\wb_alu[27]_i_15_n_0 ), .I2(mem_reg_0_0_i_168_n_0), .I3(\wb_alu[27]_i_16_n_0 ), .O(\wb_alu[27]_i_4_n_0 )); LUT6 #( .INIT(64'h575757F7F7F757F7)) \wb_alu[27]_i_5 (.I0(\wb_alu_reg[29] ), .I1(\alu/data0 [27]), .I2(ALUSel[0]), .I3(\wb_alu[27]_i_17_n_0 ), .I4(\f_ex_imm_reg[16] [1]), .I5(mem_reg_0_0_i_128_n_0), .O(\wb_alu[27]_i_5_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[27]_i_6 (.I0(\wb_alu_reg[29]_i_5_0 [27]), .I1(ASel), .I2(wb_mux[27]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_7_0), .O(a_mux[27])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[27]_i_7 (.I0(\wb_alu_reg[29]_i_5_0 [26]), .I1(ASel), .I2(wb_mux[26]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_7_1), .O(a_mux[26])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[27]_i_8 (.I0(\wb_alu_reg[29]_i_5_0 [25]), .I1(ASel), .I2(wb_mux[25]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_8_1), .O(a_mux[25])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[27]_i_9 (.I0(\wb_alu_reg[29]_i_5_0 [24]), .I1(ASel), .I2(wb_mux[24]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_i_8_0), .O(a_mux[24])); LUT6 #( .INIT(64'hA8A8A8888888A888)) \wb_alu[28]_i_1 (.I0(\wb_alu[28]_i_2_n_0 ), .I1(\wb_alu[28]_i_3_n_0 ), .I2(\wb_alu_reg[29] ), .I3(\alu/data0 [28]), .I4(ALUSel[0]), .I5(\wb_alu[28]_i_4_n_0 ), .O(ex_alu[28])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[28]_i_10 (.I0(\wb_alu[28]_i_13_n_0 ), .I1(b_mux[2]), .I2(\wb_alu[28]_i_14_n_0 ), .I3(b_mux[1]), .I4(\wb_alu[28]_i_15_n_0 ), .O(\wb_alu[28]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[28]_i_11 (.I0(a_mux[13]), .I1(a_mux[14]), .I2(b_mux[1]), .I3(a_mux[15]), .I4(b_mux[0]), .I5(a_mux[16]), .O(\wb_alu[28]_i_11_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[28]_i_12 (.I0(a_mux[17]), .I1(a_mux[18]), .I2(b_mux[1]), .I3(a_mux[19]), .I4(b_mux[0]), .I5(a_mux[20]), .O(\wb_alu[28]_i_12_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[28]_i_13 (.I0(a_mux[21]), .I1(a_mux[22]), .I2(b_mux[1]), .I3(a_mux[23]), .I4(b_mux[0]), .I5(a_mux[24]), .O(\wb_alu[28]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT3 #( .INIT(8'hB8)) \wb_alu[28]_i_14 (.I0(a_mux[25]), .I1(b_mux[0]), .I2(a_mux[26]), .O(\wb_alu[28]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT3 #( .INIT(8'hB8)) \wb_alu[28]_i_15 (.I0(a_mux[27]), .I1(b_mux[0]), .I2(a_mux[28]), .O(\wb_alu[28]_i_15_n_0 )); LUT5 #( .INIT(32'hFFFF4445)) \wb_alu[28]_i_2 (.I0(\wb_alu[28]_i_5_n_0 ), .I1(\wb_alu_reg[22] ), .I2(mem_reg_0_0_i_127_n_0), .I3(\f_ex_imm_reg[16] [1]), .I4(\wb_alu_reg[28] ), .O(\wb_alu[28]_i_2_n_0 )); LUT5 #( .INIT(32'hFFABAAAA)) \wb_alu[28]_i_3 (.I0(ALUSel[3]), .I1(\wb_alu[28]_i_7_n_0 ), .I2(mem_reg_0_0_i_168_n_0), .I3(\wb_alu[28]_i_8_n_0 ), .I4(ALUSel[2]), .O(\wb_alu[28]_i_3_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[28]_i_4 (.I0(mem_reg_0_0_i_121_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(\wb_alu[28]_i_9_n_0 ), .I3(\f_ex_imm_reg[16] [0]), .I4(\wb_alu[28]_i_10_n_0 ), .O(\wb_alu[28]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT3 #( .INIT(8'h5D)) \wb_alu[28]_i_5 (.I0(\wb_alu_reg[16] ), .I1(ALUSel[1]), .I2(b_mux[28]), .O(\wb_alu[28]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'hEF)) \wb_alu[28]_i_7 (.I0(\f_ex_imm_reg[16] [0]), .I1(b_mux[2]), .I2(\wb_alu[0]_i_9_n_0 ), .O(\wb_alu[28]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT4 #( .INIT(16'hD414)) \wb_alu[28]_i_8 (.I0(ALUSel[0]), .I1(b_mux[28]), .I2(a_mux[28]), .I3(ALUSel[1]), .O(\wb_alu[28]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT3 #( .INIT(8'hB8)) \wb_alu[28]_i_9 (.I0(\wb_alu[28]_i_11_n_0 ), .I1(b_mux[2]), .I2(\wb_alu[28]_i_12_n_0 ), .O(\wb_alu[28]_i_9_n_0 )); LUT6 #( .INIT(64'hA8A8A8888888A888)) \wb_alu[29]_i_1 (.I0(\wb_alu[29]_i_2_n_0 ), .I1(\wb_alu[29]_i_3_n_0 ), .I2(\wb_alu_reg[29] ), .I3(\alu/data0 [29]), .I4(ALUSel[0]), .I5(\wb_alu[29]_i_6_n_0 ), .O(ex_alu[29])); LUT6 #( .INIT(64'hB8FF00B8004700B8)) \wb_alu[29]_i_10 (.I0(Q[29]), .I1(BSel), .I2(fwd_b[29]), .I3(ALUSel[0]), .I4(a_mux[29]), .I5(ALUSel[1]), .O(\wb_alu[29]_i_10_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[29]_i_12 (.I0(\wb_alu_reg[29]_i_5_0 [29]), .I1(ASel), .I2(wb_mux[29]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_6_1), .O(a_mux[29])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[29]_i_13 (.I0(\wb_alu_reg[29]_i_5_0 [28]), .I1(ASel), .I2(wb_mux[28]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrEq_i_6_0), .O(a_mux[28])); LUT2 #( .INIT(4'h6)) \wb_alu[29]_i_15 (.I0(a_mux[30]), .I1(b_mux[30]), .O(\wb_alu[29]_i_15_n_0 )); LUT4 #( .INIT(16'h47B8)) \wb_alu[29]_i_16 (.I0(Q[29]), .I1(BSel), .I2(fwd_b[29]), .I3(a_mux[29]), .O(\wb_alu[29]_i_16_n_0 )); LUT2 #( .INIT(4'h6)) \wb_alu[29]_i_17 (.I0(a_mux[28]), .I1(b_mux[28]), .O(\wb_alu[29]_i_17_n_0 )); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT3 #( .INIT(8'hB8)) \wb_alu[29]_i_18 (.I0(\wb_alu[29]_i_28_n_0 ), .I1(b_mux[2]), .I2(\wb_alu[29]_i_29_n_0 ), .O(\wb_alu[29]_i_18_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[29]_i_19 (.I0(\wb_alu[29]_i_30_n_0 ), .I1(b_mux[2]), .I2(\wb_alu[29]_i_31_n_0 ), .I3(b_mux[1]), .I4(\wb_alu[29]_i_32_n_0 ), .O(\wb_alu[29]_i_19_n_0 )); LUT5 #( .INIT(32'hFFFF4445)) \wb_alu[29]_i_2 (.I0(\wb_alu[29]_i_7_n_0 ), .I1(\wb_alu_reg[22] ), .I2(mem_reg_0_0_i_120_n_0), .I3(\f_ex_imm_reg[16] [1]), .I4(\wb_alu_reg[29]_0 ), .O(\wb_alu[29]_i_2_n_0 )); LUT2 #( .INIT(4'h6)) \wb_alu[29]_i_21 (.I0(a_mux[27]), .I1(b_mux[27]), .O(\wb_alu[29]_i_21_n_0 )); LUT2 #( .INIT(4'h6)) \wb_alu[29]_i_22 (.I0(a_mux[26]), .I1(b_mux[26]), .O(\wb_alu[29]_i_22_n_0 )); LUT2 #( .INIT(4'h6)) \wb_alu[29]_i_23 (.I0(a_mux[25]), .I1(b_mux[25]), .O(\wb_alu[29]_i_23_n_0 )); LUT2 #( .INIT(4'h6)) \wb_alu[29]_i_24 (.I0(a_mux[24]), .I1(b_mux[24]), .O(\wb_alu[29]_i_24_n_0 )); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT3 #( .INIT(8'hB8)) \wb_alu[29]_i_27 (.I0(Q[28]), .I1(BSel), .I2(fwd_b[28]), .O(b_mux[28])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[29]_i_28 (.I0(a_mux[14]), .I1(a_mux[15]), .I2(b_mux[1]), .I3(a_mux[16]), .I4(b_mux[0]), .I5(a_mux[17]), .O(\wb_alu[29]_i_28_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[29]_i_29 (.I0(a_mux[18]), .I1(a_mux[19]), .I2(b_mux[1]), .I3(a_mux[20]), .I4(b_mux[0]), .I5(a_mux[21]), .O(\wb_alu[29]_i_29_n_0 )); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT5 #( .INIT(32'hFFABAAAA)) \wb_alu[29]_i_3 (.I0(ALUSel[3]), .I1(\wb_alu[29]_i_9_n_0 ), .I2(mem_reg_0_0_i_168_n_0), .I3(\wb_alu[29]_i_10_n_0 ), .I4(ALUSel[2]), .O(\wb_alu[29]_i_3_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[29]_i_30 (.I0(a_mux[22]), .I1(a_mux[23]), .I2(b_mux[1]), .I3(a_mux[24]), .I4(b_mux[0]), .I5(a_mux[25]), .O(\wb_alu[29]_i_30_n_0 )); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT3 #( .INIT(8'hB8)) \wb_alu[29]_i_31 (.I0(a_mux[26]), .I1(b_mux[0]), .I2(a_mux[27]), .O(\wb_alu[29]_i_31_n_0 )); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT3 #( .INIT(8'hB8)) \wb_alu[29]_i_32 (.I0(a_mux[28]), .I1(b_mux[0]), .I2(a_mux[29]), .O(\wb_alu[29]_i_32_n_0 )); LUT2 #( .INIT(4'h6)) \wb_alu[29]_i_33 (.I0(a_mux[23]), .I1(b_mux[23]), .O(\wb_alu[29]_i_33_n_0 )); LUT2 #( .INIT(4'h6)) \wb_alu[29]_i_34 (.I0(a_mux[22]), .I1(b_mux[22]), .O(\wb_alu[29]_i_34_n_0 )); LUT2 #( .INIT(4'h6)) \wb_alu[29]_i_35 (.I0(a_mux[21]), .I1(b_mux[21]), .O(\wb_alu[29]_i_35_n_0 )); LUT2 #( .INIT(4'h6)) \wb_alu[29]_i_36 (.I0(a_mux[20]), .I1(b_mux[20]), .O(\wb_alu[29]_i_36_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[29]_i_6 (.I0(mem_reg_0_0_i_114_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(\wb_alu[29]_i_18_n_0 ), .I3(\f_ex_imm_reg[16] [0]), .I4(\wb_alu[29]_i_19_n_0 ), .O(\wb_alu[29]_i_6_n_0 )); LUT5 #( .INIT(32'h47FF00FF)) \wb_alu[29]_i_7 (.I0(Q[29]), .I1(BSel), .I2(fwd_b[29]), .I3(\wb_alu_reg[16] ), .I4(ALUSel[1]), .O(\wb_alu[29]_i_7_n_0 )); LUT6 #( .INIT(64'hFFEFEEEEFFEFFFFF)) \wb_alu[29]_i_9 (.I0(\f_ex_imm_reg[16] [0]), .I1(b_mux[2]), .I2(\wb_alu_reg[0]_i_18_1 ), .I3(b_mux[0]), .I4(b_mux[1]), .I5(mem_reg_0_0_i_269_n_0), .O(\wb_alu[29]_i_9_n_0 )); LUT6 #( .INIT(64'h88888888A8AAA8A8)) \wb_alu[2]_i_1 (.I0(mem_reg_0_0_i_85_n_0), .I1(mem_reg_0_0_i_86_n_0), .I2(mem_reg_0_0_i_87_n_0), .I3(mem_reg_0_0_i_88_n_0), .I4(ALUSel[0]), .I5(mem_reg_0_0_i_90_n_0), .O(ex_alu[2])); LUT6 #( .INIT(64'h8B88BBBB8B888B88)) \wb_alu[30]_i_1 (.I0(\wb_alu[30]_i_2_n_0 ), .I1(ALUSel[3]), .I2(\wb_alu[30]_i_3_n_0 ), .I3(\wb_alu[30]_i_4_n_0 ), .I4(\wb_alu[30]_i_5_n_0 ), .I5(ALUSel[2]), .O(ex_alu[30])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[30]_i_10 (.I0(a_mux[23]), .I1(a_mux[24]), .I2(b_mux[1]), .I3(a_mux[25]), .I4(b_mux[0]), .I5(a_mux[26]), .O(\wb_alu[30]_i_10_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEEEFFFEF)) \wb_alu[30]_i_11 (.I0(\f_ex_imm_reg[16] [0]), .I1(b_mux[2]), .I2(a_mux[30]), .I3(b_mux[0]), .I4(\wb_alu_reg[0]_i_18_1 ), .I5(b_mux[1]), .O(\wb_alu[30]_i_11_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[30]_i_12 (.I0(\wb_alu_reg[29]_i_5_0 [30]), .I1(ASel), .I2(wb_mux[30]), .I3(wb_BrLt_reg_i_2_0), .I4(wb_BrLt_reg_i_2_1), .O(a_mux[30])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[30]_i_13 (.I0(a_mux[15]), .I1(a_mux[16]), .I2(b_mux[1]), .I3(a_mux[17]), .I4(b_mux[0]), .I5(a_mux[18]), .O(\wb_alu[30]_i_13_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[30]_i_14 (.I0(a_mux[19]), .I1(a_mux[20]), .I2(b_mux[1]), .I3(a_mux[21]), .I4(b_mux[0]), .I5(a_mux[22]), .O(\wb_alu[30]_i_14_n_0 )); LUT6 #( .INIT(64'h8000C00F8000C000)) \wb_alu[30]_i_2 (.I0(b_mux[30]), .I1(\wb_alu[30]_i_7_n_0 ), .I2(ALUSel[0]), .I3(ALUSel[2]), .I4(ALUSel[1]), .I5(\alu/data8 [30]), .O(\wb_alu[30]_i_2_n_0 )); LUT6 #( .INIT(64'hFFF1FFFFFFF1FFF1)) \wb_alu[30]_i_3 (.I0(ALUSel[0]), .I1(\f_ex_pc_reg[30] [6]), .I2(ALUSel[1]), .I3(ALUSel[2]), .I4(mem_reg_0_0_i_107_n_0), .I5(\wb_alu[0]_i_3_n_0 ), .O(\wb_alu[30]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFAAAAFC0C)) \wb_alu[30]_i_4 (.I0(\wb_alu[30]_i_8_n_0 ), .I1(\wb_alu[30]_i_9_n_0 ), .I2(b_mux[2]), .I3(\wb_alu[30]_i_10_n_0 ), .I4(\f_ex_imm_reg[16] [0]), .I5(\wb_alu[31]_i_9_n_0 ), .O(\wb_alu[30]_i_4_n_0 )); LUT6 #( .INIT(64'h0EEEEEEE0E0000EE)) \wb_alu[30]_i_5 (.I0(mem_reg_0_0_i_168_n_0), .I1(\wb_alu[30]_i_11_n_0 ), .I2(ALUSel[1]), .I3(a_mux[30]), .I4(b_mux[30]), .I5(ALUSel[0]), .O(\wb_alu[30]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[30]_i_6 (.I0(Q[30]), .I1(BSel), .I2(wb_mux[30]), .I3(mem_reg_1_0), .I4(mem_reg_3_3_0), .O(b_mux[30])); LUT3 #( .INIT(8'hF1)) \wb_alu[30]_i_7 (.I0(mem_reg_0_0_i_113_n_0), .I1(\f_ex_imm_reg[16] [1]), .I2(\wb_alu_reg[22] ), .O(\wb_alu[30]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT3 #( .INIT(8'hB8)) \wb_alu[30]_i_8 (.I0(\wb_alu[30]_i_13_n_0 ), .I1(b_mux[2]), .I2(\wb_alu[30]_i_14_n_0 ), .O(\wb_alu[30]_i_8_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[30]_i_9 (.I0(a_mux[27]), .I1(a_mux[28]), .I2(b_mux[1]), .I3(a_mux[29]), .I4(b_mux[0]), .I5(a_mux[30]), .O(\wb_alu[30]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT3 #( .INIT(8'hB8)) \wb_alu[31]_i_10 (.I0(\wb_alu[31]_i_19_n_0 ), .I1(b_mux[2]), .I2(\wb_alu[31]_i_20_n_0 ), .O(\wb_alu[31]_i_10_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[31]_i_11 (.I0(a_mux[28]), .I1(a_mux[29]), .I2(b_mux[1]), .I3(a_mux[30]), .I4(b_mux[0]), .I5(\wb_alu_reg[0]_i_18_1 ), .O(\wb_alu[31]_i_11_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[31]_i_12 (.I0(a_mux[24]), .I1(a_mux[25]), .I2(b_mux[1]), .I3(a_mux[26]), .I4(b_mux[0]), .I5(a_mux[27]), .O(\wb_alu[31]_i_12_n_0 )); LUT6 #( .INIT(64'h0000000000000010)) \wb_alu[31]_i_13 (.I0(\wb_alu[31]_i_9_n_0 ), .I1(b_mux[0]), .I2(\wb_alu_reg[0]_i_18_1 ), .I3(b_mux[1]), .I4(b_mux[2]), .I5(\f_ex_imm_reg[16] [0]), .O(\f_ex_imm_reg[4] )); LUT2 #( .INIT(4'h9)) \wb_alu[31]_i_16 (.I0(b_mux[30]), .I1(a_mux[30]), .O(\wb_alu[31]_i_16_n_0 )); LUT4 #( .INIT(16'hB847)) \wb_alu[31]_i_17 (.I0(Q[29]), .I1(BSel), .I2(fwd_b[29]), .I3(a_mux[29]), .O(\wb_alu[31]_i_17_n_0 )); LUT2 #( .INIT(4'h9)) \wb_alu[31]_i_18 (.I0(a_mux[28]), .I1(b_mux[28]), .O(\wb_alu[31]_i_18_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[31]_i_19 (.I0(a_mux[16]), .I1(a_mux[17]), .I2(b_mux[1]), .I3(a_mux[18]), .I4(b_mux[0]), .I5(a_mux[19]), .O(\wb_alu[31]_i_19_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \wb_alu[31]_i_20 (.I0(a_mux[20]), .I1(a_mux[21]), .I2(b_mux[1]), .I3(a_mux[22]), .I4(b_mux[0]), .I5(a_mux[23]), .O(\wb_alu[31]_i_20_n_0 )); LUT6 #( .INIT(64'hFFF1FFFFFFF1FFF1)) \wb_alu[31]_i_3 (.I0(ALUSel[0]), .I1(\f_ex_pc_reg[30] [7]), .I2(ALUSel[1]), .I3(ALUSel[2]), .I4(mem_reg_0_0_i_95_n_0), .I5(\wb_alu[0]_i_3_n_0 ), .O(\f_ex_inst_reg[12] )); LUT6 #( .INIT(64'hFBFBFBEAEAEAFBEA)) \wb_alu[31]_i_4 (.I0(\wb_alu[31]_i_9_n_0 ), .I1(\f_ex_imm_reg[16] [0]), .I2(\wb_alu[31]_i_10_n_0 ), .I3(\wb_alu[31]_i_11_n_0 ), .I4(b_mux[2]), .I5(\wb_alu[31]_i_12_n_0 ), .O(\f_ex_imm_reg[4]_0 )); LUT4 #( .INIT(16'hE2FF)) \wb_alu[31]_i_9 (.I0(fwd_b[4]), .I1(BSel), .I2(Q[4]), .I3(ALUSel[0]), .O(\wb_alu[31]_i_9_n_0 )); LUT6 #( .INIT(64'h0E00EEEEEEEEEEEE)) \wb_alu[3]_i_1 (.I0(mem_reg_0_0_i_81_n_0), .I1(mem_reg_0_0_i_82_n_0), .I2(douta_reg_0_2), .I3(\alu/data8 [3]), .I4(ALUSel[3]), .I5(mem_reg_0_0_i_84_n_0), .O(ex_alu[3])); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \wb_alu_reg[0]_i_17 (.CI(\wb_alu_reg[0]_i_19_n_0 ), .CO({\alu/data3 ,\wb_alu_reg[0]_i_17_n_1 ,\wb_alu_reg[0]_i_17_n_2 ,\wb_alu_reg[0]_i_17_n_3 }), .CYINIT(\<const0> ), .DI({\wb_alu[0]_i_20_n_0 ,\wb_alu[0]_i_21_n_0 ,\wb_alu[0]_i_22_n_0 ,\wb_alu[0]_i_23_n_0 }), .S({\wb_alu[0]_i_24_n_0 ,\wb_alu[0]_i_25_n_0 ,\wb_alu[0]_i_26_n_0 ,\wb_alu[0]_i_27_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \wb_alu_reg[0]_i_18 (.CI(\wb_alu_reg[0]_i_28_n_0 ), .CO({\alu/data2 ,\wb_alu_reg[0]_i_18_n_1 ,\wb_alu_reg[0]_i_18_n_2 ,\wb_alu_reg[0]_i_18_n_3 }), .CYINIT(\<const0> ), .DI({\wb_alu[0]_i_29_n_0 ,\wb_alu[0]_i_30_n_0 ,\wb_alu[0]_i_31_n_0 ,\wb_alu[0]_i_32_n_0 }), .S({\wb_alu[0]_i_33_n_0 ,\wb_alu[0]_i_34_n_0 ,\wb_alu[0]_i_35_n_0 ,\wb_alu[0]_i_36_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \wb_alu_reg[0]_i_19 (.CI(\wb_alu_reg[0]_i_37_n_0 ), .CO({\wb_alu_reg[0]_i_19_n_0 ,\wb_alu_reg[0]_i_19_n_1 ,\wb_alu_reg[0]_i_19_n_2 ,\wb_alu_reg[0]_i_19_n_3 }), .CYINIT(\<const0> ), .DI({\wb_alu[0]_i_38_n_0 ,\wb_alu[0]_i_39_n_0 ,\wb_alu[0]_i_40_n_0 ,\wb_alu[0]_i_41_n_0 }), .S({\wb_alu[0]_i_42_n_0 ,\wb_alu[0]_i_43_n_0 ,\wb_alu[0]_i_44_n_0 ,\wb_alu[0]_i_45_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \wb_alu_reg[0]_i_28 (.CI(\wb_alu_reg[0]_i_46_n_0 ), .CO({\wb_alu_reg[0]_i_28_n_0 ,\wb_alu_reg[0]_i_28_n_1 ,\wb_alu_reg[0]_i_28_n_2 ,\wb_alu_reg[0]_i_28_n_3 }), .CYINIT(\<const0> ), .DI({\wb_alu[0]_i_38_n_0 ,\wb_alu[0]_i_39_n_0 ,\wb_alu[0]_i_40_n_0 ,\wb_alu[0]_i_41_n_0 }), .S({\wb_alu[0]_i_47_n_0 ,\wb_alu[0]_i_48_n_0 ,\wb_alu[0]_i_49_n_0 ,\wb_alu[0]_i_50_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \wb_alu_reg[0]_i_37 (.CI(\wb_alu_reg[0]_i_51_n_0 ), .CO({\wb_alu_reg[0]_i_37_n_0 ,\wb_alu_reg[0]_i_37_n_1 ,\wb_alu_reg[0]_i_37_n_2 ,\wb_alu_reg[0]_i_37_n_3 }), .CYINIT(\<const0> ), .DI({\wb_alu[0]_i_52_n_0 ,\wb_alu[0]_i_53_n_0 ,\wb_alu[0]_i_54_n_0 ,\wb_alu[0]_i_55_n_0 }), .S({\wb_alu[0]_i_56_n_0 ,\wb_alu[0]_i_57_n_0 ,\wb_alu[0]_i_58_n_0 ,\wb_alu[0]_i_59_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \wb_alu_reg[0]_i_46 (.CI(\wb_alu_reg[0]_i_60_n_0 ), .CO({\wb_alu_reg[0]_i_46_n_0 ,\wb_alu_reg[0]_i_46_n_1 ,\wb_alu_reg[0]_i_46_n_2 ,\wb_alu_reg[0]_i_46_n_3 }), .CYINIT(\<const0> ), .DI({\wb_alu[0]_i_52_n_0 ,\wb_alu[0]_i_53_n_0 ,\wb_alu[0]_i_54_n_0 ,\wb_alu[0]_i_55_n_0 }), .S({\wb_alu[0]_i_61_n_0 ,\wb_alu[0]_i_62_n_0 ,\wb_alu[0]_i_63_n_0 ,\wb_alu[0]_i_64_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \wb_alu_reg[0]_i_51 (.CI(\<const0> ), .CO({\wb_alu_reg[0]_i_51_n_0 ,\wb_alu_reg[0]_i_51_n_1 ,\wb_alu_reg[0]_i_51_n_2 ,\wb_alu_reg[0]_i_51_n_3 }), .CYINIT(\<const0> ), .DI({\wb_alu[0]_i_65_n_0 ,\wb_alu[0]_i_66_n_0 ,\wb_alu[0]_i_67_n_0 ,\wb_alu[0]_i_68_n_0 }), .S({\wb_alu[0]_i_69_n_0 ,\wb_alu[0]_i_70_n_0 ,\wb_alu[0]_i_71_n_0 ,\wb_alu[0]_i_72_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \wb_alu_reg[0]_i_60 (.CI(\<const0> ), .CO({\wb_alu_reg[0]_i_60_n_0 ,\wb_alu_reg[0]_i_60_n_1 ,\wb_alu_reg[0]_i_60_n_2 ,\wb_alu_reg[0]_i_60_n_3 }), .CYINIT(\<const0> ), .DI({\wb_alu[0]_i_73_n_0 ,\wb_alu[0]_i_74_n_0 ,\wb_alu[0]_i_75_n_0 ,\wb_alu[0]_i_76_n_0 }), .S({\wb_alu[0]_i_77_n_0 ,\wb_alu[0]_i_78_n_0 ,\wb_alu[0]_i_79_n_0 ,\wb_alu[0]_i_80_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY4 \wb_alu_reg[19]_i_24 (.CI(mem_reg_0_0_i_96_n_0), .CO({\wb_alu_reg[19]_i_24_n_0 ,\wb_alu_reg[19]_i_24_n_1 ,\wb_alu_reg[19]_i_24_n_2 ,\wb_alu_reg[19]_i_24_n_3 }), .CYINIT(\<const0> ), .DI(a_mux[19:16]), .O(\alu/data0 [19:16]), .S({\wb_alu[19]_i_25_n_0 ,\wb_alu[19]_i_26_n_0 ,\wb_alu[19]_i_27_n_0 ,\wb_alu[19]_i_28_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY4 \wb_alu_reg[19]_i_3 (.CI(mem_reg_0_0_i_104_n_0), .CO({\wb_alu_reg[19]_i_3_n_0 ,\wb_alu_reg[19]_i_3_n_1 ,\wb_alu_reg[19]_i_3_n_2 ,\wb_alu_reg[19]_i_3_n_3 }), .CYINIT(\<const0> ), .DI(a_mux[19:16]), .O(\alu/data8 [19:16]), .S({\wb_alu[19]_i_11_n_0 ,\wb_alu[19]_i_12_n_0 ,\wb_alu[19]_i_13_n_0 ,\wb_alu[19]_i_14_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY4 \wb_alu_reg[23]_i_3 (.CI(\wb_alu_reg[19]_i_3_n_0 ), .CO({\wb_alu_reg[23]_i_3_n_0 ,\wb_alu_reg[23]_i_3_n_1 ,\wb_alu_reg[23]_i_3_n_2 ,\wb_alu_reg[23]_i_3_n_3 }), .CYINIT(\<const0> ), .DI(a_mux[23:20]), .O(\alu/data8 [23:20]), .S({\wb_alu[23]_i_11_n_0 ,\wb_alu[23]_i_12_n_0 ,\wb_alu[23]_i_13_n_0 ,\wb_alu[23]_i_14_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY4 \wb_alu_reg[27]_i_2 (.CI(\wb_alu_reg[23]_i_3_n_0 ), .CO({\wb_alu_reg[27]_i_2_n_0 ,\wb_alu_reg[27]_i_2_n_1 ,\wb_alu_reg[27]_i_2_n_2 ,\wb_alu_reg[27]_i_2_n_3 }), .CYINIT(\<const0> ), .DI(a_mux[27:24]), .O(\f_ex_pc_reg[30]_0 [14:11]), .S({\wb_alu[27]_i_10_n_0 ,\wb_alu[27]_i_11_n_0 ,\wb_alu[27]_i_12_n_0 ,\wb_alu[27]_i_13_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY4 \wb_alu_reg[29]_i_11 (.CI(\wb_alu_reg[29]_i_20_n_0 ), .CO({\wb_alu_reg[29]_i_11_n_0 ,\wb_alu_reg[29]_i_11_n_1 ,\wb_alu_reg[29]_i_11_n_2 ,\wb_alu_reg[29]_i_11_n_3 }), .CYINIT(\<const0> ), .DI(a_mux[27:24]), .O(\alu/data0 [27:24]), .S({\wb_alu[29]_i_21_n_0 ,\wb_alu[29]_i_22_n_0 ,\wb_alu[29]_i_23_n_0 ,\wb_alu[29]_i_24_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY4 \wb_alu_reg[29]_i_20 (.CI(\wb_alu_reg[19]_i_24_n_0 ), .CO({\wb_alu_reg[29]_i_20_n_0 ,\wb_alu_reg[29]_i_20_n_1 ,\wb_alu_reg[29]_i_20_n_2 ,\wb_alu_reg[29]_i_20_n_3 }), .CYINIT(\<const0> ), .DI(a_mux[23:20]), .O(\f_ex_pc_reg[30] [5:2]), .S({\wb_alu[29]_i_33_n_0 ,\wb_alu[29]_i_34_n_0 ,\wb_alu[29]_i_35_n_0 ,\wb_alu[29]_i_36_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY4 \wb_alu_reg[29]_i_5 (.CI(\wb_alu_reg[29]_i_11_n_0 ), .CO({\wb_alu_reg[29]_i_5_n_1 ,\wb_alu_reg[29]_i_5_n_2 ,\wb_alu_reg[29]_i_5_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,a_mux[30:28]}), .O({\f_ex_pc_reg[30] [7:6],\alu/data0 [29:28]}), .S({S,\wb_alu[29]_i_15_n_0 ,\wb_alu[29]_i_16_n_0 ,\wb_alu[29]_i_17_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY4 \wb_alu_reg[31]_i_8 (.CI(\wb_alu_reg[27]_i_2_n_0 ), .CO({\wb_alu_reg[31]_i_8_n_1 ,\wb_alu_reg[31]_i_8_n_2 ,\wb_alu_reg[31]_i_8_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,a_mux[30:28]}), .O({\f_ex_pc_reg[30]_0 [17],\alu/data8 [30],\f_ex_pc_reg[30]_0 [16:15]}), .S({\wb_alu[28]_i_6 ,\wb_alu[31]_i_16_n_0 ,\wb_alu[31]_i_17_n_0 ,\wb_alu[31]_i_18_n_0 })); endmodule module bp_cache (D, douta_reg_1, \ex_wb_inst_reg[6] , douta_reg_1_0, douta_reg_1_1, \wb_alu_reg[31] , \wb_alu_reg[31]_0 , \wb_alu_reg[31]_1 , \f_ex_pc_reg[4] , SR, douta_reg_1_2, br_inst_cnt, cpu_clk_locked, buttons_pressed, rd10, rd20, SWITCHES_IBUF, br, wb_br_taken, data2, \f_ex_rd2_reg[0] , wb_br_taken_reg, Q, i__carry__1_i_1__0_0, \f_ex_imm_reg[30] , \pc_reg[31] , \pc_reg[0] , cpu_reset, \pc_reg[31]_0 , O, data3, mem_reg_0_0, mem_reg_0_0_0, mem_reg_3_3, \pc_reg[19] , \pc_reg[23] , \pc_reg[27] , \br_inst_cnt_reg[0] , doutb, out, \pc_reg[31]_1 , \f_ex_rd2_reg[0]_0 , cpu_clk); output [30:0]D; output [30:0]douta_reg_1; output \ex_wb_inst_reg[6] ; output [31:0]douta_reg_1_0; output [31:0]douta_reg_1_1; output \wb_alu_reg[31] ; output [31:0]\wb_alu_reg[31]_0 ; output \wb_alu_reg[31]_1 ; output \f_ex_pc_reg[4] ; output [0:0]SR; output douta_reg_1_2; output br_inst_cnt; input cpu_clk_locked; input buttons_pressed; input [31:0]rd10; input [31:0]rd20; input [0:0]SWITCHES_IBUF; input br; input wb_br_taken; input [30:0]data2; input \f_ex_rd2_reg[0] ; input wb_br_taken_reg; input [29:0]Q; input [30:0]i__carry__1_i_1__0_0; input \f_ex_imm_reg[30] ; input [31:0]\pc_reg[31] ; input [0:0]\pc_reg[0] ; input cpu_reset; input \pc_reg[31]_0 ; input [3:0]O; input [30:0]data3; input [3:0]mem_reg_0_0; input [3:0]mem_reg_0_0_0; input [3:0]mem_reg_3_3; input [3:0]\pc_reg[19] ; input [3:0]\pc_reg[23] ; input [3:0]\pc_reg[27] ; input \br_inst_cnt_reg[0] ; input [31:0]doutb; input [31:0]out; input [3:0]\pc_reg[31]_1 ; input [6:0]\f_ex_rd2_reg[0]_0 ; input cpu_clk; wire \<const0> ; wire \<const1> ; wire [30:0]D; wire GND_2; wire [3:0]O; wire [29:0]Q; wire [0:0]SR; wire [0:0]SWITCHES_IBUF; wire br; wire br_inst_cnt; wire \br_inst_cnt_reg[0] ; wire buttons_pressed; wire cache_hit_check; wire [1:0]cache_out_check; wire [1:1]cache_out_guess; wire cpu_clk; wire cpu_clk_locked; wire cpu_reset; wire [30:0]data2; wire [30:0]data3; wire data_reg_0_7_0_0_i_1_n_0; wire data_reg_0_7_0_0_i_2_n_0; wire data_reg_0_7_0_0_i_6_n_0; wire data_reg_0_7_0_0_i_7_n_0; wire data_reg_0_7_0_0_i_8_n_0; wire data_reg_0_7_0_0_n_0; wire data_reg_0_7_1_1_i_1_n_0; wire [30:0]douta_reg_1; wire [31:0]douta_reg_1_0; wire [31:0]douta_reg_1_1; wire douta_reg_1_2; wire [31:0]doutb; wire \ex_wb_inst_reg[6] ; wire \f_ex_imm[30]_i_3_n_0 ; wire \f_ex_imm_reg[30] ; wire \f_ex_pc_reg[4] ; wire \f_ex_rd2_reg[0] ; wire [6:0]\f_ex_rd2_reg[0]_0 ; wire hit00; wire \hit00_inferred__0/i__carry__0_n_0 ; wire \hit00_inferred__0/i__carry__0_n_1 ; wire \hit00_inferred__0/i__carry__0_n_2 ; wire \hit00_inferred__0/i__carry__0_n_3 ; wire \hit00_inferred__0/i__carry_n_0 ; wire \hit00_inferred__0/i__carry_n_1 ; wire \hit00_inferred__0/i__carry_n_2 ; wire \hit00_inferred__0/i__carry_n_3 ; wire [26:0]hit01; wire hit10; wire \hit10_inferred__0/i__carry__0_n_0 ; wire \hit10_inferred__0/i__carry__0_n_1 ; wire \hit10_inferred__0/i__carry__0_n_2 ; wire \hit10_inferred__0/i__carry__0_n_3 ; wire \hit10_inferred__0/i__carry_n_0 ; wire \hit10_inferred__0/i__carry_n_1 ; wire \hit10_inferred__0/i__carry_n_2 ; wire \hit10_inferred__0/i__carry_n_3 ; wire [26:0]hit11; wire i__carry__0_i_1__0_n_0; wire i__carry__0_i_1_n_0; wire i__carry__0_i_2__0_n_0; wire i__carry__0_i_2_n_0; wire i__carry__0_i_3__0_n_0; wire i__carry__0_i_3_n_0; wire i__carry__0_i_4__0_n_0; wire i__carry__0_i_4_n_0; wire [30:0]i__carry__1_i_1__0_0; wire i__carry__1_i_1__0_n_0; wire i__carry__1_i_1_n_0; wire i__carry_i_1__0_n_0; wire i__carry_i_1_n_0; wire i__carry_i_2__0_n_0; wire i__carry_i_2_n_0; wire i__carry_i_3__0_n_0; wire i__carry_i_3_n_0; wire i__carry_i_4__0_n_0; wire i__carry_i_4_n_0; wire [2:0]\imm_gen/ImmSel ; wire [7:0]is_valid; wire \is_valid[0]_i_1_n_0 ; wire \is_valid[1]_i_1_n_0 ; wire \is_valid[2]_i_1_n_0 ; wire \is_valid[3]_i_1_n_0 ; wire \is_valid[4]_i_1_n_0 ; wire \is_valid[5]_i_1_n_0 ; wire \is_valid[6]_i_1_n_0 ; wire \is_valid[7]_i_1_n_0 ; wire [3:0]mem_reg_0_0; wire [3:0]mem_reg_0_0_0; wire mem_reg_0_0_i_21__0_n_0; wire mem_reg_0_0_i_22__0_n_0; wire mem_reg_0_0_i_24__0_n_0; wire mem_reg_0_0_i_25_n_0; wire mem_reg_0_0_i_27__0_n_0; wire mem_reg_0_0_i_28__0_n_0; wire mem_reg_0_0_i_29__0_n_0; wire mem_reg_0_0_i_30__0_n_0; wire mem_reg_0_0_i_32_n_0; wire mem_reg_0_0_i_33__0_n_0; wire mem_reg_0_0_i_34__0_n_0; wire mem_reg_0_0_i_35__0_n_0; wire mem_reg_0_0_i_37_n_0; wire mem_reg_0_0_i_38_n_0; wire mem_reg_0_0_i_39__0_n_0; wire mem_reg_0_0_i_41__0_n_0; wire [3:0]mem_reg_3_3; wire [31:0]out; wire \pc[0]_i_2_n_0 ; wire \pc[16]_i_2_n_0 ; wire \pc[17]_i_2_n_0 ; wire \pc[18]_i_2_n_0 ; wire \pc[19]_i_2_n_0 ; wire \pc[1]_i_2_n_0 ; wire \pc[20]_i_3_n_0 ; wire \pc[21]_i_2_n_0 ; wire \pc[22]_i_2_n_0 ; wire \pc[23]_i_2_n_0 ; wire \pc[24]_i_3_n_0 ; wire \pc[25]_i_2_n_0 ; wire \pc[26]_i_2_n_0 ; wire \pc[27]_i_2_n_0 ; wire \pc[28]_i_3_n_0 ; wire \pc[29]_i_2_n_0 ; wire \pc[30]_i_2_n_0 ; wire \pc[30]_i_3_n_0 ; wire \pc[30]_i_4_n_0 ; wire \pc[31]_i_3_n_0 ; wire [0:0]\pc_reg[0] ; wire [3:0]\pc_reg[19] ; wire [3:0]\pc_reg[23] ; wire [3:0]\pc_reg[27] ; wire [31:0]\pc_reg[31] ; wire \pc_reg[31]_0 ; wire [3:0]\pc_reg[31]_1 ; wire [31:0]rd10; wire [31:0]rd20; wire \wb_alu_reg[31] ; wire [31:0]\wb_alu_reg[31]_0 ; wire \wb_alu_reg[31]_1 ; wire wb_br_taken; wire wb_br_taken_i_5_n_0; wire wb_br_taken_i_6_n_0; wire wb_br_taken_reg; GND GND (.G(\<const0> )); GND GND_1 (.G(GND_2)); VCC VCC (.P(\<const1> )); LUT6 #( .INIT(64'h0000040000000000)) \br_inst_cnt[0]_i_1 (.I0(douta_reg_1[2]), .I1(\br_inst_cnt_reg[0] ), .I2(douta_reg_1[3]), .I3(douta_reg_1[0]), .I4(douta_reg_1[4]), .I5(douta_reg_1[6]), .O(br_inst_cnt)); (* RTL_RAM_BITS = "16" *) (* RTL_RAM_NAME = "cache/data" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "0" *) RAM32X1D #( .INIT(32'h00000000)) data_reg_0_7_0_0 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(data_reg_0_7_0_0_i_1_n_0), .DPO(data_reg_0_7_0_0_n_0), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(cache_out_check[0]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); LUT4 #( .INIT(16'hB02F)) data_reg_0_7_0_0_i_1 (.I0(cache_out_check[1]), .I1(cache_out_check[0]), .I2(cache_hit_check), .I3(br), .O(data_reg_0_7_0_0_i_1_n_0)); LUT3 #( .INIT(8'h04)) data_reg_0_7_0_0_i_2 (.I0(\ex_wb_inst_reg[6] ), .I1(cpu_clk_locked), .I2(buttons_pressed), .O(data_reg_0_7_0_0_i_2_n_0)); LUT4 #( .INIT(16'hA808)) data_reg_0_7_0_0_i_3 (.I0(hit10), .I1(data_reg_0_7_0_0_i_6_n_0), .I2(i__carry__1_i_1__0_0[3]), .I3(data_reg_0_7_0_0_i_7_n_0), .O(cache_hit_check)); LUT6 #( .INIT(64'hFFFFFFFFDFFFFFFF)) data_reg_0_7_0_0_i_5 (.I0(\f_ex_rd2_reg[0]_0 [6]), .I1(\f_ex_rd2_reg[0]_0 [4]), .I2(\f_ex_rd2_reg[0]_0 [5]), .I3(\f_ex_rd2_reg[0]_0 [1]), .I4(\f_ex_rd2_reg[0]_0 [0]), .I5(data_reg_0_7_0_0_i_8_n_0), .O(\ex_wb_inst_reg[6] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) data_reg_0_7_0_0_i_6 (.I0(is_valid[3]), .I1(is_valid[2]), .I2(i__carry__1_i_1__0_0[2]), .I3(is_valid[1]), .I4(i__carry__1_i_1__0_0[1]), .I5(is_valid[0]), .O(data_reg_0_7_0_0_i_6_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) data_reg_0_7_0_0_i_7 (.I0(is_valid[7]), .I1(is_valid[6]), .I2(i__carry__1_i_1__0_0[2]), .I3(is_valid[5]), .I4(i__carry__1_i_1__0_0[1]), .I5(is_valid[4]), .O(data_reg_0_7_0_0_i_7_n_0)); LUT2 #( .INIT(4'hE)) data_reg_0_7_0_0_i_8 (.I0(\f_ex_rd2_reg[0]_0 [2]), .I1(\f_ex_rd2_reg[0]_0 [3]), .O(data_reg_0_7_0_0_i_8_n_0)); (* RTL_RAM_BITS = "16" *) (* RTL_RAM_NAME = "cache/data" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "1" *) (* ram_slice_end = "1" *) RAM32X1D #( .INIT(32'h00000000)) data_reg_0_7_1_1 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(data_reg_0_7_1_1_i_1_n_0), .DPO(cache_out_guess), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(cache_out_check[1]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); LUT4 #( .INIT(16'hEF80)) data_reg_0_7_1_1_i_1 (.I0(cache_out_check[1]), .I1(cache_out_check[0]), .I2(cache_hit_check), .I3(br), .O(data_reg_0_7_1_1_i_1_n_0)); LUT5 #( .INIT(32'h00004540)) \f_ex_imm[0]_i_1 (.I0(\imm_gen/ImmSel [1]), .I1(douta_reg_1[7]), .I2(\imm_gen/ImmSel [0]), .I3(douta_reg_1[20]), .I4(\imm_gen/ImmSel [2]), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT4 #( .INIT(16'hBF00)) \f_ex_imm[10]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(\imm_gen/ImmSel [0]), .I2(\imm_gen/ImmSel [1]), .I3(douta_reg_1[30]), .O(D[10])); LUT6 #( .INIT(64'h88B8BBBB88B88888)) \f_ex_imm[11]_i_1 (.I0(douta_reg_1[20]), .I1(\imm_gen/ImmSel [2]), .I2(douta_reg_1[7]), .I3(\imm_gen/ImmSel [0]), .I4(\imm_gen/ImmSel [1]), .I5(douta_reg_1_2), .O(D[11])); LUT5 #( .INIT(32'hCDDDC888)) \f_ex_imm[12]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[12]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[12])); LUT5 #( .INIT(32'hCDDDC888)) \f_ex_imm[13]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[13]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[13])); LUT5 #( .INIT(32'hCDDDC888)) \f_ex_imm[14]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[14]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[14])); LUT5 #( .INIT(32'hCDDDC888)) \f_ex_imm[15]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[15]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[15])); LUT5 #( .INIT(32'hCDDDC888)) \f_ex_imm[16]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[16]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[16])); LUT5 #( .INIT(32'hCDDDC888)) \f_ex_imm[17]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[17]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[17])); LUT5 #( .INIT(32'hCDDDC888)) \f_ex_imm[18]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[18]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[18])); LUT5 #( .INIT(32'hCDDDC888)) \f_ex_imm[19]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[19]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[19])); LUT5 #( .INIT(32'hBAFB1040)) \f_ex_imm[1]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(\imm_gen/ImmSel [1]), .I2(douta_reg_1[8]), .I3(\imm_gen/ImmSel [0]), .I4(douta_reg_1[21]), .O(D[1])); LUT5 #( .INIT(32'hEFFF4000)) \f_ex_imm[20]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[20]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[20])); LUT5 #( .INIT(32'hEFFF4000)) \f_ex_imm[21]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[21]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[21])); LUT5 #( .INIT(32'hEFFF4000)) \f_ex_imm[22]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[22]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[22])); LUT5 #( .INIT(32'hEFFF4000)) \f_ex_imm[23]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[23]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[23])); LUT5 #( .INIT(32'hEFFF4000)) \f_ex_imm[24]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[24]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[24])); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT5 #( .INIT(32'hEFFF4000)) \f_ex_imm[25]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[25]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[25])); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT5 #( .INIT(32'hEFFF4000)) \f_ex_imm[26]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[26]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[26])); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT5 #( .INIT(32'hEFFF4000)) \f_ex_imm[27]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[27]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[27])); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT5 #( .INIT(32'hEFFF4000)) \f_ex_imm[28]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[28]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[28])); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT5 #( .INIT(32'hEFFF4000)) \f_ex_imm[29]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[29]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[29])); LUT5 #( .INIT(32'hBAFB1040)) \f_ex_imm[2]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(\imm_gen/ImmSel [1]), .I2(douta_reg_1[9]), .I3(\imm_gen/ImmSel [0]), .I4(douta_reg_1[22]), .O(D[2])); LUT6 #( .INIT(64'hFFFF1F40FFFFFFFF)) \f_ex_imm[30]_i_1 (.I0(\ex_wb_inst_reg[6] ), .I1(wb_br_taken), .I2(SWITCHES_IBUF), .I3(br), .I4(\f_ex_rd2_reg[0] ), .I5(\f_ex_imm[30]_i_3_n_0 ), .O(SR)); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT5 #( .INIT(32'hEFFF4000)) \f_ex_imm[30]_i_2 (.I0(\imm_gen/ImmSel [2]), .I1(douta_reg_1[30]), .I2(\imm_gen/ImmSel [0]), .I3(\imm_gen/ImmSel [1]), .I4(douta_reg_1_2), .O(D[30])); LUT2 #( .INIT(4'h7)) \f_ex_imm[30]_i_3 (.I0(SWITCHES_IBUF), .I1(\f_ex_pc_reg[4] ), .O(\f_ex_imm[30]_i_3_n_0 )); LUT4 #( .INIT(16'h0040)) \f_ex_imm[30]_i_4 (.I0(douta_reg_1[4]), .I1(douta_reg_1[3]), .I2(douta_reg_1[2]), .I3(\f_ex_imm_reg[30] ), .O(\imm_gen/ImmSel [2])); LUT5 #( .INIT(32'h10100100)) \f_ex_imm[30]_i_5 (.I0(douta_reg_1[6]), .I1(douta_reg_1[3]), .I2(douta_reg_1[4]), .I3(douta_reg_1[5]), .I4(douta_reg_1[2]), .O(\imm_gen/ImmSel [0])); LUT5 #( .INIT(32'h01200020)) \f_ex_imm[30]_i_6 (.I0(douta_reg_1[2]), .I1(douta_reg_1[3]), .I2(douta_reg_1[4]), .I3(douta_reg_1[6]), .I4(douta_reg_1[5]), .O(\imm_gen/ImmSel [1])); LUT4 #( .INIT(16'h4F44)) \f_ex_imm[31]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[31]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[31]), .O(douta_reg_1_2)); LUT5 #( .INIT(32'hBAFB1040)) \f_ex_imm[3]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(\imm_gen/ImmSel [1]), .I2(douta_reg_1[10]), .I3(\imm_gen/ImmSel [0]), .I4(douta_reg_1[23]), .O(D[3])); LUT5 #( .INIT(32'hBAFB1040)) \f_ex_imm[4]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(\imm_gen/ImmSel [1]), .I2(douta_reg_1[11]), .I3(\imm_gen/ImmSel [0]), .I4(douta_reg_1[24]), .O(D[4])); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT4 #( .INIT(16'hBF00)) \f_ex_imm[5]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(\imm_gen/ImmSel [0]), .I2(\imm_gen/ImmSel [1]), .I3(douta_reg_1[25]), .O(D[5])); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT4 #( .INIT(16'hBF00)) \f_ex_imm[6]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(\imm_gen/ImmSel [0]), .I2(\imm_gen/ImmSel [1]), .I3(douta_reg_1[26]), .O(D[6])); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT4 #( .INIT(16'hBF00)) \f_ex_imm[7]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(\imm_gen/ImmSel [0]), .I2(\imm_gen/ImmSel [1]), .I3(douta_reg_1[27]), .O(D[7])); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT4 #( .INIT(16'hBF00)) \f_ex_imm[8]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(\imm_gen/ImmSel [0]), .I2(\imm_gen/ImmSel [1]), .I3(douta_reg_1[28]), .O(D[8])); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT4 #( .INIT(16'hBF00)) \f_ex_imm[9]_i_1 (.I0(\imm_gen/ImmSel [2]), .I1(\imm_gen/ImmSel [0]), .I2(\imm_gen/ImmSel [1]), .I3(douta_reg_1[29]), .O(D[9])); LUT4 #( .INIT(16'h44F4)) \f_ex_inst[0]_i_1 (.I0(\wb_alu_reg[31]_1 ), .I1(doutb[0]), .I2(out[0]), .I3(\wb_alu_reg[31] ), .O(douta_reg_1[0])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[10]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[10]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[10]), .O(douta_reg_1[10])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[11]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[11]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[11]), .O(douta_reg_1[11])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[12]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[12]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[12]), .O(douta_reg_1[12])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[13]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[13]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[13]), .O(douta_reg_1[13])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[14]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[14]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[14]), .O(douta_reg_1[14])); LUT4 #( .INIT(16'h44F4)) \f_ex_inst[1]_i_1 (.I0(\wb_alu_reg[31]_1 ), .I1(doutb[1]), .I2(out[1]), .I3(\wb_alu_reg[31] ), .O(douta_reg_1[1])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[25]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[25]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[25]), .O(douta_reg_1[25])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[26]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[26]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[26]), .O(douta_reg_1[26])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[27]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[27]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[27]), .O(douta_reg_1[27])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[28]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[28]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[28]), .O(douta_reg_1[28])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[29]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[29]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[29]), .O(douta_reg_1[29])); LUT4 #( .INIT(16'h44F4)) \f_ex_inst[2]_i_1 (.I0(\wb_alu_reg[31]_1 ), .I1(doutb[2]), .I2(out[2]), .I3(\wb_alu_reg[31] ), .O(douta_reg_1[2])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[30]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[30]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[30]), .O(douta_reg_1[30])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[3]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[3]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[3]), .O(douta_reg_1[3])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[4]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[4]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[4]), .O(douta_reg_1[4])); LUT4 #( .INIT(16'h44F4)) \f_ex_inst[5]_i_1 (.I0(\wb_alu_reg[31]_1 ), .I1(doutb[5]), .I2(out[5]), .I3(\wb_alu_reg[31] ), .O(douta_reg_1[5])); LUT4 #( .INIT(16'h44F4)) \f_ex_inst[6]_i_1 (.I0(\wb_alu_reg[31]_1 ), .I1(doutb[6]), .I2(out[6]), .I3(\wb_alu_reg[31] ), .O(douta_reg_1[6])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[7]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[7]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[7]), .O(douta_reg_1[7])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[8]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[8]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[8]), .O(douta_reg_1[8])); LUT4 #( .INIT(16'h4F44)) \f_ex_inst[9]_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[9]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[9]), .O(douta_reg_1[9])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[0]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[0]), .O(douta_reg_1_0[0])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[10]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[10]), .O(douta_reg_1_0[10])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[11]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[11]), .O(douta_reg_1_0[11])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[12]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[12]), .O(douta_reg_1_0[12])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[13]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[13]), .O(douta_reg_1_0[13])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[14]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[14]), .O(douta_reg_1_0[14])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[15]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[15]), .O(douta_reg_1_0[15])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[16]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[16]), .O(douta_reg_1_0[16])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[17]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[17]), .O(douta_reg_1_0[17])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[18]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[18]), .O(douta_reg_1_0[18])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[19]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[19]), .O(douta_reg_1_0[19])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[1]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[1]), .O(douta_reg_1_0[1])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[20]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[20]), .O(douta_reg_1_0[20])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[21]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[21]), .O(douta_reg_1_0[21])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[22]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[22]), .O(douta_reg_1_0[22])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[23]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[23]), .O(douta_reg_1_0[23])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[24]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[24]), .O(douta_reg_1_0[24])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[25]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[25]), .O(douta_reg_1_0[25])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[26]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[26]), .O(douta_reg_1_0[26])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[27]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[27]), .O(douta_reg_1_0[27])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[28]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[28]), .O(douta_reg_1_0[28])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[29]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[29]), .O(douta_reg_1_0[29])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[2]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[2]), .O(douta_reg_1_0[2])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[30]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[30]), .O(douta_reg_1_0[30])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[31]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[31]), .O(douta_reg_1_0[31])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[3]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[3]), .O(douta_reg_1_0[3])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[4]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[4]), .O(douta_reg_1_0[4])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[5]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[5]), .O(douta_reg_1_0[5])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[6]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[6]), .O(douta_reg_1_0[6])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[7]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[7]), .O(douta_reg_1_0[7])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[8]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[8]), .O(douta_reg_1_0[8])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd1[9]_i_1 (.I0(douta_reg_1[17]), .I1(douta_reg_1[15]), .I2(douta_reg_1[16]), .I3(douta_reg_1[18]), .I4(douta_reg_1[19]), .I5(rd10[9]), .O(douta_reg_1_0[9])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[0]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[0]), .O(douta_reg_1_1[0])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[10]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[10]), .O(douta_reg_1_1[10])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[11]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[11]), .O(douta_reg_1_1[11])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[12]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[12]), .O(douta_reg_1_1[12])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[13]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[13]), .O(douta_reg_1_1[13])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[14]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[14]), .O(douta_reg_1_1[14])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[15]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[15]), .O(douta_reg_1_1[15])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[16]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[16]), .O(douta_reg_1_1[16])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[17]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[17]), .O(douta_reg_1_1[17])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[18]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[18]), .O(douta_reg_1_1[18])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[19]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[19]), .O(douta_reg_1_1[19])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[1]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[1]), .O(douta_reg_1_1[1])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[20]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[20]), .O(douta_reg_1_1[20])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[21]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[21]), .O(douta_reg_1_1[21])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[22]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[22]), .O(douta_reg_1_1[22])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[23]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[23]), .O(douta_reg_1_1[23])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[24]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[24]), .O(douta_reg_1_1[24])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[25]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[25]), .O(douta_reg_1_1[25])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[26]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[26]), .O(douta_reg_1_1[26])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[27]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[27]), .O(douta_reg_1_1[27])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[28]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[28]), .O(douta_reg_1_1[28])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[29]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[29]), .O(douta_reg_1_1[29])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[2]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[2]), .O(douta_reg_1_1[2])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[30]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[30]), .O(douta_reg_1_1[30])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[31]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[31]), .O(douta_reg_1_1[31])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[3]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[3]), .O(douta_reg_1_1[3])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[4]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[4]), .O(douta_reg_1_1[4])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[5]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[5]), .O(douta_reg_1_1[5])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[6]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[6]), .O(douta_reg_1_1[6])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[7]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[7]), .O(douta_reg_1_1[7])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[8]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[8]), .O(douta_reg_1_1[8])); LUT6 #( .INIT(64'hFFFFFFFE00000000)) \f_ex_rd2[9]_i_1 (.I0(douta_reg_1[22]), .I1(douta_reg_1[20]), .I2(douta_reg_1[21]), .I3(douta_reg_1[23]), .I4(douta_reg_1[24]), .I5(rd20[9]), .O(douta_reg_1_1[9])); CARRY4 \hit00_inferred__0/i__carry (.CI(\<const0> ), .CO({\hit00_inferred__0/i__carry_n_0 ,\hit00_inferred__0/i__carry_n_1 ,\hit00_inferred__0/i__carry_n_2 ,\hit00_inferred__0/i__carry_n_3 }), .CYINIT(\<const1> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .S({i__carry_i_1_n_0,i__carry_i_2_n_0,i__carry_i_3_n_0,i__carry_i_4_n_0})); CARRY4 \hit00_inferred__0/i__carry__0 (.CI(\hit00_inferred__0/i__carry_n_0 ), .CO({\hit00_inferred__0/i__carry__0_n_0 ,\hit00_inferred__0/i__carry__0_n_1 ,\hit00_inferred__0/i__carry__0_n_2 ,\hit00_inferred__0/i__carry__0_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .S({i__carry__0_i_1_n_0,i__carry__0_i_2_n_0,i__carry__0_i_3_n_0,i__carry__0_i_4_n_0})); CARRY4 \hit00_inferred__0/i__carry__1 (.CI(\hit00_inferred__0/i__carry__0_n_0 ), .CO(hit00), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .S({\<const0> ,\<const0> ,\<const0> ,i__carry__1_i_1_n_0})); CARRY4 \hit10_inferred__0/i__carry (.CI(\<const0> ), .CO({\hit10_inferred__0/i__carry_n_0 ,\hit10_inferred__0/i__carry_n_1 ,\hit10_inferred__0/i__carry_n_2 ,\hit10_inferred__0/i__carry_n_3 }), .CYINIT(\<const1> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .S({i__carry_i_1__0_n_0,i__carry_i_2__0_n_0,i__carry_i_3__0_n_0,i__carry_i_4__0_n_0})); CARRY4 \hit10_inferred__0/i__carry__0 (.CI(\hit10_inferred__0/i__carry_n_0 ), .CO({\hit10_inferred__0/i__carry__0_n_0 ,\hit10_inferred__0/i__carry__0_n_1 ,\hit10_inferred__0/i__carry__0_n_2 ,\hit10_inferred__0/i__carry__0_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .S({i__carry__0_i_1__0_n_0,i__carry__0_i_2__0_n_0,i__carry__0_i_3__0_n_0,i__carry__0_i_4__0_n_0})); CARRY4 \hit10_inferred__0/i__carry__1 (.CI(\hit10_inferred__0/i__carry__0_n_0 ), .CO(hit10), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .S({\<const0> ,\<const0> ,\<const0> ,i__carry__1_i_1__0_n_0})); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_1 (.I0(hit01[21]), .I1(Q[24]), .I2(Q[26]), .I3(hit01[23]), .I4(Q[25]), .I5(hit01[22]), .O(i__carry__0_i_1_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_1__0 (.I0(hit11[21]), .I1(i__carry__1_i_1__0_0[25]), .I2(i__carry__1_i_1__0_0[27]), .I3(hit11[23]), .I4(i__carry__1_i_1__0_0[26]), .I5(hit11[22]), .O(i__carry__0_i_1__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_2 (.I0(hit01[18]), .I1(Q[21]), .I2(Q[23]), .I3(hit01[20]), .I4(Q[22]), .I5(hit01[19]), .O(i__carry__0_i_2_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_2__0 (.I0(hit11[18]), .I1(i__carry__1_i_1__0_0[22]), .I2(i__carry__1_i_1__0_0[24]), .I3(hit11[20]), .I4(i__carry__1_i_1__0_0[23]), .I5(hit11[19]), .O(i__carry__0_i_2__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_3 (.I0(hit01[15]), .I1(Q[18]), .I2(Q[20]), .I3(hit01[17]), .I4(Q[19]), .I5(hit01[16]), .O(i__carry__0_i_3_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_3__0 (.I0(hit11[15]), .I1(i__carry__1_i_1__0_0[19]), .I2(i__carry__1_i_1__0_0[21]), .I3(hit11[17]), .I4(i__carry__1_i_1__0_0[20]), .I5(hit11[16]), .O(i__carry__0_i_3__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_4 (.I0(hit01[12]), .I1(Q[15]), .I2(Q[17]), .I3(hit01[14]), .I4(Q[16]), .I5(hit01[13]), .O(i__carry__0_i_4_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_4__0 (.I0(hit11[12]), .I1(i__carry__1_i_1__0_0[16]), .I2(i__carry__1_i_1__0_0[18]), .I3(hit11[14]), .I4(i__carry__1_i_1__0_0[17]), .I5(hit11[13]), .O(i__carry__0_i_4__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__1_i_1 (.I0(hit01[24]), .I1(Q[27]), .I2(Q[29]), .I3(hit01[26]), .I4(Q[28]), .I5(hit01[25]), .O(i__carry__1_i_1_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry__1_i_1__0 (.I0(hit11[24]), .I1(i__carry__1_i_1__0_0[28]), .I2(i__carry__1_i_1__0_0[30]), .I3(hit11[26]), .I4(i__carry__1_i_1__0_0[29]), .I5(hit11[25]), .O(i__carry__1_i_1__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_1 (.I0(hit01[9]), .I1(Q[12]), .I2(Q[14]), .I3(hit01[11]), .I4(Q[13]), .I5(hit01[10]), .O(i__carry_i_1_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_1__0 (.I0(hit11[9]), .I1(i__carry__1_i_1__0_0[13]), .I2(i__carry__1_i_1__0_0[15]), .I3(hit11[11]), .I4(i__carry__1_i_1__0_0[14]), .I5(hit11[10]), .O(i__carry_i_1__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_2 (.I0(hit01[6]), .I1(Q[9]), .I2(Q[11]), .I3(hit01[8]), .I4(Q[10]), .I5(hit01[7]), .O(i__carry_i_2_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_2__0 (.I0(hit11[6]), .I1(i__carry__1_i_1__0_0[10]), .I2(i__carry__1_i_1__0_0[12]), .I3(hit11[8]), .I4(i__carry__1_i_1__0_0[11]), .I5(hit11[7]), .O(i__carry_i_2__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_3 (.I0(hit01[3]), .I1(Q[6]), .I2(Q[8]), .I3(hit01[5]), .I4(Q[7]), .I5(hit01[4]), .O(i__carry_i_3_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_3__0 (.I0(hit11[3]), .I1(i__carry__1_i_1__0_0[7]), .I2(i__carry__1_i_1__0_0[9]), .I3(hit11[5]), .I4(i__carry__1_i_1__0_0[8]), .I5(hit11[4]), .O(i__carry_i_3__0_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_4 (.I0(hit01[0]), .I1(Q[3]), .I2(Q[5]), .I3(hit01[2]), .I4(Q[4]), .I5(hit01[1]), .O(i__carry_i_4_n_0)); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_4__0 (.I0(hit11[0]), .I1(i__carry__1_i_1__0_0[4]), .I2(i__carry__1_i_1__0_0[6]), .I3(hit11[2]), .I4(i__carry__1_i_1__0_0[5]), .I5(hit11[1]), .O(i__carry_i_4__0_n_0)); LUT5 #( .INIT(32'hFFFF0001)) \is_valid[0]_i_1 (.I0(\ex_wb_inst_reg[6] ), .I1(i__carry__1_i_1__0_0[3]), .I2(i__carry__1_i_1__0_0[1]), .I3(i__carry__1_i_1__0_0[2]), .I4(is_valid[0]), .O(\is_valid[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF0010)) \is_valid[1]_i_1 (.I0(\ex_wb_inst_reg[6] ), .I1(i__carry__1_i_1__0_0[3]), .I2(i__carry__1_i_1__0_0[1]), .I3(i__carry__1_i_1__0_0[2]), .I4(is_valid[1]), .O(\is_valid[1]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF0010)) \is_valid[2]_i_1 (.I0(\ex_wb_inst_reg[6] ), .I1(i__carry__1_i_1__0_0[3]), .I2(i__carry__1_i_1__0_0[2]), .I3(i__carry__1_i_1__0_0[1]), .I4(is_valid[2]), .O(\is_valid[2]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF1000)) \is_valid[3]_i_1 (.I0(\ex_wb_inst_reg[6] ), .I1(i__carry__1_i_1__0_0[3]), .I2(i__carry__1_i_1__0_0[1]), .I3(i__carry__1_i_1__0_0[2]), .I4(is_valid[3]), .O(\is_valid[3]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF0004)) \is_valid[4]_i_1 (.I0(\ex_wb_inst_reg[6] ), .I1(i__carry__1_i_1__0_0[3]), .I2(i__carry__1_i_1__0_0[1]), .I3(i__carry__1_i_1__0_0[2]), .I4(is_valid[4]), .O(\is_valid[4]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF0040)) \is_valid[5]_i_1 (.I0(\ex_wb_inst_reg[6] ), .I1(i__carry__1_i_1__0_0[3]), .I2(i__carry__1_i_1__0_0[1]), .I3(i__carry__1_i_1__0_0[2]), .I4(is_valid[5]), .O(\is_valid[5]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF0040)) \is_valid[6]_i_1 (.I0(\ex_wb_inst_reg[6] ), .I1(i__carry__1_i_1__0_0[3]), .I2(i__carry__1_i_1__0_0[2]), .I3(i__carry__1_i_1__0_0[1]), .I4(is_valid[6]), .O(\is_valid[6]_i_1_n_0 )); LUT5 #( .INIT(32'hFFFF4000)) \is_valid[7]_i_1 (.I0(\ex_wb_inst_reg[6] ), .I1(i__carry__1_i_1__0_0[3]), .I2(i__carry__1_i_1__0_0[1]), .I3(i__carry__1_i_1__0_0[2]), .I4(is_valid[7]), .O(\is_valid[7]_i_1_n_0 )); FDRE \is_valid_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(\is_valid[0]_i_1_n_0 ), .Q(is_valid[0]), .R(cpu_reset)); FDRE \is_valid_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(\is_valid[1]_i_1_n_0 ), .Q(is_valid[1]), .R(cpu_reset)); FDRE \is_valid_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(\is_valid[2]_i_1_n_0 ), .Q(is_valid[2]), .R(cpu_reset)); FDRE \is_valid_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(\is_valid[3]_i_1_n_0 ), .Q(is_valid[3]), .R(cpu_reset)); FDRE \is_valid_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(\is_valid[4]_i_1_n_0 ), .Q(is_valid[4]), .R(cpu_reset)); FDRE \is_valid_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(\is_valid[5]_i_1_n_0 ), .Q(is_valid[5]), .R(cpu_reset)); FDRE \is_valid_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(\is_valid[6]_i_1_n_0 ), .Q(is_valid[6]), .R(cpu_reset)); FDRE \is_valid_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(\is_valid[7]_i_1_n_0 ), .Q(is_valid[7]), .R(cpu_reset)); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_10__0 (.I0(\pc_reg[31] [10]), .I1(data3[9]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_29__0_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [10])); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_11__0 (.I0(\pc_reg[31] [9]), .I1(data3[8]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_30__0_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [9])); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_12__0 (.I0(\pc_reg[31] [8]), .I1(data3[7]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_32_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [8])); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_13__0 (.I0(\pc_reg[31] [7]), .I1(data3[6]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_33__0_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [7])); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_14__0 (.I0(\pc_reg[31] [6]), .I1(data3[5]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_34__0_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [6])); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_15__0 (.I0(\pc_reg[31] [5]), .I1(data3[4]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_35__0_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [5])); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_16__0 (.I0(\pc_reg[31] [4]), .I1(data3[3]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_37_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [4])); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_17 (.I0(\pc_reg[31] [3]), .I1(data3[2]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_38_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [3])); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_18__0 (.I0(\pc_reg[31] [2]), .I1(data3[1]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_39__0_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [2])); LUT5 #( .INIT(32'hBBBF88C8)) mem_reg_0_0_i_21__0 (.I0(\f_ex_pc_reg[4] ), .I1(SWITCHES_IBUF), .I2(wb_br_taken), .I3(\ex_wb_inst_reg[6] ), .I4(br), .O(mem_reg_0_0_i_21__0_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_22__0 (.I0(data2[14]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(mem_reg_3_3[3]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [15]), .O(mem_reg_0_0_i_22__0_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_24__0 (.I0(data2[13]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(mem_reg_3_3[2]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [14]), .O(mem_reg_0_0_i_24__0_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_25 (.I0(data2[12]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(mem_reg_3_3[1]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [13]), .O(mem_reg_0_0_i_25_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_27__0 (.I0(data2[11]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(mem_reg_3_3[0]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [12]), .O(mem_reg_0_0_i_27__0_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_28__0 (.I0(data2[10]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(mem_reg_0_0_0[3]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [11]), .O(mem_reg_0_0_i_28__0_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_29__0 (.I0(data2[9]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(mem_reg_0_0_0[2]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [10]), .O(mem_reg_0_0_i_29__0_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_30__0 (.I0(data2[8]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(mem_reg_0_0_0[1]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [9]), .O(mem_reg_0_0_i_30__0_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_32 (.I0(data2[7]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(mem_reg_0_0_0[0]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [8]), .O(mem_reg_0_0_i_32_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_33__0 (.I0(data2[6]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(mem_reg_0_0[3]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [7]), .O(mem_reg_0_0_i_33__0_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_34__0 (.I0(data2[5]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(mem_reg_0_0[2]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [6]), .O(mem_reg_0_0_i_34__0_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_35__0 (.I0(data2[4]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(mem_reg_0_0[1]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [5]), .O(mem_reg_0_0_i_35__0_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_37 (.I0(data2[3]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(mem_reg_0_0[0]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [4]), .O(mem_reg_0_0_i_37_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_38 (.I0(data2[2]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(O[3]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [3]), .O(mem_reg_0_0_i_38_n_0)); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) mem_reg_0_0_i_39__0 (.I0(data2[1]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(O[2]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [2]), .O(mem_reg_0_0_i_39__0_n_0)); LUT5 #( .INIT(32'hFFFFFBFF)) mem_reg_0_0_i_41__0 (.I0(\f_ex_pc_reg[4] ), .I1(SWITCHES_IBUF), .I2(\ex_wb_inst_reg[6] ), .I3(wb_br_taken), .I4(br), .O(mem_reg_0_0_i_41__0_n_0)); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_5__0 (.I0(\pc_reg[31] [15]), .I1(data3[14]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_22__0_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [15])); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_6__0 (.I0(\pc_reg[31] [14]), .I1(data3[13]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_24__0_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [14])); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_7__0 (.I0(\pc_reg[31] [13]), .I1(data3[12]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_25_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [13])); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_8__0 (.I0(\pc_reg[31] [12]), .I1(data3[11]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_27__0_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [12])); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) mem_reg_0_0_i_9__0 (.I0(\pc_reg[31] [11]), .I1(data3[10]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(mem_reg_0_0_i_28__0_n_0), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [11])); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_10 (.I0(\wb_alu_reg[31] ), .I1(out[17]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[17]), .O(douta_reg_1[17])); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_11 (.I0(\wb_alu_reg[31] ), .I1(out[16]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[16]), .O(douta_reg_1[16])); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_12 (.I0(\wb_alu_reg[31] ), .I1(out[15]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[15]), .O(douta_reg_1[15])); LUT4 #( .INIT(16'hFFEF)) mem_reg_r1_0_31_0_5_i_26 (.I0(\wb_alu_reg[31]_0 [31]), .I1(\wb_alu_reg[31]_0 [29]), .I2(\wb_alu_reg[31]_0 [30]), .I3(\wb_alu_reg[31]_0 [28]), .O(\wb_alu_reg[31] )); LUT4 #( .INIT(16'hFFEF)) mem_reg_r1_0_31_0_5_i_27 (.I0(\wb_alu_reg[31]_0 [31]), .I1(\wb_alu_reg[31]_0 [29]), .I2(\wb_alu_reg[31]_0 [28]), .I3(\wb_alu_reg[31]_0 [30]), .O(\wb_alu_reg[31]_1 )); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_8 (.I0(\wb_alu_reg[31] ), .I1(out[19]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[19]), .O(douta_reg_1[19])); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_9 (.I0(\wb_alu_reg[31] ), .I1(out[18]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[18]), .O(douta_reg_1[18])); LUT4 #( .INIT(16'h4F44)) mem_reg_r2_0_31_0_5_i_1 (.I0(\wb_alu_reg[31] ), .I1(out[24]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[24]), .O(douta_reg_1[24])); LUT4 #( .INIT(16'h4F44)) mem_reg_r2_0_31_0_5_i_2 (.I0(\wb_alu_reg[31] ), .I1(out[23]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[23]), .O(douta_reg_1[23])); LUT4 #( .INIT(16'h4F44)) mem_reg_r2_0_31_0_5_i_3 (.I0(\wb_alu_reg[31] ), .I1(out[22]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[22]), .O(douta_reg_1[22])); LUT4 #( .INIT(16'h4F44)) mem_reg_r2_0_31_0_5_i_4 (.I0(\wb_alu_reg[31] ), .I1(out[21]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[21]), .O(douta_reg_1[21])); LUT4 #( .INIT(16'h4F44)) mem_reg_r2_0_31_0_5_i_5 (.I0(\wb_alu_reg[31] ), .I1(out[20]), .I2(\wb_alu_reg[31]_1 ), .I3(doutb[20]), .O(douta_reg_1[20])); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[0]_i_1 (.I0(\pc_reg[31] [0]), .I1(\pc_reg[0] ), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[0]_i_2_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [0])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[0]_i_2 (.I0(i__carry__1_i_1__0_0[0]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(O[0]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [0]), .O(\pc[0]_i_2_n_0 )); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[16]_i_1 (.I0(\pc_reg[31] [16]), .I1(data3[15]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[16]_i_2_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [16])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[16]_i_2 (.I0(data2[15]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[19] [0]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [16]), .O(\pc[16]_i_2_n_0 )); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[17]_i_1 (.I0(\pc_reg[31] [17]), .I1(data3[16]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[17]_i_2_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [17])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[17]_i_2 (.I0(data2[16]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[19] [1]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [17]), .O(\pc[17]_i_2_n_0 )); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[18]_i_1 (.I0(\pc_reg[31] [18]), .I1(data3[17]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[18]_i_2_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [18])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[18]_i_2 (.I0(data2[17]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[19] [2]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [18]), .O(\pc[18]_i_2_n_0 )); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[19]_i_1 (.I0(\pc_reg[31] [19]), .I1(data3[18]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[19]_i_2_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [19])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[19]_i_2 (.I0(data2[18]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[19] [3]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [19]), .O(\pc[19]_i_2_n_0 )); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[1]_i_1 (.I0(\pc_reg[31] [1]), .I1(data3[0]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[1]_i_2_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [1])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[1]_i_2 (.I0(data2[0]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(O[1]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [1]), .O(\pc[1]_i_2_n_0 )); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[20]_i_1 (.I0(\pc_reg[31] [20]), .I1(data3[19]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[20]_i_3_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [20])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[20]_i_3 (.I0(data2[19]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[23] [0]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [20]), .O(\pc[20]_i_3_n_0 )); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[21]_i_1 (.I0(\pc_reg[31] [21]), .I1(data3[20]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[21]_i_2_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [21])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[21]_i_2 (.I0(data2[20]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[23] [1]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [21]), .O(\pc[21]_i_2_n_0 )); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[22]_i_1 (.I0(\pc_reg[31] [22]), .I1(data3[21]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[22]_i_2_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [22])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[22]_i_2 (.I0(data2[21]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[23] [2]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [22]), .O(\pc[22]_i_2_n_0 )); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[23]_i_1 (.I0(\pc_reg[31] [23]), .I1(data3[22]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[23]_i_2_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [23])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[23]_i_2 (.I0(data2[22]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[23] [3]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [23]), .O(\pc[23]_i_2_n_0 )); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[24]_i_1 (.I0(\pc_reg[31] [24]), .I1(data3[23]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[24]_i_3_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [24])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[24]_i_3 (.I0(data2[23]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[27] [0]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [24]), .O(\pc[24]_i_3_n_0 )); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[25]_i_1 (.I0(\pc_reg[31] [25]), .I1(data3[24]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[25]_i_2_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [25])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[25]_i_2 (.I0(data2[24]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[27] [1]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [25]), .O(\pc[25]_i_2_n_0 )); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[26]_i_1 (.I0(\pc_reg[31] [26]), .I1(data3[25]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[26]_i_2_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [26])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[26]_i_2 (.I0(data2[25]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[27] [2]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [26]), .O(\pc[26]_i_2_n_0 )); LUT6 #( .INIT(64'h0000FF0C0000AAAA)) \pc[27]_i_1 (.I0(\pc_reg[31] [27]), .I1(data3[26]), .I2(mem_reg_0_0_i_21__0_n_0), .I3(\pc[27]_i_2_n_0 ), .I4(cpu_reset), .I5(\pc_reg[31]_0 ), .O(\wb_alu_reg[31]_0 [27])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[27]_i_2 (.I0(data2[26]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[27] [3]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [27]), .O(\pc[27]_i_2_n_0 )); LUT6 #( .INIT(64'h00F200FF00F20000)) \pc[28]_i_1 (.I0(data3[27]), .I1(mem_reg_0_0_i_21__0_n_0), .I2(\pc[28]_i_3_n_0 ), .I3(cpu_reset), .I4(\pc_reg[31]_0 ), .I5(\pc_reg[31] [28]), .O(\wb_alu_reg[31]_0 [28])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[28]_i_3 (.I0(data2[27]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[31]_1 [0]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [28]), .O(\pc[28]_i_3_n_0 )); LUT6 #( .INIT(64'h00F200FF00F20000)) \pc[29]_i_1 (.I0(data3[28]), .I1(mem_reg_0_0_i_21__0_n_0), .I2(\pc[29]_i_2_n_0 ), .I3(cpu_reset), .I4(\pc_reg[31]_0 ), .I5(\pc_reg[31] [29]), .O(\wb_alu_reg[31]_0 [29])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[29]_i_2 (.I0(data2[28]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[31]_1 [1]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [29]), .O(\pc[29]_i_2_n_0 )); LUT6 #( .INIT(64'hAEFFAEAEAEAEAEAE)) \pc[30]_i_1 (.I0(\pc[30]_i_2_n_0 ), .I1(\pc_reg[31] [30]), .I2(\pc[30]_i_3_n_0 ), .I3(mem_reg_0_0_i_21__0_n_0), .I4(\pc_reg[31]_0 ), .I5(data3[29]), .O(\wb_alu_reg[31]_0 [30])); LUT6 #( .INIT(64'hF2FEF2F2FEFEFEFE)) \pc[30]_i_2 (.I0(\pc_reg[31] [30]), .I1(\pc_reg[31]_0 ), .I2(cpu_reset), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc_reg[31]_1 [2]), .I5(\pc[30]_i_4_n_0 ), .O(\pc[30]_i_2_n_0 )); LUT5 #( .INIT(32'hCFCFCF8F)) \pc[30]_i_3 (.I0(\f_ex_pc_reg[4] ), .I1(SWITCHES_IBUF), .I2(br), .I3(\ex_wb_inst_reg[6] ), .I4(wb_br_taken), .O(\pc[30]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFBFFFFFFFFF)) \pc[30]_i_4 (.I0(\f_ex_pc_reg[4] ), .I1(SWITCHES_IBUF), .I2(wb_br_taken), .I3(br), .I4(\ex_wb_inst_reg[6] ), .I5(data2[29]), .O(\pc[30]_i_4_n_0 )); LUT6 #( .INIT(64'h00F200FF00F20000)) \pc[31]_i_1 (.I0(data3[30]), .I1(mem_reg_0_0_i_21__0_n_0), .I2(\pc[31]_i_3_n_0 ), .I3(cpu_reset), .I4(\pc_reg[31]_0 ), .I5(\pc_reg[31] [31]), .O(\wb_alu_reg[31]_0 [31])); LUT6 #( .INIT(64'h22F2FFFF22F222F2)) \pc[31]_i_3 (.I0(data2[30]), .I1(mem_reg_0_0_i_41__0_n_0), .I2(\pc_reg[31]_1 [3]), .I3(\f_ex_imm[30]_i_3_n_0 ), .I4(\pc[30]_i_3_n_0 ), .I5(\pc_reg[31] [31]), .O(\pc[31]_i_3_n_0 )); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "0" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_0_0 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[4]), .DPO(hit01[0]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[0]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "10" *) (* ram_slice_end = "10" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_10_10 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[14]), .DPO(hit01[10]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[10]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "11" *) (* ram_slice_end = "11" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_11_11 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[15]), .DPO(hit01[11]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[11]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "12" *) (* ram_slice_end = "12" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_12_12 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[16]), .DPO(hit01[12]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[12]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "13" *) (* ram_slice_end = "13" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_13_13 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[17]), .DPO(hit01[13]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[13]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "14" *) (* ram_slice_end = "14" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_14_14 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[18]), .DPO(hit01[14]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[14]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "15" *) (* ram_slice_end = "15" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_15_15 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[19]), .DPO(hit01[15]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[15]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "16" *) (* ram_slice_end = "16" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_16_16 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[20]), .DPO(hit01[16]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[16]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "17" *) (* ram_slice_end = "17" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_17_17 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[21]), .DPO(hit01[17]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[17]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "18" *) (* ram_slice_end = "18" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_18_18 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[22]), .DPO(hit01[18]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[18]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "19" *) (* ram_slice_end = "19" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_19_19 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[23]), .DPO(hit01[19]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[19]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "1" *) (* ram_slice_end = "1" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_1_1 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[5]), .DPO(hit01[1]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[1]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "20" *) (* ram_slice_end = "20" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_20_20 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[24]), .DPO(hit01[20]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[20]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "21" *) (* ram_slice_end = "21" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_21_21 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[25]), .DPO(hit01[21]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[21]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "22" *) (* ram_slice_end = "22" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_22_22 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[26]), .DPO(hit01[22]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[22]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "23" *) (* ram_slice_end = "23" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_23_23 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[27]), .DPO(hit01[23]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[23]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "24" *) (* ram_slice_end = "24" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_24_24 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[28]), .DPO(hit01[24]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[24]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "25" *) (* ram_slice_end = "25" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_25_25 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[29]), .DPO(hit01[25]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[25]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "26" *) (* ram_slice_end = "26" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_26_26 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[30]), .DPO(hit01[26]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[26]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "2" *) (* ram_slice_end = "2" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_2_2 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[6]), .DPO(hit01[2]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[2]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "3" *) (* ram_slice_end = "3" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_3_3 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[7]), .DPO(hit01[3]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[3]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "4" *) (* ram_slice_end = "4" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_4_4 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[8]), .DPO(hit01[4]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[4]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "5" *) (* ram_slice_end = "5" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_5_5 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[9]), .DPO(hit01[5]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[5]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "6" *) (* ram_slice_end = "6" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_6_6 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[10]), .DPO(hit01[6]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[6]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "7" *) (* ram_slice_end = "7" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_7_7 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[11]), .DPO(hit01[7]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[7]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "8" *) (* ram_slice_end = "8" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_8_8 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[12]), .DPO(hit01[8]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[8]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); (* RTL_RAM_BITS = "216" *) (* RTL_RAM_NAME = "cache/tag" *) (* RTL_RAM_TYPE = "RAM_TDP" *) (* XILINX_LEGACY_PRIM = "RAM16X1D" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "7" *) (* ram_offset = "0" *) (* ram_slice_begin = "9" *) (* ram_slice_end = "9" *) RAM32X1D #( .INIT(32'h00000000)) tag_reg_0_7_9_9 (.A0(i__carry__1_i_1__0_0[1]), .A1(i__carry__1_i_1__0_0[2]), .A2(i__carry__1_i_1__0_0[3]), .A3(\<const0> ), .A4(GND_2), .D(i__carry__1_i_1__0_0[13]), .DPO(hit01[9]), .DPRA0(Q[0]), .DPRA1(Q[1]), .DPRA2(Q[2]), .DPRA3(\<const0> ), .DPRA4(GND_2), .SPO(hit11[9]), .WCLK(cpu_clk), .WE(data_reg_0_7_0_0_i_2_n_0)); LUT6 #( .INIT(64'h8880008000000000)) wb_br_taken_i_2 (.I0(wb_br_taken_reg), .I1(hit00), .I2(wb_br_taken_i_5_n_0), .I3(Q[2]), .I4(wb_br_taken_i_6_n_0), .I5(cache_out_guess), .O(\f_ex_pc_reg[4] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) wb_br_taken_i_5 (.I0(is_valid[3]), .I1(is_valid[2]), .I2(Q[1]), .I3(is_valid[1]), .I4(Q[0]), .I5(is_valid[0]), .O(wb_br_taken_i_5_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) wb_br_taken_i_6 (.I0(is_valid[7]), .I1(is_valid[6]), .I2(Q[1]), .I3(is_valid[5]), .I4(Q[0]), .I5(is_valid[4]), .O(wb_br_taken_i_6_n_0)); endmodule module branch_predictor (D, douta_reg_1, \ex_wb_inst_reg[6] , douta_reg_1_0, douta_reg_1_1, \wb_alu_reg[31] , \wb_alu_reg[31]_0 , \wb_alu_reg[31]_1 , br_pred_taken, SR, douta_reg_1_2, br_inst_cnt, cpu_clk_locked, buttons_pressed, rd10, rd20, SWITCHES_IBUF, br, wb_br_taken, data2, \f_ex_rd2_reg[0] , wb_br_taken_reg, Q, i__carry__1_i_1__0, \f_ex_imm_reg[30] , \pc_reg[31] , \pc_reg[0] , cpu_reset, \pc_reg[31]_0 , O, data3, mem_reg_0_0, mem_reg_0_0_0, mem_reg_3_3, \pc_reg[19] , \pc_reg[23] , \pc_reg[27] , \br_inst_cnt_reg[0] , doutb, out, \pc_reg[31]_1 , \f_ex_rd2_reg[0]_0 , cpu_clk); output [30:0]D; output [30:0]douta_reg_1; output \ex_wb_inst_reg[6] ; output [31:0]douta_reg_1_0; output [31:0]douta_reg_1_1; output \wb_alu_reg[31] ; output [31:0]\wb_alu_reg[31]_0 ; output \wb_alu_reg[31]_1 ; output br_pred_taken; output [0:0]SR; output douta_reg_1_2; output br_inst_cnt; input cpu_clk_locked; input buttons_pressed; input [31:0]rd10; input [31:0]rd20; input [0:0]SWITCHES_IBUF; input br; input wb_br_taken; input [30:0]data2; input \f_ex_rd2_reg[0] ; input wb_br_taken_reg; input [29:0]Q; input [30:0]i__carry__1_i_1__0; input \f_ex_imm_reg[30] ; input [31:0]\pc_reg[31] ; input [0:0]\pc_reg[0] ; input cpu_reset; input \pc_reg[31]_0 ; input [3:0]O; input [30:0]data3; input [3:0]mem_reg_0_0; input [3:0]mem_reg_0_0_0; input [3:0]mem_reg_3_3; input [3:0]\pc_reg[19] ; input [3:0]\pc_reg[23] ; input [3:0]\pc_reg[27] ; input \br_inst_cnt_reg[0] ; input [31:0]doutb; input [31:0]out; input [3:0]\pc_reg[31]_1 ; input [6:0]\f_ex_rd2_reg[0]_0 ; input cpu_clk; wire [30:0]D; wire [3:0]O; wire [29:0]Q; wire [0:0]SR; wire [0:0]SWITCHES_IBUF; wire br; wire br_inst_cnt; wire \br_inst_cnt_reg[0] ; wire br_pred_taken; wire buttons_pressed; wire cpu_clk; wire cpu_clk_locked; wire cpu_reset; wire [30:0]data2; wire [30:0]data3; wire [30:0]douta_reg_1; wire [31:0]douta_reg_1_0; wire [31:0]douta_reg_1_1; wire douta_reg_1_2; wire [31:0]doutb; wire \ex_wb_inst_reg[6] ; wire \f_ex_imm_reg[30] ; wire \f_ex_rd2_reg[0] ; wire [6:0]\f_ex_rd2_reg[0]_0 ; wire [30:0]i__carry__1_i_1__0; wire [3:0]mem_reg_0_0; wire [3:0]mem_reg_0_0_0; wire [3:0]mem_reg_3_3; wire [31:0]out; wire [0:0]\pc_reg[0] ; wire [3:0]\pc_reg[19] ; wire [3:0]\pc_reg[23] ; wire [3:0]\pc_reg[27] ; wire [31:0]\pc_reg[31] ; wire \pc_reg[31]_0 ; wire [3:0]\pc_reg[31]_1 ; wire [31:0]rd10; wire [31:0]rd20; wire \wb_alu_reg[31] ; wire [31:0]\wb_alu_reg[31]_0 ; wire \wb_alu_reg[31]_1 ; wire wb_br_taken; wire wb_br_taken_reg; bp_cache cache (.D(D), .O(O), .Q(Q), .SR(SR), .SWITCHES_IBUF(SWITCHES_IBUF), .br(br), .br_inst_cnt(br_inst_cnt), .\br_inst_cnt_reg[0] (\br_inst_cnt_reg[0] ), .buttons_pressed(buttons_pressed), .cpu_clk(cpu_clk), .cpu_clk_locked(cpu_clk_locked), .cpu_reset(cpu_reset), .data2(data2), .data3(data3), .douta_reg_1(douta_reg_1), .douta_reg_1_0(douta_reg_1_0), .douta_reg_1_1(douta_reg_1_1), .douta_reg_1_2(douta_reg_1_2), .doutb(doutb), .\ex_wb_inst_reg[6] (\ex_wb_inst_reg[6] ), .\f_ex_imm_reg[30] (\f_ex_imm_reg[30] ), .\f_ex_pc_reg[4] (br_pred_taken), .\f_ex_rd2_reg[0] (\f_ex_rd2_reg[0] ), .\f_ex_rd2_reg[0]_0 (\f_ex_rd2_reg[0]_0 ), .i__carry__1_i_1__0_0(i__carry__1_i_1__0), .mem_reg_0_0(mem_reg_0_0), .mem_reg_0_0_0(mem_reg_0_0_0), .mem_reg_3_3(mem_reg_3_3), .out(out), .\pc_reg[0] (\pc_reg[0] ), .\pc_reg[19] (\pc_reg[19] ), .\pc_reg[23] (\pc_reg[23] ), .\pc_reg[27] (\pc_reg[27] ), .\pc_reg[31] (\pc_reg[31] ), .\pc_reg[31]_0 (\pc_reg[31]_0 ), .\pc_reg[31]_1 (\pc_reg[31]_1 ), .rd10(rd10), .rd20(rd20), .\wb_alu_reg[31] (\wb_alu_reg[31] ), .\wb_alu_reg[31]_0 (\wb_alu_reg[31]_0 ), .\wb_alu_reg[31]_1 (\wb_alu_reg[31]_1 ), .wb_br_taken(wb_br_taken), .wb_br_taken_reg(wb_br_taken_reg)); endmodule module button_parser (buttons_pressed, cpu_reset, BUTTONS_IBUF, cpu_clk, cpu_clk_locked); output buttons_pressed; output cpu_reset; input [0:0]BUTTONS_IBUF; input cpu_clk; input cpu_clk_locked; wire [0:0]BUTTONS_IBUF; wire button_debouncer_n_0; wire button_synchronizer_n_0; wire buttons_pressed; wire cpu_clk; wire cpu_clk_locked; wire cpu_reset; wire [0:0]debounced_signals; wire [0:0]pulse; debouncer button_debouncer (.SR(button_synchronizer_n_0), .cpu_clk(cpu_clk), .debounced_signals(debounced_signals), .pulse(pulse), .\saturating_counter_reg[0][8]_0 (button_debouncer_n_0)); edge_detector button_edge_detector (.buttons_pressed(buttons_pressed), .cpu_clk(cpu_clk), .cpu_clk_locked(cpu_clk_locked), .cpu_reset(cpu_reset), .debounced_signals(debounced_signals), .\out_reg[0]_0 (button_debouncer_n_0), .pulse(pulse)); synchronizer__parameterized0 button_synchronizer (.BUTTONS_IBUF(BUTTONS_IBUF), .SR(button_synchronizer_n_0), .cpu_clk(cpu_clk)); endmodule module clocks (cpu_clk, cpu_clk_locked, clk_125mhz); output cpu_clk; output cpu_clk_locked; input clk_125mhz; wire \<const0> ; wire \<const1> ; wire clk_125mhz; wire cpu_clk; wire cpu_clk_int; wire cpu_clk_locked; wire cpu_clk_pll_fb_in; wire cpu_clk_pll_fb_out; wire plle2_pwm_inst_n_8; wire pwm_clk; wire pwm_clk_int; wire pwm_clk_pll_fb_in; wire pwm_clk_pll_fb_out; GND GND (.G(\<const0> )); VCC VCC (.P(\<const1> )); (* BOX_TYPE = "PRIMITIVE" *) BUFG cpu_clk_buf (.I(cpu_clk_int), .O(cpu_clk)); (* BOX_TYPE = "PRIMITIVE" *) BUFG cpu_clk_f_buf (.I(cpu_clk_pll_fb_out), .O(cpu_clk_pll_fb_in)); (* BOX_TYPE = "PRIMITIVE" *) PLLE2_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT(34), .CLKFBOUT_PHASE(0.000000), .CLKIN1_PERIOD(8.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE(17), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT1_DIVIDE(1), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .COMPENSATION("BUF_IN"), .DIVCLK_DIVIDE(5), .IS_CLKINSEL_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.010000), .REF_JITTER2(0.010000), .STARTUP_WAIT("FALSE")) plle2_cpu_inst (.CLKFBIN(cpu_clk_pll_fb_in), .CLKFBOUT(cpu_clk_pll_fb_out), .CLKIN1(clk_125mhz), .CLKIN2(\<const0> ), .CLKINSEL(\<const1> ), .CLKOUT0(cpu_clk_int), .DADDR({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DCLK(\<const0> ), .DEN(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DWE(\<const0> ), .LOCKED(cpu_clk_locked), .PWRDWN(\<const0> ), .RST(\<const0> )); (* BOX_TYPE = "PRIMITIVE" *) PLLE2_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT(36), .CLKFBOUT_PHASE(0.000000), .CLKIN1_PERIOD(8.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE(6), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT1_DIVIDE(1), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT2_DIVIDE(1), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT3_DIVIDE(1), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .COMPENSATION("BUF_IN"), .DIVCLK_DIVIDE(5), .IS_CLKINSEL_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.010000), .REF_JITTER2(0.010000), .STARTUP_WAIT("FALSE")) plle2_pwm_inst (.CLKFBIN(pwm_clk_pll_fb_in), .CLKFBOUT(pwm_clk_pll_fb_out), .CLKIN1(clk_125mhz), .CLKIN2(\<const0> ), .CLKINSEL(\<const1> ), .CLKOUT0(pwm_clk_int), .DADDR({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DCLK(\<const0> ), .DEN(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DWE(\<const0> ), .LOCKED(plle2_pwm_inst_n_8), .PWRDWN(\<const0> ), .RST(\<const0> )); (* BOX_TYPE = "PRIMITIVE" *) BUFG pwm_clk_buf (.I(pwm_clk_int), .O(pwm_clk)); (* BOX_TYPE = "PRIMITIVE" *) BUFG pwm_clk_f_buf (.I(pwm_clk_pll_fb_out), .O(pwm_clk_pll_fb_in)); endmodule module cpu (serial_out, cpu_clk, cpu_clk_locked, buttons_pressed, SWITCHES_IBUF, cpu_reset, serial_in); output serial_out; input cpu_clk; input cpu_clk_locked; input buttons_pressed; input [0:0]SWITCHES_IBUF; input cpu_reset; input serial_in; wire \<const0> ; wire \<const1> ; wire [3:0]ALUSel; wire ASel; wire BSel; wire BrEq; wire BrLt; wire [3:0]MemRW; wire [0:0]SWITCHES_IBUF; wire [31:31]a_mux; wire [31:6]\alu/data0 ; wire [31:1]\alu/data8 ; wire [31:3]b_mux; wire bios_mem_n_116; wire bios_mem_n_118; wire bios_mem_n_126; wire bios_mem_n_177; wire bios_mem_n_178; wire bios_mem_n_179; wire bios_mem_n_180; wire bios_mem_n_181; wire bios_mem_n_182; wire bios_mem_n_183; wire bios_mem_n_184; wire bios_mem_n_185; wire bios_mem_n_186; wire bios_mem_n_187; wire bios_mem_n_188; wire bios_mem_n_189; wire bios_mem_n_190; wire bios_mem_n_191; wire bios_mem_n_192; wire bios_mem_n_193; wire bios_mem_n_194; wire bios_mem_n_195; wire bios_mem_n_196; wire bios_mem_n_197; wire bios_mem_n_198; wire bios_mem_n_199; wire bios_mem_n_201; wire bios_mem_n_202; wire bios_mem_n_204; wire bios_mem_n_225; wire bios_mem_n_3; wire bios_mem_n_36; wire bios_mem_n_4; wire br; wire br_corr_cnt0; wire \br_corr_cnt[0]_i_3_n_0 ; wire [31:0]br_corr_cnt_reg; wire \br_corr_cnt_reg[0]_i_2_n_0 ; wire \br_corr_cnt_reg[0]_i_2_n_1 ; wire \br_corr_cnt_reg[0]_i_2_n_2 ; wire \br_corr_cnt_reg[0]_i_2_n_3 ; wire \br_corr_cnt_reg[0]_i_2_n_4 ; wire \br_corr_cnt_reg[0]_i_2_n_5 ; wire \br_corr_cnt_reg[0]_i_2_n_6 ; wire \br_corr_cnt_reg[0]_i_2_n_7 ; wire \br_corr_cnt_reg[12]_i_1_n_0 ; wire \br_corr_cnt_reg[12]_i_1_n_1 ; wire \br_corr_cnt_reg[12]_i_1_n_2 ; wire \br_corr_cnt_reg[12]_i_1_n_3 ; wire \br_corr_cnt_reg[12]_i_1_n_4 ; wire \br_corr_cnt_reg[12]_i_1_n_5 ; wire \br_corr_cnt_reg[12]_i_1_n_6 ; wire \br_corr_cnt_reg[12]_i_1_n_7 ; wire \br_corr_cnt_reg[16]_i_1_n_0 ; wire \br_corr_cnt_reg[16]_i_1_n_1 ; wire \br_corr_cnt_reg[16]_i_1_n_2 ; wire \br_corr_cnt_reg[16]_i_1_n_3 ; wire \br_corr_cnt_reg[16]_i_1_n_4 ; wire \br_corr_cnt_reg[16]_i_1_n_5 ; wire \br_corr_cnt_reg[16]_i_1_n_6 ; wire \br_corr_cnt_reg[16]_i_1_n_7 ; wire \br_corr_cnt_reg[20]_i_1_n_0 ; wire \br_corr_cnt_reg[20]_i_1_n_1 ; wire \br_corr_cnt_reg[20]_i_1_n_2 ; wire \br_corr_cnt_reg[20]_i_1_n_3 ; wire \br_corr_cnt_reg[20]_i_1_n_4 ; wire \br_corr_cnt_reg[20]_i_1_n_5 ; wire \br_corr_cnt_reg[20]_i_1_n_6 ; wire \br_corr_cnt_reg[20]_i_1_n_7 ; wire \br_corr_cnt_reg[24]_i_1_n_0 ; wire \br_corr_cnt_reg[24]_i_1_n_1 ; wire \br_corr_cnt_reg[24]_i_1_n_2 ; wire \br_corr_cnt_reg[24]_i_1_n_3 ; wire \br_corr_cnt_reg[24]_i_1_n_4 ; wire \br_corr_cnt_reg[24]_i_1_n_5 ; wire \br_corr_cnt_reg[24]_i_1_n_6 ; wire \br_corr_cnt_reg[24]_i_1_n_7 ; wire \br_corr_cnt_reg[28]_i_1_n_1 ; wire \br_corr_cnt_reg[28]_i_1_n_2 ; wire \br_corr_cnt_reg[28]_i_1_n_3 ; wire \br_corr_cnt_reg[28]_i_1_n_4 ; wire \br_corr_cnt_reg[28]_i_1_n_5 ; wire \br_corr_cnt_reg[28]_i_1_n_6 ; wire \br_corr_cnt_reg[28]_i_1_n_7 ; wire \br_corr_cnt_reg[4]_i_1_n_0 ; wire \br_corr_cnt_reg[4]_i_1_n_1 ; wire \br_corr_cnt_reg[4]_i_1_n_2 ; wire \br_corr_cnt_reg[4]_i_1_n_3 ; wire \br_corr_cnt_reg[4]_i_1_n_4 ; wire \br_corr_cnt_reg[4]_i_1_n_5 ; wire \br_corr_cnt_reg[4]_i_1_n_6 ; wire \br_corr_cnt_reg[4]_i_1_n_7 ; wire \br_corr_cnt_reg[8]_i_1_n_0 ; wire \br_corr_cnt_reg[8]_i_1_n_1 ; wire \br_corr_cnt_reg[8]_i_1_n_2 ; wire \br_corr_cnt_reg[8]_i_1_n_3 ; wire \br_corr_cnt_reg[8]_i_1_n_4 ; wire \br_corr_cnt_reg[8]_i_1_n_5 ; wire \br_corr_cnt_reg[8]_i_1_n_6 ; wire \br_corr_cnt_reg[8]_i_1_n_7 ; wire br_inst_cnt; wire \br_inst_cnt[0]_i_4_n_0 ; wire [31:0]br_inst_cnt_reg; wire \br_inst_cnt_reg[0]_i_2_n_0 ; wire \br_inst_cnt_reg[0]_i_2_n_1 ; wire \br_inst_cnt_reg[0]_i_2_n_2 ; wire \br_inst_cnt_reg[0]_i_2_n_3 ; wire \br_inst_cnt_reg[0]_i_2_n_4 ; wire \br_inst_cnt_reg[0]_i_2_n_5 ; wire \br_inst_cnt_reg[0]_i_2_n_6 ; wire \br_inst_cnt_reg[0]_i_2_n_7 ; wire \br_inst_cnt_reg[12]_i_1_n_0 ; wire \br_inst_cnt_reg[12]_i_1_n_1 ; wire \br_inst_cnt_reg[12]_i_1_n_2 ; wire \br_inst_cnt_reg[12]_i_1_n_3 ; wire \br_inst_cnt_reg[12]_i_1_n_4 ; wire \br_inst_cnt_reg[12]_i_1_n_5 ; wire \br_inst_cnt_reg[12]_i_1_n_6 ; wire \br_inst_cnt_reg[12]_i_1_n_7 ; wire \br_inst_cnt_reg[16]_i_1_n_0 ; wire \br_inst_cnt_reg[16]_i_1_n_1 ; wire \br_inst_cnt_reg[16]_i_1_n_2 ; wire \br_inst_cnt_reg[16]_i_1_n_3 ; wire \br_inst_cnt_reg[16]_i_1_n_4 ; wire \br_inst_cnt_reg[16]_i_1_n_5 ; wire \br_inst_cnt_reg[16]_i_1_n_6 ; wire \br_inst_cnt_reg[16]_i_1_n_7 ; wire \br_inst_cnt_reg[20]_i_1_n_0 ; wire \br_inst_cnt_reg[20]_i_1_n_1 ; wire \br_inst_cnt_reg[20]_i_1_n_2 ; wire \br_inst_cnt_reg[20]_i_1_n_3 ; wire \br_inst_cnt_reg[20]_i_1_n_4 ; wire \br_inst_cnt_reg[20]_i_1_n_5 ; wire \br_inst_cnt_reg[20]_i_1_n_6 ; wire \br_inst_cnt_reg[20]_i_1_n_7 ; wire \br_inst_cnt_reg[24]_i_1_n_0 ; wire \br_inst_cnt_reg[24]_i_1_n_1 ; wire \br_inst_cnt_reg[24]_i_1_n_2 ; wire \br_inst_cnt_reg[24]_i_1_n_3 ; wire \br_inst_cnt_reg[24]_i_1_n_4 ; wire \br_inst_cnt_reg[24]_i_1_n_5 ; wire \br_inst_cnt_reg[24]_i_1_n_6 ; wire \br_inst_cnt_reg[24]_i_1_n_7 ; wire \br_inst_cnt_reg[28]_i_1_n_1 ; wire \br_inst_cnt_reg[28]_i_1_n_2 ; wire \br_inst_cnt_reg[28]_i_1_n_3 ; wire \br_inst_cnt_reg[28]_i_1_n_4 ; wire \br_inst_cnt_reg[28]_i_1_n_5 ; wire \br_inst_cnt_reg[28]_i_1_n_6 ; wire \br_inst_cnt_reg[28]_i_1_n_7 ; wire \br_inst_cnt_reg[4]_i_1_n_0 ; wire \br_inst_cnt_reg[4]_i_1_n_1 ; wire \br_inst_cnt_reg[4]_i_1_n_2 ; wire \br_inst_cnt_reg[4]_i_1_n_3 ; wire \br_inst_cnt_reg[4]_i_1_n_4 ; wire \br_inst_cnt_reg[4]_i_1_n_5 ; wire \br_inst_cnt_reg[4]_i_1_n_6 ; wire \br_inst_cnt_reg[4]_i_1_n_7 ; wire \br_inst_cnt_reg[8]_i_1_n_0 ; wire \br_inst_cnt_reg[8]_i_1_n_1 ; wire \br_inst_cnt_reg[8]_i_1_n_2 ; wire \br_inst_cnt_reg[8]_i_1_n_3 ; wire \br_inst_cnt_reg[8]_i_1_n_4 ; wire \br_inst_cnt_reg[8]_i_1_n_5 ; wire \br_inst_cnt_reg[8]_i_1_n_6 ; wire \br_inst_cnt_reg[8]_i_1_n_7 ; wire br_pred_n_100; wire br_pred_n_101; wire br_pred_n_102; wire br_pred_n_103; wire br_pred_n_104; wire br_pred_n_105; wire br_pred_n_106; wire br_pred_n_107; wire br_pred_n_108; wire br_pred_n_109; wire br_pred_n_110; wire br_pred_n_111; wire br_pred_n_112; wire br_pred_n_113; wire br_pred_n_114; wire br_pred_n_115; wire br_pred_n_116; wire br_pred_n_117; wire br_pred_n_118; wire br_pred_n_119; wire br_pred_n_120; wire br_pred_n_121; wire br_pred_n_122; wire br_pred_n_123; wire br_pred_n_124; wire br_pred_n_125; wire br_pred_n_126; wire br_pred_n_127; wire br_pred_n_128; wire br_pred_n_129; wire br_pred_n_130; wire br_pred_n_131; wire br_pred_n_132; wire br_pred_n_133; wire br_pred_n_134; wire br_pred_n_135; wire br_pred_n_136; wire br_pred_n_137; wire br_pred_n_138; wire br_pred_n_139; wire br_pred_n_140; wire br_pred_n_141; wire br_pred_n_142; wire br_pred_n_143; wire br_pred_n_144; wire br_pred_n_145; wire br_pred_n_146; wire br_pred_n_147; wire br_pred_n_148; wire br_pred_n_149; wire br_pred_n_150; wire br_pred_n_151; wire br_pred_n_152; wire br_pred_n_153; wire br_pred_n_154; wire br_pred_n_155; wire br_pred_n_156; wire br_pred_n_157; wire br_pred_n_158; wire br_pred_n_159; wire br_pred_n_160; wire br_pred_n_163; wire br_pred_n_30; wire br_pred_n_31; wire br_pred_n_32; wire br_pred_n_33; wire br_pred_n_34; wire br_pred_n_35; wire br_pred_n_36; wire br_pred_n_47; wire br_pred_n_48; wire br_pred_n_49; wire br_pred_n_50; wire br_pred_n_51; wire br_pred_n_52; wire br_pred_n_53; wire br_pred_n_54; wire br_pred_n_55; wire br_pred_n_56; wire br_pred_n_57; wire br_pred_n_58; wire br_pred_n_59; wire br_pred_n_60; wire br_pred_n_61; wire br_pred_n_62; wire br_pred_n_63; wire br_pred_n_64; wire br_pred_n_65; wire br_pred_n_66; wire br_pred_n_67; wire br_pred_n_68; wire br_pred_n_69; wire br_pred_n_70; wire br_pred_n_71; wire br_pred_n_72; wire br_pred_n_73; wire br_pred_n_74; wire br_pred_n_75; wire br_pred_n_76; wire br_pred_n_77; wire br_pred_n_78; wire br_pred_n_79; wire br_pred_n_80; wire br_pred_n_81; wire br_pred_n_82; wire br_pred_n_83; wire br_pred_n_84; wire br_pred_n_85; wire br_pred_n_86; wire br_pred_n_87; wire br_pred_n_88; wire br_pred_n_89; wire br_pred_n_90; wire br_pred_n_91; wire br_pred_n_92; wire br_pred_n_93; wire br_pred_n_94; wire br_pred_n_95; wire br_pred_n_96; wire br_pred_n_97; wire br_pred_n_98; wire br_pred_n_99; wire br_pred_taken; wire buttons_pressed; wire cnt_reset; wire cpu_clk; wire cpu_clk_locked; wire cpu_reset; wire \cycle_cnt[0]_i_8_n_0 ; wire [31:0]cycle_cnt_reg; wire \cycle_cnt_reg[0]_i_2_n_0 ; wire \cycle_cnt_reg[0]_i_2_n_1 ; wire \cycle_cnt_reg[0]_i_2_n_2 ; wire \cycle_cnt_reg[0]_i_2_n_3 ; wire \cycle_cnt_reg[0]_i_2_n_4 ; wire \cycle_cnt_reg[0]_i_2_n_5 ; wire \cycle_cnt_reg[0]_i_2_n_6 ; wire \cycle_cnt_reg[0]_i_2_n_7 ; wire \cycle_cnt_reg[12]_i_1_n_0 ; wire \cycle_cnt_reg[12]_i_1_n_1 ; wire \cycle_cnt_reg[12]_i_1_n_2 ; wire \cycle_cnt_reg[12]_i_1_n_3 ; wire \cycle_cnt_reg[12]_i_1_n_4 ; wire \cycle_cnt_reg[12]_i_1_n_5 ; wire \cycle_cnt_reg[12]_i_1_n_6 ; wire \cycle_cnt_reg[12]_i_1_n_7 ; wire \cycle_cnt_reg[16]_i_1_n_0 ; wire \cycle_cnt_reg[16]_i_1_n_1 ; wire \cycle_cnt_reg[16]_i_1_n_2 ; wire \cycle_cnt_reg[16]_i_1_n_3 ; wire \cycle_cnt_reg[16]_i_1_n_4 ; wire \cycle_cnt_reg[16]_i_1_n_5 ; wire \cycle_cnt_reg[16]_i_1_n_6 ; wire \cycle_cnt_reg[16]_i_1_n_7 ; wire \cycle_cnt_reg[20]_i_1_n_0 ; wire \cycle_cnt_reg[20]_i_1_n_1 ; wire \cycle_cnt_reg[20]_i_1_n_2 ; wire \cycle_cnt_reg[20]_i_1_n_3 ; wire \cycle_cnt_reg[20]_i_1_n_4 ; wire \cycle_cnt_reg[20]_i_1_n_5 ; wire \cycle_cnt_reg[20]_i_1_n_6 ; wire \cycle_cnt_reg[20]_i_1_n_7 ; wire \cycle_cnt_reg[24]_i_1_n_0 ; wire \cycle_cnt_reg[24]_i_1_n_1 ; wire \cycle_cnt_reg[24]_i_1_n_2 ; wire \cycle_cnt_reg[24]_i_1_n_3 ; wire \cycle_cnt_reg[24]_i_1_n_4 ; wire \cycle_cnt_reg[24]_i_1_n_5 ; wire \cycle_cnt_reg[24]_i_1_n_6 ; wire \cycle_cnt_reg[24]_i_1_n_7 ; wire \cycle_cnt_reg[28]_i_1_n_1 ; wire \cycle_cnt_reg[28]_i_1_n_2 ; wire \cycle_cnt_reg[28]_i_1_n_3 ; wire \cycle_cnt_reg[28]_i_1_n_4 ; wire \cycle_cnt_reg[28]_i_1_n_5 ; wire \cycle_cnt_reg[28]_i_1_n_6 ; wire \cycle_cnt_reg[28]_i_1_n_7 ; wire \cycle_cnt_reg[4]_i_1_n_0 ; wire \cycle_cnt_reg[4]_i_1_n_1 ; wire \cycle_cnt_reg[4]_i_1_n_2 ; wire \cycle_cnt_reg[4]_i_1_n_3 ; wire \cycle_cnt_reg[4]_i_1_n_4 ; wire \cycle_cnt_reg[4]_i_1_n_5 ; wire \cycle_cnt_reg[4]_i_1_n_6 ; wire \cycle_cnt_reg[4]_i_1_n_7 ; wire \cycle_cnt_reg[8]_i_1_n_0 ; wire \cycle_cnt_reg[8]_i_1_n_1 ; wire \cycle_cnt_reg[8]_i_1_n_2 ; wire \cycle_cnt_reg[8]_i_1_n_3 ; wire \cycle_cnt_reg[8]_i_1_n_4 ; wire \cycle_cnt_reg[8]_i_1_n_5 ; wire \cycle_cnt_reg[8]_i_1_n_6 ; wire \cycle_cnt_reg[8]_i_1_n_7 ; wire [31:1]data2; wire [31:1]data3; wire [31:0]dmem_din; wire [31:0]dmem_dout; wire dmem_n_0; wire dmem_n_1; wire dmem_n_13; wire dmem_n_14; wire dmem_n_15; wire dmem_n_16; wire dmem_n_17; wire dmem_n_18; wire dmem_n_2; wire dmem_n_3; wire dmem_n_6; wire dmem_n_7; wire dmem_n_8; wire dmem_n_9; wire [3:0]dmem_we; wire [31:0]douta_reg; wire [31:0]doutb_reg; wire [31:0]ex_alu; wire ex_flush; wire \ex_wb_inst_reg_n_0_[0] ; wire \ex_wb_inst_reg_n_0_[12] ; wire \ex_wb_inst_reg_n_0_[13] ; wire \ex_wb_inst_reg_n_0_[14] ; wire \ex_wb_inst_reg_n_0_[15] ; wire \ex_wb_inst_reg_n_0_[16] ; wire \ex_wb_inst_reg_n_0_[17] ; wire \ex_wb_inst_reg_n_0_[18] ; wire \ex_wb_inst_reg_n_0_[19] ; wire \ex_wb_inst_reg_n_0_[1] ; wire \ex_wb_inst_reg_n_0_[20] ; wire \ex_wb_inst_reg_n_0_[21] ; wire \ex_wb_inst_reg_n_0_[22] ; wire \ex_wb_inst_reg_n_0_[23] ; wire \ex_wb_inst_reg_n_0_[24] ; wire \ex_wb_inst_reg_n_0_[25] ; wire \ex_wb_inst_reg_n_0_[26] ; wire \ex_wb_inst_reg_n_0_[27] ; wire \ex_wb_inst_reg_n_0_[28] ; wire \ex_wb_inst_reg_n_0_[29] ; wire \ex_wb_inst_reg_n_0_[30] ; wire \ex_wb_inst_reg_n_0_[31] ; wire [31:0]ex_wb_pc; wire ex_wb_pc0; wire [31:0]f_ex_imm; wire [30:0]f_ex_inst; wire \f_ex_pc_reg_n_0_[0] ; wire \f_ex_pc_reg_n_0_[10] ; wire \f_ex_pc_reg_n_0_[11] ; wire \f_ex_pc_reg_n_0_[12] ; wire \f_ex_pc_reg_n_0_[13] ; wire \f_ex_pc_reg_n_0_[14] ; wire \f_ex_pc_reg_n_0_[15] ; wire \f_ex_pc_reg_n_0_[16] ; wire \f_ex_pc_reg_n_0_[17] ; wire \f_ex_pc_reg_n_0_[18] ; wire \f_ex_pc_reg_n_0_[19] ; wire \f_ex_pc_reg_n_0_[1] ; wire \f_ex_pc_reg_n_0_[20] ; wire \f_ex_pc_reg_n_0_[21] ; wire \f_ex_pc_reg_n_0_[22] ; wire \f_ex_pc_reg_n_0_[23] ; wire \f_ex_pc_reg_n_0_[24] ; wire \f_ex_pc_reg_n_0_[25] ; wire \f_ex_pc_reg_n_0_[26] ; wire \f_ex_pc_reg_n_0_[27] ; wire \f_ex_pc_reg_n_0_[28] ; wire \f_ex_pc_reg_n_0_[29] ; wire \f_ex_pc_reg_n_0_[2] ; wire \f_ex_pc_reg_n_0_[31] ; wire \f_ex_pc_reg_n_0_[3] ; wire \f_ex_pc_reg_n_0_[4] ; wire \f_ex_pc_reg_n_0_[5] ; wire \f_ex_pc_reg_n_0_[6] ; wire \f_ex_pc_reg_n_0_[7] ; wire \f_ex_pc_reg_n_0_[8] ; wire \f_ex_pc_reg_n_0_[9] ; wire [31:0]f_ex_rd1; wire [31:0]f_ex_rd2; wire [31:31]fwd_b; wire [31:0]imem_doutb; wire imem_ena; wire imem_n_0; wire imem_n_1; wire imem_n_10; wire imem_n_101; wire imem_n_102; wire imem_n_103; wire imem_n_104; wire imem_n_105; wire imem_n_106; wire imem_n_107; wire imem_n_108; wire imem_n_109; wire imem_n_11; wire imem_n_110; wire imem_n_111; wire imem_n_112; wire imem_n_113; wire imem_n_114; wire imem_n_115; wire imem_n_116; wire imem_n_117; wire imem_n_118; wire imem_n_119; wire imem_n_12; wire imem_n_120; wire imem_n_121; wire imem_n_122; wire imem_n_123; wire imem_n_124; wire imem_n_125; wire imem_n_126; wire imem_n_127; wire imem_n_128; wire imem_n_129; wire imem_n_13; wire imem_n_130; wire imem_n_131; wire imem_n_132; wire imem_n_133; wire imem_n_134; wire imem_n_135; wire imem_n_136; wire imem_n_137; wire imem_n_138; wire imem_n_139; wire imem_n_14; wire imem_n_140; wire imem_n_141; wire imem_n_142; wire imem_n_143; wire imem_n_144; wire imem_n_145; wire imem_n_146; wire imem_n_147; wire imem_n_148; wire imem_n_149; wire imem_n_15; wire imem_n_16; wire imem_n_166; wire imem_n_167; wire imem_n_168; wire imem_n_169; wire imem_n_17; wire imem_n_170; wire imem_n_171; wire imem_n_172; wire imem_n_173; wire imem_n_174; wire imem_n_175; wire imem_n_176; wire imem_n_177; wire imem_n_178; wire imem_n_179; wire imem_n_18; wire imem_n_180; wire imem_n_181; wire imem_n_182; wire imem_n_183; wire imem_n_184; wire imem_n_185; wire imem_n_19; wire imem_n_20; wire imem_n_21; wire imem_n_22; wire imem_n_23; wire imem_n_24; wire imem_n_25; wire imem_n_26; wire imem_n_27; wire imem_n_28; wire imem_n_29; wire imem_n_30; wire imem_n_31; wire imem_n_32; wire imem_n_33; wire imem_n_34; wire imem_n_35; wire imem_n_36; wire imem_n_37; wire imem_n_38; wire imem_n_39; wire imem_n_40; wire imem_n_41; wire imem_n_42; wire imem_n_43; wire imem_n_44; wire imem_n_48; wire imem_n_5; wire imem_n_51; wire imem_n_52; wire imem_n_53; wire imem_n_54; wire imem_n_55; wire imem_n_56; wire imem_n_57; wire imem_n_58; wire imem_n_59; wire imem_n_6; wire imem_n_60; wire imem_n_61; wire imem_n_62; wire imem_n_63; wire imem_n_64; wire imem_n_65; wire imem_n_66; wire imem_n_67; wire imem_n_68; wire imem_n_69; wire imem_n_7; wire imem_n_70; wire imem_n_71; wire imem_n_72; wire imem_n_73; wire imem_n_74; wire imem_n_75; wire imem_n_76; wire imem_n_77; wire imem_n_78; wire imem_n_79; wire imem_n_8; wire imem_n_80; wire imem_n_81; wire imem_n_83; wire imem_n_84; wire imem_n_9; wire [3:0]imem_wea; wire [30:1]imm; wire \insts_cnt[0]_i_10_n_0 ; wire \insts_cnt[0]_i_11_n_0 ; wire \insts_cnt[0]_i_1_n_0 ; wire \insts_cnt[0]_i_3_n_0 ; wire \insts_cnt[0]_i_4_n_0 ; wire \insts_cnt[0]_i_5_n_0 ; wire \insts_cnt[0]_i_6_n_0 ; wire \insts_cnt[0]_i_7_n_0 ; wire \insts_cnt[0]_i_8_n_0 ; wire \insts_cnt[0]_i_9_n_0 ; wire [31:0]insts_cnt_reg; wire \insts_cnt_reg[0]_i_2_n_0 ; wire \insts_cnt_reg[0]_i_2_n_1 ; wire \insts_cnt_reg[0]_i_2_n_2 ; wire \insts_cnt_reg[0]_i_2_n_3 ; wire \insts_cnt_reg[0]_i_2_n_4 ; wire \insts_cnt_reg[0]_i_2_n_5 ; wire \insts_cnt_reg[0]_i_2_n_6 ; wire \insts_cnt_reg[0]_i_2_n_7 ; wire \insts_cnt_reg[12]_i_1_n_0 ; wire \insts_cnt_reg[12]_i_1_n_1 ; wire \insts_cnt_reg[12]_i_1_n_2 ; wire \insts_cnt_reg[12]_i_1_n_3 ; wire \insts_cnt_reg[12]_i_1_n_4 ; wire \insts_cnt_reg[12]_i_1_n_5 ; wire \insts_cnt_reg[12]_i_1_n_6 ; wire \insts_cnt_reg[12]_i_1_n_7 ; wire \insts_cnt_reg[16]_i_1_n_0 ; wire \insts_cnt_reg[16]_i_1_n_1 ; wire \insts_cnt_reg[16]_i_1_n_2 ; wire \insts_cnt_reg[16]_i_1_n_3 ; wire \insts_cnt_reg[16]_i_1_n_4 ; wire \insts_cnt_reg[16]_i_1_n_5 ; wire \insts_cnt_reg[16]_i_1_n_6 ; wire \insts_cnt_reg[16]_i_1_n_7 ; wire \insts_cnt_reg[20]_i_1_n_0 ; wire \insts_cnt_reg[20]_i_1_n_1 ; wire \insts_cnt_reg[20]_i_1_n_2 ; wire \insts_cnt_reg[20]_i_1_n_3 ; wire \insts_cnt_reg[20]_i_1_n_4 ; wire \insts_cnt_reg[20]_i_1_n_5 ; wire \insts_cnt_reg[20]_i_1_n_6 ; wire \insts_cnt_reg[20]_i_1_n_7 ; wire \insts_cnt_reg[24]_i_1_n_0 ; wire \insts_cnt_reg[24]_i_1_n_1 ; wire \insts_cnt_reg[24]_i_1_n_2 ; wire \insts_cnt_reg[24]_i_1_n_3 ; wire \insts_cnt_reg[24]_i_1_n_4 ; wire \insts_cnt_reg[24]_i_1_n_5 ; wire \insts_cnt_reg[24]_i_1_n_6 ; wire \insts_cnt_reg[24]_i_1_n_7 ; wire \insts_cnt_reg[28]_i_1_n_1 ; wire \insts_cnt_reg[28]_i_1_n_2 ; wire \insts_cnt_reg[28]_i_1_n_3 ; wire \insts_cnt_reg[28]_i_1_n_4 ; wire \insts_cnt_reg[28]_i_1_n_5 ; wire \insts_cnt_reg[28]_i_1_n_6 ; wire \insts_cnt_reg[28]_i_1_n_7 ; wire \insts_cnt_reg[4]_i_1_n_0 ; wire \insts_cnt_reg[4]_i_1_n_1 ; wire \insts_cnt_reg[4]_i_1_n_2 ; wire \insts_cnt_reg[4]_i_1_n_3 ; wire \insts_cnt_reg[4]_i_1_n_4 ; wire \insts_cnt_reg[4]_i_1_n_5 ; wire \insts_cnt_reg[4]_i_1_n_6 ; wire \insts_cnt_reg[4]_i_1_n_7 ; wire \insts_cnt_reg[8]_i_1_n_0 ; wire \insts_cnt_reg[8]_i_1_n_1 ; wire \insts_cnt_reg[8]_i_1_n_2 ; wire \insts_cnt_reg[8]_i_1_n_3 ; wire \insts_cnt_reg[8]_i_1_n_4 ; wire \insts_cnt_reg[8]_i_1_n_5 ; wire \insts_cnt_reg[8]_i_1_n_6 ; wire \insts_cnt_reg[8]_i_1_n_7 ; wire [30:0]mem_wb_mux; wire on_chip_uart_n_10; wire on_chip_uart_n_11; wire on_chip_uart_n_12; wire on_chip_uart_n_13; wire on_chip_uart_n_17; wire on_chip_uart_n_18; wire on_chip_uart_n_19; wire on_chip_uart_n_20; wire on_chip_uart_n_21; wire on_chip_uart_n_22; wire on_chip_uart_n_23; wire on_chip_uart_n_24; wire on_chip_uart_n_25; wire on_chip_uart_n_26; wire on_chip_uart_n_27; wire on_chip_uart_n_28; wire on_chip_uart_n_29; wire on_chip_uart_n_30; wire on_chip_uart_n_31; wire on_chip_uart_n_32; wire on_chip_uart_n_33; wire on_chip_uart_n_37; wire on_chip_uart_n_38; wire on_chip_uart_n_39; wire on_chip_uart_n_40; wire on_chip_uart_n_41; wire on_chip_uart_n_42; wire on_chip_uart_n_43; wire on_chip_uart_n_44; wire on_chip_uart_n_45; wire on_chip_uart_n_46; wire on_chip_uart_n_47; wire on_chip_uart_n_48; wire on_chip_uart_n_8; wire on_chip_uart_n_9; wire [4:0]p_0_in; wire p_0_in10_in; wire p_1_in; wire [7:1]p_1_in_0; wire p_2_in; wire [31:0]pc; wire [31:0]pprev_data; wire [11:2]pprev_inst; wire [4:0]ra1; wire [4:0]ra2; wire [31:0]rd10; wire [31:0]rd20; wire rf_n_100; wire rf_n_101; wire rf_n_102; wire rf_n_118; wire rf_n_119; wire rf_n_120; wire rf_n_121; wire rf_n_122; wire rf_n_123; wire rf_n_124; wire rf_n_125; wire rf_n_126; wire rf_n_127; wire rf_n_128; wire rf_n_129; wire rf_n_130; wire rf_n_131; wire rf_n_132; wire rf_n_133; wire rf_n_65; wire rf_n_66; wire rf_n_67; wire rf_n_68; wire rf_n_69; wire rf_n_70; wire rf_n_86; wire rf_n_87; wire rf_n_88; wire rf_n_89; wire rf_n_90; wire rf_n_91; wire rf_n_92; wire rf_n_93; wire rf_n_94; wire rf_n_95; wire rf_n_96; wire rf_n_97; wire rf_n_98; wire rf_n_99; wire serial_in; wire serial_out; wire [8:2]tx_shift; wire \uatransmit/start ; wire \uatransmit/symbol_edge__7 ; wire \uatransmit/tx_running__2 ; wire [4:0]wa; wire wb_BrEq; wire wb_BrLt; wire \wb_alu_reg_n_0_[0] ; wire \wb_alu_reg_n_0_[10] ; wire \wb_alu_reg_n_0_[11] ; wire \wb_alu_reg_n_0_[12] ; wire \wb_alu_reg_n_0_[13] ; wire \wb_alu_reg_n_0_[14] ; wire \wb_alu_reg_n_0_[15] ; wire \wb_alu_reg_n_0_[16] ; wire \wb_alu_reg_n_0_[17] ; wire \wb_alu_reg_n_0_[18] ; wire \wb_alu_reg_n_0_[19] ; wire \wb_alu_reg_n_0_[1] ; wire \wb_alu_reg_n_0_[20] ; wire \wb_alu_reg_n_0_[21] ; wire \wb_alu_reg_n_0_[22] ; wire \wb_alu_reg_n_0_[23] ; wire \wb_alu_reg_n_0_[24] ; wire \wb_alu_reg_n_0_[25] ; wire \wb_alu_reg_n_0_[26] ; wire \wb_alu_reg_n_0_[27] ; wire \wb_alu_reg_n_0_[29] ; wire \wb_alu_reg_n_0_[2] ; wire \wb_alu_reg_n_0_[3] ; wire \wb_alu_reg_n_0_[4] ; wire \wb_alu_reg_n_0_[5] ; wire \wb_alu_reg_n_0_[6] ; wire \wb_alu_reg_n_0_[7] ; wire \wb_alu_reg_n_0_[8] ; wire \wb_alu_reg_n_0_[9] ; wire wb_br_taken; wire wb_br_taken_i_3_n_0; wire [31:0]wb_mux; wire we; GND GND (.G(\<const0> )); VCC VCC (.P(\<const1> )); bios_mem bios_mem (.ADDRARDADDR({bios_mem_n_178,bios_mem_n_179,bios_mem_n_180,bios_mem_n_181,bios_mem_n_182,bios_mem_n_183,bios_mem_n_184,bios_mem_n_185,bios_mem_n_186,bios_mem_n_187,bios_mem_n_188,bios_mem_n_189,bios_mem_n_190,bios_mem_n_191}), .ALUSel(ALUSel), .ASel(ASel), .BSel(BSel), .BrLt(BrLt), .CO(bios_mem_n_198), .DI(dmem_n_8), .MemRW({MemRW[3],MemRW[1:0]}), .Q(f_ex_imm[30:0]), .S(dmem_n_18), .SR(bios_mem_n_118), .addr({bios_mem_n_196,bios_mem_n_197}), .addra({bios_mem_n_192,bios_mem_n_193}), .\bit_counter[3]_i_11_0 (on_chip_uart_n_27), .\bit_counter[3]_i_11_1 (dmem_n_14), .\bit_counter[3]_i_12_0 (dmem_n_17), .\bit_counter[3]_i_12_1 (on_chip_uart_n_11), .\bit_counter[3]_i_12_2 (on_chip_uart_n_10), .\bit_counter[3]_i_15_0 (on_chip_uart_n_28), .\bit_counter[3]_i_15_1 (on_chip_uart_n_9), .\bit_counter[3]_i_16_0 (on_chip_uart_n_8), .\bit_counter[3]_i_17_0 (on_chip_uart_n_13), .\bit_counter[3]_i_17_1 (dmem_n_15), .\bit_counter[3]_i_4_0 (imem_n_119), .\bit_counter[3]_i_5_0 (dmem_n_13), .\bit_counter[3]_i_5_1 (on_chip_uart_n_12), .\br_inst_cnt_reg[0] (br_pred_n_127), .\br_inst_cnt_reg[0]_0 (br_pred_n_160), .buttons_pressed(buttons_pressed), .\clock_counter_reg[0] (bios_mem_n_116), .cnt_reset(cnt_reset), .cpu_clk(cpu_clk), .cpu_clk_locked(cpu_clk_locked), .dmem_we(dmem_we), .dout(dmem_dout), .douta_reg_0_0(bios_mem_n_126), .douta_reg_0_1(bios_mem_n_204), .douta_reg_0_2(imem_n_1), .douta_reg_0_3(imem_n_78), .douta_reg_0_4(imem_n_10), .douta_reg_0_5(imem_n_8), .douta_reg_0_6(imem_n_7), .douta_reg_0_7(imem_n_79), .douta_reg_0_8(imem_n_11), .douta_reg_0_9(imem_n_9), .douta_reg_1_0({doutb_reg[31:15],doutb_reg[7],doutb_reg[1:0]}), .douta_reg_1_1(imem_n_12), .doutb({imem_doutb[6:5],imem_doutb[1]}), .ex_alu(ex_alu[30:0]), .\ex_wb_inst_reg[12] (bios_mem_n_36), .\f_ex_imm_reg[16] ({b_mux[16],b_mux[4:3]}), .\f_ex_imm_reg[4] (bios_mem_n_3), .\f_ex_imm_reg[4]_0 (bios_mem_n_4), .\f_ex_inst_reg[12] (bios_mem_n_177), .\f_ex_inst_reg[2] ({bios_mem_n_194,bios_mem_n_195}), .\f_ex_pc_reg[30] ({\alu/data0 [31:30],\alu/data0 [23:20],\alu/data0 [7:6]}), .\f_ex_pc_reg[30]_0 ({\alu/data8 [31],\alu/data8 [29:24],\alu/data8 [15:10],\alu/data8 [7:6],\alu/data8 [4],\alu/data8 [2:1]}), .imem_wea(imem_wea), .mem_reg_0_0_i_224_0(on_chip_uart_n_38), .mem_reg_0_0_i_224_1(imem_n_127), .mem_reg_0_0_i_227_0(on_chip_uart_n_37), .mem_reg_0_0_i_227_1(imem_n_124), .mem_reg_0_1_i_5_0(on_chip_uart_n_47), .mem_reg_0_1_i_5_1(imem_n_131), .mem_reg_0_1_i_7_0(on_chip_uart_n_46), .mem_reg_0_1_i_7_1(imem_n_130), .mem_reg_0_2_i_7_0(on_chip_uart_n_48), .mem_reg_0_2_i_7_1(imem_n_132), .mem_reg_1_0(imem_n_77), .mem_reg_1_0_0(imem_n_44), .mem_reg_1_0_1(imem_n_43), .mem_reg_1_0_2(imem_n_36), .mem_reg_1_0_3(imem_n_35), .mem_reg_1_1(imem_n_42), .mem_reg_1_1_0(imem_n_41), .mem_reg_1_1_1(imem_n_34), .mem_reg_1_1_2(imem_n_33), .mem_reg_1_2(imem_n_40), .mem_reg_1_2_0(imem_n_39), .mem_reg_1_2_1(imem_n_32), .mem_reg_1_2_2(imem_n_31), .mem_reg_1_3(imem_n_38), .mem_reg_1_3_0(imem_n_37), .mem_reg_1_3_1(imem_n_30), .mem_reg_1_3_2(imem_n_29), .mem_reg_1_3_3(imem_n_51), .mem_reg_2_0({f_ex_inst[14:12],f_ex_inst[6],f_ex_inst[3]}), .mem_reg_2_0_i_13_0(imem_n_27), .mem_reg_2_0_i_14_0(imem_n_28), .mem_reg_2_1_i_3_0(imem_n_25), .mem_reg_2_1_i_4_0(imem_n_26), .mem_reg_2_2(dmem_n_2), .mem_reg_2_2_i_5_0(imem_n_23), .mem_reg_2_2_i_6_0(imem_n_24), .mem_reg_2_3(ex_alu[31]), .mem_reg_2_3_i_3_0(imem_n_21), .mem_reg_2_3_i_4_0(imem_n_22), .mem_reg_3_0(imem_n_20), .mem_reg_3_0_0(imem_n_19), .mem_reg_3_0_1(imem_n_81), .mem_reg_3_1(imem_n_18), .mem_reg_3_1_0(imem_n_17), .mem_reg_3_2(imem_n_16), .mem_reg_3_2_0(imem_n_15), .mem_reg_3_3(fwd_b), .mem_reg_3_3_0(imem_n_14), .mem_reg_3_3_1(dmem_n_1), .mem_reg_3_3_2(imem_n_5), .mem_reg_3_3_3(imem_n_6), .mem_reg_3_3_4(imem_n_185), .mem_reg_3_3_5(imem_n_48), .mem_reg_r1_0_31_0_5_i_22_0(imem_n_133), .mem_reg_r1_0_31_12_17_i_11_0(imem_n_139), .mem_reg_r1_0_31_12_17_i_17_0(imem_n_141), .mem_reg_r1_0_31_12_17_i_19_0(imem_n_144), .mem_reg_r1_0_31_12_17_i_21_0(imem_n_143), .mem_reg_r1_0_31_12_17_i_8_0(imem_n_140), .mem_reg_r1_0_31_18_23_i_11_0(imem_n_148), .mem_reg_r1_0_31_18_23_i_13_0(imem_n_147), .mem_reg_r1_0_31_18_23_i_15_0(imem_n_120), .mem_reg_r1_0_31_18_23_i_15_1(imem_n_142), .mem_reg_r1_0_31_18_23_i_15_2(rf_n_98), .mem_reg_r1_0_31_18_23_i_17_0(rf_n_97), .mem_reg_r1_0_31_18_23_i_7_0(imem_n_146), .mem_reg_r1_0_31_18_23_i_9_0(imem_n_145), .mem_reg_r1_0_31_6_11_i_12_0(imem_n_136), .mem_reg_r1_0_31_6_11_i_15_0(imem_n_135), .mem_reg_r1_0_31_6_11_i_15_1(rf_n_96), .mem_reg_r1_0_31_6_11_i_18_0(imem_n_138), .mem_reg_r1_0_31_6_11_i_21_0(imem_n_137), .mem_reg_r1_0_31_6_11_i_23_0({p_2_in,p_1_in,\wb_alu_reg_n_0_[29] ,p_0_in10_in,\wb_alu_reg_n_0_[1] ,\wb_alu_reg_n_0_[0] }), .mem_reg_r1_0_31_6_11_i_9_0(imem_n_134), .mem_wb_mux({mem_wb_mux[30:16],mem_wb_mux[7],mem_wb_mux[1:0]}), .out(douta_reg), .p_1_in(dmem_din), .p_1_in_0(p_1_in_0), .\pprev_data[31]_i_2 (on_chip_uart_n_44), .\pprev_data_reg[0] (imem_n_117), .\pprev_data_reg[0]_0 (rf_n_65), .\pprev_data_reg[0]_1 ({\ex_wb_inst_reg_n_0_[14] ,\ex_wb_inst_reg_n_0_[13] ,\ex_wb_inst_reg_n_0_[12] }), .\pprev_data_reg[10] (imem_n_105), .\pprev_data_reg[11] (imem_n_106), .\pprev_data_reg[12] (imem_n_107), .\pprev_data_reg[13] (imem_n_108), .\pprev_data_reg[14] (imem_n_109), .\pprev_data_reg[15] (imem_n_110), .\pprev_data_reg[16] (imem_n_111), .\pprev_data_reg[17] (imem_n_112), .\pprev_data_reg[18] (imem_n_113), .\pprev_data_reg[19] (imem_n_114), .\pprev_data_reg[1] (rf_n_66), .\pprev_data_reg[20] (imem_n_115), .\pprev_data_reg[21] (imem_n_116), .\pprev_data_reg[22] (rf_n_70), .\pprev_data_reg[23] (rf_n_86), .\pprev_data_reg[24] (rf_n_87), .\pprev_data_reg[25] (rf_n_88), .\pprev_data_reg[26] (rf_n_89), .\pprev_data_reg[27] (rf_n_90), .\pprev_data_reg[28] (rf_n_91), .\pprev_data_reg[29] (rf_n_92), .\pprev_data_reg[2] (rf_n_67), .\pprev_data_reg[2]_0 (on_chip_uart_n_39), .\pprev_data_reg[30] (rf_n_93), .\pprev_data_reg[3] (rf_n_68), .\pprev_data_reg[3]_0 (on_chip_uart_n_40), .\pprev_data_reg[4] (rf_n_69), .\pprev_data_reg[4]_0 (on_chip_uart_n_41), .\pprev_data_reg[5] (on_chip_uart_n_42), .\pprev_data_reg[5]_0 (imem_n_83), .\pprev_data_reg[6] (on_chip_uart_n_43), .\pprev_data_reg[6]_0 (imem_n_101), .\pprev_data_reg[7] (on_chip_uart_n_45), .\pprev_data_reg[7]_0 (imem_n_102), .\pprev_data_reg[8] (imem_n_103), .\pprev_data_reg[9] (imem_n_104), .sel({br_pred_n_147,br_pred_n_148,br_pred_n_149,br_pred_n_150,br_pred_n_151,br_pred_n_152,br_pred_n_153,br_pred_n_154,br_pred_n_155,br_pred_n_156,br_pred_n_157}), .start(\uatransmit/start ), .symbol_edge__7(\uatransmit/symbol_edge__7 ), .tx_running__2(\uatransmit/tx_running__2 ), .tx_shift(tx_shift), .\tx_shift_reg[8] (bios_mem_n_225), .wb_BrEq_i_13_0(on_chip_uart_n_17), .wb_BrEq_i_13_1(on_chip_uart_n_18), .wb_BrEq_i_14_0(imem_n_74), .wb_BrEq_i_15_0(imem_n_70), .wb_BrEq_i_15_1(imem_n_71), .wb_BrEq_i_16_0(imem_n_68), .wb_BrEq_i_29_0(imem_n_64), .wb_BrEq_i_29_1(imem_n_65), .wb_BrEq_i_30_0(imem_n_62), .wb_BrEq_i_31_0(imem_n_58), .wb_BrEq_i_31_1(imem_n_59), .wb_BrEq_i_32_0(imem_n_56), .wb_BrEq_i_6_0(on_chip_uart_n_23), .wb_BrEq_i_6_1(on_chip_uart_n_24), .wb_BrEq_i_7_0(bios_mem_n_199), .wb_BrEq_i_7_1(on_chip_uart_n_21), .wb_BrLt_i_24_0(imem_n_75), .wb_BrLt_i_25_0(imem_n_72), .wb_BrLt_i_25_1(imem_n_73), .wb_BrLt_i_43_0(imem_n_69), .wb_BrLt_i_44_0(imem_n_66), .wb_BrLt_i_44_1(imem_n_67), .wb_BrLt_i_46_0(imem_n_63), .wb_BrLt_i_60_0(imem_n_60), .wb_BrLt_i_60_1(imem_n_61), .wb_BrLt_i_62_0(imem_n_57), .wb_BrLt_i_63_0(imem_n_52), .wb_BrLt_i_63_1(imem_n_55), .wb_BrLt_i_7_0(on_chip_uart_n_22), .wb_BrLt_i_8_0(on_chip_uart_n_19), .wb_BrLt_i_8_1(on_chip_uart_n_20), .wb_BrLt_reg(dmem_n_7), .wb_BrLt_reg_i_2_0(imem_n_76), .wb_BrLt_reg_i_2_1(on_chip_uart_n_25), .wb_BrLt_reg_i_2_2(dmem_n_3), .wb_BrLt_reg_i_3_0(dmem_n_6), .\wb_alu[20]_i_4_0 (on_chip_uart_n_32), .\wb_alu[21]_i_3_0 (on_chip_uart_n_31), .\wb_alu[22]_i_3_0 (on_chip_uart_n_30), .\wb_alu[23]_i_4_0 (on_chip_uart_n_29), .\wb_alu[28]_i_6 (dmem_n_9), .\wb_alu_reg[0] (bios_mem_n_202), .\wb_alu_reg[0]_i_18_0 (b_mux[31]), .\wb_alu_reg[0]_i_18_1 (a_mux), .\wb_alu_reg[16] (imem_n_80), .\wb_alu_reg[1] (bios_mem_n_201), .\wb_alu_reg[22] (dmem_n_16), .\wb_alu_reg[28] (dmem_n_0), .\wb_alu_reg[29] (on_chip_uart_n_33), .\wb_alu_reg[29]_0 (imem_n_0), .\wb_alu_reg[29]_i_5_0 ({imem_ena,\f_ex_pc_reg_n_0_[29] ,\f_ex_pc_reg_n_0_[28] ,\f_ex_pc_reg_n_0_[27] ,\f_ex_pc_reg_n_0_[26] ,\f_ex_pc_reg_n_0_[25] ,\f_ex_pc_reg_n_0_[24] ,\f_ex_pc_reg_n_0_[23] ,\f_ex_pc_reg_n_0_[22] ,\f_ex_pc_reg_n_0_[21] ,\f_ex_pc_reg_n_0_[20] ,\f_ex_pc_reg_n_0_[19] ,\f_ex_pc_reg_n_0_[18] ,\f_ex_pc_reg_n_0_[17] ,\f_ex_pc_reg_n_0_[16] ,\f_ex_pc_reg_n_0_[15] ,\f_ex_pc_reg_n_0_[14] ,\f_ex_pc_reg_n_0_[13] ,\f_ex_pc_reg_n_0_[12] ,\f_ex_pc_reg_n_0_[11] ,\f_ex_pc_reg_n_0_[10] ,\f_ex_pc_reg_n_0_[9] ,\f_ex_pc_reg_n_0_[8] ,\f_ex_pc_reg_n_0_[7] ,\f_ex_pc_reg_n_0_[6] ,\f_ex_pc_reg_n_0_[5] ,\f_ex_pc_reg_n_0_[4] ,\f_ex_pc_reg_n_0_[3] ,\f_ex_pc_reg_n_0_[2] ,\f_ex_pc_reg_n_0_[1] ,\f_ex_pc_reg_n_0_[0] }), .wb_mux(wb_mux[30:0])); LUT3 #( .INIT(8'h82)) \br_corr_cnt[0]_i_1 (.I0(SWITCHES_IBUF), .I1(br), .I2(wb_br_taken), .O(br_corr_cnt0)); LUT1 #( .INIT(2'h1)) \br_corr_cnt[0]_i_3 (.I0(br_corr_cnt_reg[0]), .O(\br_corr_cnt[0]_i_3_n_0 )); FDRE \br_corr_cnt_reg[0] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[0]_i_2_n_7 ), .Q(br_corr_cnt_reg[0]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_corr_cnt_reg[0]_i_2 (.CI(\<const0> ), .CO({\br_corr_cnt_reg[0]_i_2_n_0 ,\br_corr_cnt_reg[0]_i_2_n_1 ,\br_corr_cnt_reg[0]_i_2_n_2 ,\br_corr_cnt_reg[0]_i_2_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const1> }), .O({\br_corr_cnt_reg[0]_i_2_n_4 ,\br_corr_cnt_reg[0]_i_2_n_5 ,\br_corr_cnt_reg[0]_i_2_n_6 ,\br_corr_cnt_reg[0]_i_2_n_7 }), .S({br_corr_cnt_reg[3:1],\br_corr_cnt[0]_i_3_n_0 })); FDRE \br_corr_cnt_reg[10] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[8]_i_1_n_5 ), .Q(br_corr_cnt_reg[10]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[11] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[8]_i_1_n_4 ), .Q(br_corr_cnt_reg[11]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[12] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[12]_i_1_n_7 ), .Q(br_corr_cnt_reg[12]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_corr_cnt_reg[12]_i_1 (.CI(\br_corr_cnt_reg[8]_i_1_n_0 ), .CO({\br_corr_cnt_reg[12]_i_1_n_0 ,\br_corr_cnt_reg[12]_i_1_n_1 ,\br_corr_cnt_reg[12]_i_1_n_2 ,\br_corr_cnt_reg[12]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_corr_cnt_reg[12]_i_1_n_4 ,\br_corr_cnt_reg[12]_i_1_n_5 ,\br_corr_cnt_reg[12]_i_1_n_6 ,\br_corr_cnt_reg[12]_i_1_n_7 }), .S(br_corr_cnt_reg[15:12])); FDRE \br_corr_cnt_reg[13] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[12]_i_1_n_6 ), .Q(br_corr_cnt_reg[13]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[14] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[12]_i_1_n_5 ), .Q(br_corr_cnt_reg[14]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[15] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[12]_i_1_n_4 ), .Q(br_corr_cnt_reg[15]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[16] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[16]_i_1_n_7 ), .Q(br_corr_cnt_reg[16]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_corr_cnt_reg[16]_i_1 (.CI(\br_corr_cnt_reg[12]_i_1_n_0 ), .CO({\br_corr_cnt_reg[16]_i_1_n_0 ,\br_corr_cnt_reg[16]_i_1_n_1 ,\br_corr_cnt_reg[16]_i_1_n_2 ,\br_corr_cnt_reg[16]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_corr_cnt_reg[16]_i_1_n_4 ,\br_corr_cnt_reg[16]_i_1_n_5 ,\br_corr_cnt_reg[16]_i_1_n_6 ,\br_corr_cnt_reg[16]_i_1_n_7 }), .S(br_corr_cnt_reg[19:16])); FDRE \br_corr_cnt_reg[17] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[16]_i_1_n_6 ), .Q(br_corr_cnt_reg[17]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[18] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[16]_i_1_n_5 ), .Q(br_corr_cnt_reg[18]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[19] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[16]_i_1_n_4 ), .Q(br_corr_cnt_reg[19]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[1] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[0]_i_2_n_6 ), .Q(br_corr_cnt_reg[1]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[20] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[20]_i_1_n_7 ), .Q(br_corr_cnt_reg[20]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_corr_cnt_reg[20]_i_1 (.CI(\br_corr_cnt_reg[16]_i_1_n_0 ), .CO({\br_corr_cnt_reg[20]_i_1_n_0 ,\br_corr_cnt_reg[20]_i_1_n_1 ,\br_corr_cnt_reg[20]_i_1_n_2 ,\br_corr_cnt_reg[20]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_corr_cnt_reg[20]_i_1_n_4 ,\br_corr_cnt_reg[20]_i_1_n_5 ,\br_corr_cnt_reg[20]_i_1_n_6 ,\br_corr_cnt_reg[20]_i_1_n_7 }), .S(br_corr_cnt_reg[23:20])); FDRE \br_corr_cnt_reg[21] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[20]_i_1_n_6 ), .Q(br_corr_cnt_reg[21]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[22] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[20]_i_1_n_5 ), .Q(br_corr_cnt_reg[22]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[23] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[20]_i_1_n_4 ), .Q(br_corr_cnt_reg[23]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[24] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[24]_i_1_n_7 ), .Q(br_corr_cnt_reg[24]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_corr_cnt_reg[24]_i_1 (.CI(\br_corr_cnt_reg[20]_i_1_n_0 ), .CO({\br_corr_cnt_reg[24]_i_1_n_0 ,\br_corr_cnt_reg[24]_i_1_n_1 ,\br_corr_cnt_reg[24]_i_1_n_2 ,\br_corr_cnt_reg[24]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_corr_cnt_reg[24]_i_1_n_4 ,\br_corr_cnt_reg[24]_i_1_n_5 ,\br_corr_cnt_reg[24]_i_1_n_6 ,\br_corr_cnt_reg[24]_i_1_n_7 }), .S(br_corr_cnt_reg[27:24])); FDRE \br_corr_cnt_reg[25] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[24]_i_1_n_6 ), .Q(br_corr_cnt_reg[25]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[26] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[24]_i_1_n_5 ), .Q(br_corr_cnt_reg[26]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[27] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[24]_i_1_n_4 ), .Q(br_corr_cnt_reg[27]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[28] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[28]_i_1_n_7 ), .Q(br_corr_cnt_reg[28]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_corr_cnt_reg[28]_i_1 (.CI(\br_corr_cnt_reg[24]_i_1_n_0 ), .CO({\br_corr_cnt_reg[28]_i_1_n_1 ,\br_corr_cnt_reg[28]_i_1_n_2 ,\br_corr_cnt_reg[28]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_corr_cnt_reg[28]_i_1_n_4 ,\br_corr_cnt_reg[28]_i_1_n_5 ,\br_corr_cnt_reg[28]_i_1_n_6 ,\br_corr_cnt_reg[28]_i_1_n_7 }), .S(br_corr_cnt_reg[31:28])); FDRE \br_corr_cnt_reg[29] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[28]_i_1_n_6 ), .Q(br_corr_cnt_reg[29]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[2] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[0]_i_2_n_5 ), .Q(br_corr_cnt_reg[2]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[30] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[28]_i_1_n_5 ), .Q(br_corr_cnt_reg[30]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[31] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[28]_i_1_n_4 ), .Q(br_corr_cnt_reg[31]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[3] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[0]_i_2_n_4 ), .Q(br_corr_cnt_reg[3]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[4] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[4]_i_1_n_7 ), .Q(br_corr_cnt_reg[4]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_corr_cnt_reg[4]_i_1 (.CI(\br_corr_cnt_reg[0]_i_2_n_0 ), .CO({\br_corr_cnt_reg[4]_i_1_n_0 ,\br_corr_cnt_reg[4]_i_1_n_1 ,\br_corr_cnt_reg[4]_i_1_n_2 ,\br_corr_cnt_reg[4]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_corr_cnt_reg[4]_i_1_n_4 ,\br_corr_cnt_reg[4]_i_1_n_5 ,\br_corr_cnt_reg[4]_i_1_n_6 ,\br_corr_cnt_reg[4]_i_1_n_7 }), .S(br_corr_cnt_reg[7:4])); FDRE \br_corr_cnt_reg[5] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[4]_i_1_n_6 ), .Q(br_corr_cnt_reg[5]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[6] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[4]_i_1_n_5 ), .Q(br_corr_cnt_reg[6]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[7] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[4]_i_1_n_4 ), .Q(br_corr_cnt_reg[7]), .R(cnt_reset)); FDRE \br_corr_cnt_reg[8] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[8]_i_1_n_7 ), .Q(br_corr_cnt_reg[8]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_corr_cnt_reg[8]_i_1 (.CI(\br_corr_cnt_reg[4]_i_1_n_0 ), .CO({\br_corr_cnt_reg[8]_i_1_n_0 ,\br_corr_cnt_reg[8]_i_1_n_1 ,\br_corr_cnt_reg[8]_i_1_n_2 ,\br_corr_cnt_reg[8]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_corr_cnt_reg[8]_i_1_n_4 ,\br_corr_cnt_reg[8]_i_1_n_5 ,\br_corr_cnt_reg[8]_i_1_n_6 ,\br_corr_cnt_reg[8]_i_1_n_7 }), .S(br_corr_cnt_reg[11:8])); FDRE \br_corr_cnt_reg[9] (.C(cpu_clk), .CE(br_corr_cnt0), .D(\br_corr_cnt_reg[8]_i_1_n_6 ), .Q(br_corr_cnt_reg[9]), .R(cnt_reset)); LUT1 #( .INIT(2'h1)) \br_inst_cnt[0]_i_4 (.I0(br_inst_cnt_reg[0]), .O(\br_inst_cnt[0]_i_4_n_0 )); FDRE \br_inst_cnt_reg[0] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[0]_i_2_n_7 ), .Q(br_inst_cnt_reg[0]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_inst_cnt_reg[0]_i_2 (.CI(\<const0> ), .CO({\br_inst_cnt_reg[0]_i_2_n_0 ,\br_inst_cnt_reg[0]_i_2_n_1 ,\br_inst_cnt_reg[0]_i_2_n_2 ,\br_inst_cnt_reg[0]_i_2_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const1> }), .O({\br_inst_cnt_reg[0]_i_2_n_4 ,\br_inst_cnt_reg[0]_i_2_n_5 ,\br_inst_cnt_reg[0]_i_2_n_6 ,\br_inst_cnt_reg[0]_i_2_n_7 }), .S({br_inst_cnt_reg[3:1],\br_inst_cnt[0]_i_4_n_0 })); FDRE \br_inst_cnt_reg[10] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[8]_i_1_n_5 ), .Q(br_inst_cnt_reg[10]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[11] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[8]_i_1_n_4 ), .Q(br_inst_cnt_reg[11]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[12] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[12]_i_1_n_7 ), .Q(br_inst_cnt_reg[12]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_inst_cnt_reg[12]_i_1 (.CI(\br_inst_cnt_reg[8]_i_1_n_0 ), .CO({\br_inst_cnt_reg[12]_i_1_n_0 ,\br_inst_cnt_reg[12]_i_1_n_1 ,\br_inst_cnt_reg[12]_i_1_n_2 ,\br_inst_cnt_reg[12]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_inst_cnt_reg[12]_i_1_n_4 ,\br_inst_cnt_reg[12]_i_1_n_5 ,\br_inst_cnt_reg[12]_i_1_n_6 ,\br_inst_cnt_reg[12]_i_1_n_7 }), .S(br_inst_cnt_reg[15:12])); FDRE \br_inst_cnt_reg[13] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[12]_i_1_n_6 ), .Q(br_inst_cnt_reg[13]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[14] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[12]_i_1_n_5 ), .Q(br_inst_cnt_reg[14]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[15] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[12]_i_1_n_4 ), .Q(br_inst_cnt_reg[15]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[16] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[16]_i_1_n_7 ), .Q(br_inst_cnt_reg[16]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_inst_cnt_reg[16]_i_1 (.CI(\br_inst_cnt_reg[12]_i_1_n_0 ), .CO({\br_inst_cnt_reg[16]_i_1_n_0 ,\br_inst_cnt_reg[16]_i_1_n_1 ,\br_inst_cnt_reg[16]_i_1_n_2 ,\br_inst_cnt_reg[16]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_inst_cnt_reg[16]_i_1_n_4 ,\br_inst_cnt_reg[16]_i_1_n_5 ,\br_inst_cnt_reg[16]_i_1_n_6 ,\br_inst_cnt_reg[16]_i_1_n_7 }), .S(br_inst_cnt_reg[19:16])); FDRE \br_inst_cnt_reg[17] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[16]_i_1_n_6 ), .Q(br_inst_cnt_reg[17]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[18] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[16]_i_1_n_5 ), .Q(br_inst_cnt_reg[18]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[19] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[16]_i_1_n_4 ), .Q(br_inst_cnt_reg[19]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[1] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[0]_i_2_n_6 ), .Q(br_inst_cnt_reg[1]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[20] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[20]_i_1_n_7 ), .Q(br_inst_cnt_reg[20]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_inst_cnt_reg[20]_i_1 (.CI(\br_inst_cnt_reg[16]_i_1_n_0 ), .CO({\br_inst_cnt_reg[20]_i_1_n_0 ,\br_inst_cnt_reg[20]_i_1_n_1 ,\br_inst_cnt_reg[20]_i_1_n_2 ,\br_inst_cnt_reg[20]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_inst_cnt_reg[20]_i_1_n_4 ,\br_inst_cnt_reg[20]_i_1_n_5 ,\br_inst_cnt_reg[20]_i_1_n_6 ,\br_inst_cnt_reg[20]_i_1_n_7 }), .S(br_inst_cnt_reg[23:20])); FDRE \br_inst_cnt_reg[21] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[20]_i_1_n_6 ), .Q(br_inst_cnt_reg[21]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[22] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[20]_i_1_n_5 ), .Q(br_inst_cnt_reg[22]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[23] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[20]_i_1_n_4 ), .Q(br_inst_cnt_reg[23]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[24] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[24]_i_1_n_7 ), .Q(br_inst_cnt_reg[24]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_inst_cnt_reg[24]_i_1 (.CI(\br_inst_cnt_reg[20]_i_1_n_0 ), .CO({\br_inst_cnt_reg[24]_i_1_n_0 ,\br_inst_cnt_reg[24]_i_1_n_1 ,\br_inst_cnt_reg[24]_i_1_n_2 ,\br_inst_cnt_reg[24]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_inst_cnt_reg[24]_i_1_n_4 ,\br_inst_cnt_reg[24]_i_1_n_5 ,\br_inst_cnt_reg[24]_i_1_n_6 ,\br_inst_cnt_reg[24]_i_1_n_7 }), .S(br_inst_cnt_reg[27:24])); FDRE \br_inst_cnt_reg[25] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[24]_i_1_n_6 ), .Q(br_inst_cnt_reg[25]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[26] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[24]_i_1_n_5 ), .Q(br_inst_cnt_reg[26]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[27] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[24]_i_1_n_4 ), .Q(br_inst_cnt_reg[27]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[28] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[28]_i_1_n_7 ), .Q(br_inst_cnt_reg[28]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_inst_cnt_reg[28]_i_1 (.CI(\br_inst_cnt_reg[24]_i_1_n_0 ), .CO({\br_inst_cnt_reg[28]_i_1_n_1 ,\br_inst_cnt_reg[28]_i_1_n_2 ,\br_inst_cnt_reg[28]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_inst_cnt_reg[28]_i_1_n_4 ,\br_inst_cnt_reg[28]_i_1_n_5 ,\br_inst_cnt_reg[28]_i_1_n_6 ,\br_inst_cnt_reg[28]_i_1_n_7 }), .S(br_inst_cnt_reg[31:28])); FDRE \br_inst_cnt_reg[29] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[28]_i_1_n_6 ), .Q(br_inst_cnt_reg[29]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[2] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[0]_i_2_n_5 ), .Q(br_inst_cnt_reg[2]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[30] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[28]_i_1_n_5 ), .Q(br_inst_cnt_reg[30]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[31] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[28]_i_1_n_4 ), .Q(br_inst_cnt_reg[31]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[3] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[0]_i_2_n_4 ), .Q(br_inst_cnt_reg[3]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[4] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[4]_i_1_n_7 ), .Q(br_inst_cnt_reg[4]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_inst_cnt_reg[4]_i_1 (.CI(\br_inst_cnt_reg[0]_i_2_n_0 ), .CO({\br_inst_cnt_reg[4]_i_1_n_0 ,\br_inst_cnt_reg[4]_i_1_n_1 ,\br_inst_cnt_reg[4]_i_1_n_2 ,\br_inst_cnt_reg[4]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_inst_cnt_reg[4]_i_1_n_4 ,\br_inst_cnt_reg[4]_i_1_n_5 ,\br_inst_cnt_reg[4]_i_1_n_6 ,\br_inst_cnt_reg[4]_i_1_n_7 }), .S(br_inst_cnt_reg[7:4])); FDRE \br_inst_cnt_reg[5] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[4]_i_1_n_6 ), .Q(br_inst_cnt_reg[5]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[6] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[4]_i_1_n_5 ), .Q(br_inst_cnt_reg[6]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[7] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[4]_i_1_n_4 ), .Q(br_inst_cnt_reg[7]), .R(cnt_reset)); FDRE \br_inst_cnt_reg[8] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[8]_i_1_n_7 ), .Q(br_inst_cnt_reg[8]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \br_inst_cnt_reg[8]_i_1 (.CI(\br_inst_cnt_reg[4]_i_1_n_0 ), .CO({\br_inst_cnt_reg[8]_i_1_n_0 ,\br_inst_cnt_reg[8]_i_1_n_1 ,\br_inst_cnt_reg[8]_i_1_n_2 ,\br_inst_cnt_reg[8]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\br_inst_cnt_reg[8]_i_1_n_4 ,\br_inst_cnt_reg[8]_i_1_n_5 ,\br_inst_cnt_reg[8]_i_1_n_6 ,\br_inst_cnt_reg[8]_i_1_n_7 }), .S(br_inst_cnt_reg[11:8])); FDRE \br_inst_cnt_reg[9] (.C(cpu_clk), .CE(br_inst_cnt), .D(\br_inst_cnt_reg[8]_i_1_n_6 ), .Q(br_inst_cnt_reg[9]), .R(cnt_reset)); branch_predictor br_pred (.D({imm,br_pred_n_30}), .O({imem_n_167,imem_n_168,imem_n_169,imem_n_170}), .Q({\f_ex_pc_reg_n_0_[31] ,imem_ena,\f_ex_pc_reg_n_0_[29] ,\f_ex_pc_reg_n_0_[28] ,\f_ex_pc_reg_n_0_[27] ,\f_ex_pc_reg_n_0_[26] ,\f_ex_pc_reg_n_0_[25] ,\f_ex_pc_reg_n_0_[24] ,\f_ex_pc_reg_n_0_[23] ,\f_ex_pc_reg_n_0_[22] ,\f_ex_pc_reg_n_0_[21] ,\f_ex_pc_reg_n_0_[20] ,\f_ex_pc_reg_n_0_[19] ,\f_ex_pc_reg_n_0_[18] ,\f_ex_pc_reg_n_0_[17] ,\f_ex_pc_reg_n_0_[16] ,\f_ex_pc_reg_n_0_[15] ,\f_ex_pc_reg_n_0_[14] ,\f_ex_pc_reg_n_0_[13] ,\f_ex_pc_reg_n_0_[12] ,\f_ex_pc_reg_n_0_[11] ,\f_ex_pc_reg_n_0_[10] ,\f_ex_pc_reg_n_0_[9] ,\f_ex_pc_reg_n_0_[8] ,\f_ex_pc_reg_n_0_[7] ,\f_ex_pc_reg_n_0_[6] ,\f_ex_pc_reg_n_0_[5] ,\f_ex_pc_reg_n_0_[4] ,\f_ex_pc_reg_n_0_[3] ,\f_ex_pc_reg_n_0_[2] }), .SR(ex_flush), .SWITCHES_IBUF(SWITCHES_IBUF), .br(br), .br_inst_cnt(br_inst_cnt), .\br_inst_cnt_reg[0] (bios_mem_n_204), .br_pred_taken(br_pred_taken), .buttons_pressed(buttons_pressed), .cpu_clk(cpu_clk), .cpu_clk_locked(cpu_clk_locked), .cpu_reset(cpu_reset), .data2(data2), .data3(data3), .douta_reg_1({br_pred_n_31,br_pred_n_32,br_pred_n_33,br_pred_n_34,br_pred_n_35,br_pred_n_36,ra2,ra1,br_pred_n_47,br_pred_n_48,br_pred_n_49,br_pred_n_50,br_pred_n_51,br_pred_n_52,br_pred_n_53,br_pred_n_54,br_pred_n_55,br_pred_n_56,br_pred_n_57,br_pred_n_58,br_pred_n_59,br_pred_n_60,br_pred_n_61}), .douta_reg_1_0({br_pred_n_63,br_pred_n_64,br_pred_n_65,br_pred_n_66,br_pred_n_67,br_pred_n_68,br_pred_n_69,br_pred_n_70,br_pred_n_71,br_pred_n_72,br_pred_n_73,br_pred_n_74,br_pred_n_75,br_pred_n_76,br_pred_n_77,br_pred_n_78,br_pred_n_79,br_pred_n_80,br_pred_n_81,br_pred_n_82,br_pred_n_83,br_pred_n_84,br_pred_n_85,br_pred_n_86,br_pred_n_87,br_pred_n_88,br_pred_n_89,br_pred_n_90,br_pred_n_91,br_pred_n_92,br_pred_n_93,br_pred_n_94}), .douta_reg_1_1({br_pred_n_95,br_pred_n_96,br_pred_n_97,br_pred_n_98,br_pred_n_99,br_pred_n_100,br_pred_n_101,br_pred_n_102,br_pred_n_103,br_pred_n_104,br_pred_n_105,br_pred_n_106,br_pred_n_107,br_pred_n_108,br_pred_n_109,br_pred_n_110,br_pred_n_111,br_pred_n_112,br_pred_n_113,br_pred_n_114,br_pred_n_115,br_pred_n_116,br_pred_n_117,br_pred_n_118,br_pred_n_119,br_pred_n_120,br_pred_n_121,br_pred_n_122,br_pred_n_123,br_pred_n_124,br_pred_n_125,br_pred_n_126}), .douta_reg_1_2(br_pred_n_163), .doutb(imem_doutb), .\ex_wb_inst_reg[6] (br_pred_n_62), .\f_ex_imm_reg[30] (bios_mem_n_126), .\f_ex_rd2_reg[0] (wb_br_taken_i_3_n_0), .\f_ex_rd2_reg[0]_0 ({p_0_in,\ex_wb_inst_reg_n_0_[1] ,\ex_wb_inst_reg_n_0_[0] }), .i__carry__1_i_1__0({ex_wb_pc[31:2],ex_wb_pc[0]}), .mem_reg_0_0({imem_n_171,imem_n_172,imem_n_173,imem_n_174}), .mem_reg_0_0_0({imem_n_175,imem_n_176,imem_n_177,imem_n_178}), .mem_reg_3_3({imem_n_180,imem_n_181,imem_n_182,imem_n_183}), .out(douta_reg), .\pc_reg[0] (pc[0]), .\pc_reg[19] ({rf_n_118,rf_n_119,rf_n_120,rf_n_121}), .\pc_reg[23] ({rf_n_122,rf_n_123,rf_n_124,rf_n_125}), .\pc_reg[27] ({rf_n_126,rf_n_127,rf_n_128,rf_n_129}), .\pc_reg[31] ({p_2_in,p_1_in,\wb_alu_reg_n_0_[29] ,p_0_in10_in,\wb_alu_reg_n_0_[27] ,\wb_alu_reg_n_0_[26] ,\wb_alu_reg_n_0_[25] ,\wb_alu_reg_n_0_[24] ,\wb_alu_reg_n_0_[23] ,\wb_alu_reg_n_0_[22] ,\wb_alu_reg_n_0_[21] ,\wb_alu_reg_n_0_[20] ,\wb_alu_reg_n_0_[19] ,\wb_alu_reg_n_0_[18] ,\wb_alu_reg_n_0_[17] ,\wb_alu_reg_n_0_[16] ,\wb_alu_reg_n_0_[15] ,\wb_alu_reg_n_0_[14] ,\wb_alu_reg_n_0_[13] ,\wb_alu_reg_n_0_[12] ,\wb_alu_reg_n_0_[11] ,\wb_alu_reg_n_0_[10] ,\wb_alu_reg_n_0_[9] ,\wb_alu_reg_n_0_[8] ,\wb_alu_reg_n_0_[7] ,\wb_alu_reg_n_0_[6] ,\wb_alu_reg_n_0_[5] ,\wb_alu_reg_n_0_[4] ,\wb_alu_reg_n_0_[3] ,\wb_alu_reg_n_0_[2] ,\wb_alu_reg_n_0_[1] ,\wb_alu_reg_n_0_[0] }), .\pc_reg[31]_0 (imem_n_84), .\pc_reg[31]_1 ({rf_n_130,rf_n_131,rf_n_132,rf_n_133}), .rd10(rd10), .rd20(rd20), .\wb_alu_reg[31] (br_pred_n_127), .\wb_alu_reg[31]_0 ({br_pred_n_128,br_pred_n_129,br_pred_n_130,br_pred_n_131,br_pred_n_132,br_pred_n_133,br_pred_n_134,br_pred_n_135,br_pred_n_136,br_pred_n_137,br_pred_n_138,br_pred_n_139,br_pred_n_140,br_pred_n_141,br_pred_n_142,br_pred_n_143,br_pred_n_144,br_pred_n_145,br_pred_n_146,br_pred_n_147,br_pred_n_148,br_pred_n_149,br_pred_n_150,br_pred_n_151,br_pred_n_152,br_pred_n_153,br_pred_n_154,br_pred_n_155,br_pred_n_156,br_pred_n_157,br_pred_n_158,br_pred_n_159}), .\wb_alu_reg[31]_1 (br_pred_n_160), .wb_br_taken(wb_br_taken), .wb_br_taken_reg(imem_n_118)); LUT1 #( .INIT(2'h1)) \cycle_cnt[0]_i_8 (.I0(cycle_cnt_reg[0]), .O(\cycle_cnt[0]_i_8_n_0 )); FDRE \cycle_cnt_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[0]_i_2_n_7 ), .Q(cycle_cnt_reg[0]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \cycle_cnt_reg[0]_i_2 (.CI(\<const0> ), .CO({\cycle_cnt_reg[0]_i_2_n_0 ,\cycle_cnt_reg[0]_i_2_n_1 ,\cycle_cnt_reg[0]_i_2_n_2 ,\cycle_cnt_reg[0]_i_2_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const1> }), .O({\cycle_cnt_reg[0]_i_2_n_4 ,\cycle_cnt_reg[0]_i_2_n_5 ,\cycle_cnt_reg[0]_i_2_n_6 ,\cycle_cnt_reg[0]_i_2_n_7 }), .S({cycle_cnt_reg[3:1],\cycle_cnt[0]_i_8_n_0 })); FDRE \cycle_cnt_reg[10] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[8]_i_1_n_5 ), .Q(cycle_cnt_reg[10]), .R(cnt_reset)); FDRE \cycle_cnt_reg[11] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[8]_i_1_n_4 ), .Q(cycle_cnt_reg[11]), .R(cnt_reset)); FDRE \cycle_cnt_reg[12] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[12]_i_1_n_7 ), .Q(cycle_cnt_reg[12]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \cycle_cnt_reg[12]_i_1 (.CI(\cycle_cnt_reg[8]_i_1_n_0 ), .CO({\cycle_cnt_reg[12]_i_1_n_0 ,\cycle_cnt_reg[12]_i_1_n_1 ,\cycle_cnt_reg[12]_i_1_n_2 ,\cycle_cnt_reg[12]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\cycle_cnt_reg[12]_i_1_n_4 ,\cycle_cnt_reg[12]_i_1_n_5 ,\cycle_cnt_reg[12]_i_1_n_6 ,\cycle_cnt_reg[12]_i_1_n_7 }), .S(cycle_cnt_reg[15:12])); FDRE \cycle_cnt_reg[13] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[12]_i_1_n_6 ), .Q(cycle_cnt_reg[13]), .R(cnt_reset)); FDRE \cycle_cnt_reg[14] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[12]_i_1_n_5 ), .Q(cycle_cnt_reg[14]), .R(cnt_reset)); FDRE \cycle_cnt_reg[15] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[12]_i_1_n_4 ), .Q(cycle_cnt_reg[15]), .R(cnt_reset)); FDRE \cycle_cnt_reg[16] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[16]_i_1_n_7 ), .Q(cycle_cnt_reg[16]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \cycle_cnt_reg[16]_i_1 (.CI(\cycle_cnt_reg[12]_i_1_n_0 ), .CO({\cycle_cnt_reg[16]_i_1_n_0 ,\cycle_cnt_reg[16]_i_1_n_1 ,\cycle_cnt_reg[16]_i_1_n_2 ,\cycle_cnt_reg[16]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\cycle_cnt_reg[16]_i_1_n_4 ,\cycle_cnt_reg[16]_i_1_n_5 ,\cycle_cnt_reg[16]_i_1_n_6 ,\cycle_cnt_reg[16]_i_1_n_7 }), .S(cycle_cnt_reg[19:16])); FDRE \cycle_cnt_reg[17] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[16]_i_1_n_6 ), .Q(cycle_cnt_reg[17]), .R(cnt_reset)); FDRE \cycle_cnt_reg[18] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[16]_i_1_n_5 ), .Q(cycle_cnt_reg[18]), .R(cnt_reset)); FDRE \cycle_cnt_reg[19] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[16]_i_1_n_4 ), .Q(cycle_cnt_reg[19]), .R(cnt_reset)); FDRE \cycle_cnt_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[0]_i_2_n_6 ), .Q(cycle_cnt_reg[1]), .R(cnt_reset)); FDRE \cycle_cnt_reg[20] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[20]_i_1_n_7 ), .Q(cycle_cnt_reg[20]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \cycle_cnt_reg[20]_i_1 (.CI(\cycle_cnt_reg[16]_i_1_n_0 ), .CO({\cycle_cnt_reg[20]_i_1_n_0 ,\cycle_cnt_reg[20]_i_1_n_1 ,\cycle_cnt_reg[20]_i_1_n_2 ,\cycle_cnt_reg[20]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\cycle_cnt_reg[20]_i_1_n_4 ,\cycle_cnt_reg[20]_i_1_n_5 ,\cycle_cnt_reg[20]_i_1_n_6 ,\cycle_cnt_reg[20]_i_1_n_7 }), .S(cycle_cnt_reg[23:20])); FDRE \cycle_cnt_reg[21] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[20]_i_1_n_6 ), .Q(cycle_cnt_reg[21]), .R(cnt_reset)); FDRE \cycle_cnt_reg[22] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[20]_i_1_n_5 ), .Q(cycle_cnt_reg[22]), .R(cnt_reset)); FDRE \cycle_cnt_reg[23] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[20]_i_1_n_4 ), .Q(cycle_cnt_reg[23]), .R(cnt_reset)); FDRE \cycle_cnt_reg[24] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[24]_i_1_n_7 ), .Q(cycle_cnt_reg[24]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \cycle_cnt_reg[24]_i_1 (.CI(\cycle_cnt_reg[20]_i_1_n_0 ), .CO({\cycle_cnt_reg[24]_i_1_n_0 ,\cycle_cnt_reg[24]_i_1_n_1 ,\cycle_cnt_reg[24]_i_1_n_2 ,\cycle_cnt_reg[24]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\cycle_cnt_reg[24]_i_1_n_4 ,\cycle_cnt_reg[24]_i_1_n_5 ,\cycle_cnt_reg[24]_i_1_n_6 ,\cycle_cnt_reg[24]_i_1_n_7 }), .S(cycle_cnt_reg[27:24])); FDRE \cycle_cnt_reg[25] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[24]_i_1_n_6 ), .Q(cycle_cnt_reg[25]), .R(cnt_reset)); FDRE \cycle_cnt_reg[26] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[24]_i_1_n_5 ), .Q(cycle_cnt_reg[26]), .R(cnt_reset)); FDRE \cycle_cnt_reg[27] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[24]_i_1_n_4 ), .Q(cycle_cnt_reg[27]), .R(cnt_reset)); FDRE \cycle_cnt_reg[28] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[28]_i_1_n_7 ), .Q(cycle_cnt_reg[28]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \cycle_cnt_reg[28]_i_1 (.CI(\cycle_cnt_reg[24]_i_1_n_0 ), .CO({\cycle_cnt_reg[28]_i_1_n_1 ,\cycle_cnt_reg[28]_i_1_n_2 ,\cycle_cnt_reg[28]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\cycle_cnt_reg[28]_i_1_n_4 ,\cycle_cnt_reg[28]_i_1_n_5 ,\cycle_cnt_reg[28]_i_1_n_6 ,\cycle_cnt_reg[28]_i_1_n_7 }), .S(cycle_cnt_reg[31:28])); FDRE \cycle_cnt_reg[29] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[28]_i_1_n_6 ), .Q(cycle_cnt_reg[29]), .R(cnt_reset)); FDRE \cycle_cnt_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[0]_i_2_n_5 ), .Q(cycle_cnt_reg[2]), .R(cnt_reset)); FDRE \cycle_cnt_reg[30] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[28]_i_1_n_5 ), .Q(cycle_cnt_reg[30]), .R(cnt_reset)); FDRE \cycle_cnt_reg[31] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[28]_i_1_n_4 ), .Q(cycle_cnt_reg[31]), .R(cnt_reset)); FDRE \cycle_cnt_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[0]_i_2_n_4 ), .Q(cycle_cnt_reg[3]), .R(cnt_reset)); FDRE \cycle_cnt_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[4]_i_1_n_7 ), .Q(cycle_cnt_reg[4]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \cycle_cnt_reg[4]_i_1 (.CI(\cycle_cnt_reg[0]_i_2_n_0 ), .CO({\cycle_cnt_reg[4]_i_1_n_0 ,\cycle_cnt_reg[4]_i_1_n_1 ,\cycle_cnt_reg[4]_i_1_n_2 ,\cycle_cnt_reg[4]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\cycle_cnt_reg[4]_i_1_n_4 ,\cycle_cnt_reg[4]_i_1_n_5 ,\cycle_cnt_reg[4]_i_1_n_6 ,\cycle_cnt_reg[4]_i_1_n_7 }), .S(cycle_cnt_reg[7:4])); FDRE \cycle_cnt_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[4]_i_1_n_6 ), .Q(cycle_cnt_reg[5]), .R(cnt_reset)); FDRE \cycle_cnt_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[4]_i_1_n_5 ), .Q(cycle_cnt_reg[6]), .R(cnt_reset)); FDRE \cycle_cnt_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[4]_i_1_n_4 ), .Q(cycle_cnt_reg[7]), .R(cnt_reset)); FDRE \cycle_cnt_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[8]_i_1_n_7 ), .Q(cycle_cnt_reg[8]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \cycle_cnt_reg[8]_i_1 (.CI(\cycle_cnt_reg[4]_i_1_n_0 ), .CO({\cycle_cnt_reg[8]_i_1_n_0 ,\cycle_cnt_reg[8]_i_1_n_1 ,\cycle_cnt_reg[8]_i_1_n_2 ,\cycle_cnt_reg[8]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\cycle_cnt_reg[8]_i_1_n_4 ,\cycle_cnt_reg[8]_i_1_n_5 ,\cycle_cnt_reg[8]_i_1_n_6 ,\cycle_cnt_reg[8]_i_1_n_7 }), .S(cycle_cnt_reg[11:8])); FDRE \cycle_cnt_reg[9] (.C(cpu_clk), .CE(\<const1> ), .D(\cycle_cnt_reg[8]_i_1_n_6 ), .Q(cycle_cnt_reg[9]), .R(cnt_reset)); dmem dmem (.ADDRARDADDR({ex_alu[15:14],bios_mem_n_180,ex_alu[12:4],bios_mem_n_194,bios_mem_n_195}), .ALUSel(ALUSel), .ASel(ASel), .BSel(BSel), .D(ex_alu[31]), .DI(dmem_n_8), .Q({\ex_wb_inst_reg_n_0_[14] ,\ex_wb_inst_reg_n_0_[13] ,\ex_wb_inst_reg_n_0_[12] }), .S(dmem_n_18), .addr({bios_mem_n_196,bios_mem_n_197}), .\bit_counter[3]_i_35 ({b_mux[16],b_mux[4:3]}), .cpu_clk(cpu_clk), .dmem_we(dmem_we), .dout(dmem_dout), .ex_alu(ex_alu[13]), .\ex_wb_inst_reg[12] (dmem_n_3), .\ex_wb_inst_reg[12]_0 (fwd_b), .\ex_wb_inst_reg[12]_1 (dmem_n_6), .\ex_wb_inst_reg[12]_2 (dmem_n_7), .\f_ex_imm_reg[31] (dmem_n_9), .\f_ex_imm_reg[31]_0 (b_mux[31]), .\f_ex_inst_reg[14] (dmem_n_14), .\f_ex_inst_reg[2] (dmem_n_0), .\f_ex_inst_reg[2]_0 (dmem_n_1), .\f_ex_inst_reg[2]_1 (dmem_n_2), .\f_ex_inst_reg[2]_2 (dmem_n_15), .\f_ex_pc_reg[31] (a_mux), .\f_ex_pc_reg[31]_0 (dmem_n_13), .\f_ex_pc_reg[31]_1 (dmem_n_16), .\f_ex_pc_reg[31]_2 (dmem_n_17), .mem_reg_3_3_0(mem_wb_mux[30:16]), .mem_reg_3_3_1(imem_n_1), .mem_reg_3_3_2(imem_n_77), .mem_reg_3_3_3(imem_n_13), .mem_reg_3_3_4({bios_mem_n_181,bios_mem_n_182,bios_mem_n_183,bios_mem_n_184,bios_mem_n_185,bios_mem_n_186,bios_mem_n_187,bios_mem_n_188,bios_mem_n_189}), .mem_reg_r1_0_31_12_17_i_10(imem_n_139), .mem_reg_r1_0_31_12_17_i_13(imem_n_142), .mem_reg_r1_0_31_12_17_i_16(imem_n_141), .mem_reg_r1_0_31_12_17_i_7(imem_n_140), .mem_reg_r1_0_31_24_29_i_11(imem_n_146), .mem_reg_r1_0_31_24_29_i_13(imem_n_145), .mem_reg_r1_0_31_24_29_i_15(imem_n_148), .mem_reg_r1_0_31_24_29_i_17(imem_n_147), .mem_reg_r1_0_31_24_29_i_7(imem_n_144), .mem_reg_r1_0_31_24_29_i_9(imem_n_143), .mem_reg_r1_0_31_6_11_i_11(imem_n_136), .mem_reg_r1_0_31_6_11_i_14(imem_n_135), .mem_reg_r1_0_31_6_11_i_17(imem_n_138), .mem_reg_r1_0_31_6_11_i_20(imem_n_137), .p_1_in(dmem_din), .\pprev_data[30]_i_2 (rf_n_97), .\pprev_data[31]_i_2_0 (rf_n_96), .\pprev_data[31]_i_2_1 (imem_n_120), .\pprev_data[31]_i_2_2 (rf_n_102), .\pprev_data[31]_i_2_3 (doutb_reg[31:15]), .\pprev_data[31]_i_2_4 (rf_n_101), .\pprev_data[31]_i_2_5 (rf_n_98), .\pprev_data_reg[31] ({\wb_alu_reg_n_0_[1] ,\wb_alu_reg_n_0_[0] }), .\pprev_data_reg[31]_0 (bios_mem_n_201), .\pprev_data_reg[31]_1 (imem_n_117), .\pprev_data_reg[31]_2 (bios_mem_n_202), .\pprev_data_reg[31]_3 (rf_n_94), .wb_BrLt_reg_i_3(imem_n_76), .wb_BrLt_reg_i_3_0(on_chip_uart_n_26), .wb_BrLt_reg_i_3_1(bios_mem_n_36), .\wb_alu[0]_i_33 (\f_ex_pc_reg_n_0_[31] ), .\wb_alu[0]_i_33_0 (f_ex_imm[31]), .\wb_alu_reg[31] ({\alu/data8 [31],\alu/data8 [28],\alu/data8 [13],\alu/data8 [2]}), .\wb_alu_reg[31]_0 (bios_mem_n_177), .\wb_alu_reg[31]_1 (bios_mem_n_4), .\wb_alu_reg[31]_2 (bios_mem_n_3), .wb_mux(wb_mux[31])); FDRE \ex_wb_inst_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[0]), .Q(\ex_wb_inst_reg_n_0_[0] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[10] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[10]), .Q(wa[3]), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[11] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[11]), .Q(wa[4]), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[12] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[12]), .Q(\ex_wb_inst_reg_n_0_[12] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[13] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[13]), .Q(\ex_wb_inst_reg_n_0_[13] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[14] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[14]), .Q(\ex_wb_inst_reg_n_0_[14] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[15] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[15]), .Q(\ex_wb_inst_reg_n_0_[15] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[16] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[16]), .Q(\ex_wb_inst_reg_n_0_[16] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[17] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[17]), .Q(\ex_wb_inst_reg_n_0_[17] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[18] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[18]), .Q(\ex_wb_inst_reg_n_0_[18] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[19] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[19]), .Q(\ex_wb_inst_reg_n_0_[19] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[1]), .Q(\ex_wb_inst_reg_n_0_[1] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[20] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[20]), .Q(\ex_wb_inst_reg_n_0_[20] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[21] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[21]), .Q(\ex_wb_inst_reg_n_0_[21] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[22] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[22]), .Q(\ex_wb_inst_reg_n_0_[22] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[23] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[23]), .Q(\ex_wb_inst_reg_n_0_[23] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[24] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[24]), .Q(\ex_wb_inst_reg_n_0_[24] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[25] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[25]), .Q(\ex_wb_inst_reg_n_0_[25] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[26] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[26]), .Q(\ex_wb_inst_reg_n_0_[26] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[27] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[27]), .Q(\ex_wb_inst_reg_n_0_[27] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[28] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[28]), .Q(\ex_wb_inst_reg_n_0_[28] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[29] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[29]), .Q(\ex_wb_inst_reg_n_0_[29] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[2]), .Q(p_0_in[0]), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[30] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[30]), .Q(\ex_wb_inst_reg_n_0_[30] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[31] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_imm[31]), .Q(\ex_wb_inst_reg_n_0_[31] ), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[3]), .Q(p_0_in[1]), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[4]), .Q(p_0_in[2]), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[5]), .Q(p_0_in[3]), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[6]), .Q(p_0_in[4]), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[7]), .Q(wa[0]), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[8]), .Q(wa[1]), .R(ex_wb_pc0)); FDRE \ex_wb_inst_reg[9] (.C(cpu_clk), .CE(\<const1> ), .D(f_ex_inst[9]), .Q(wa[2]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[0] ), .Q(ex_wb_pc[0]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[10] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[10] ), .Q(ex_wb_pc[10]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[11] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[11] ), .Q(ex_wb_pc[11]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[12] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[12] ), .Q(ex_wb_pc[12]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[13] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[13] ), .Q(ex_wb_pc[13]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[14] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[14] ), .Q(ex_wb_pc[14]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[15] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[15] ), .Q(ex_wb_pc[15]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[16] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[16] ), .Q(ex_wb_pc[16]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[17] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[17] ), .Q(ex_wb_pc[17]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[18] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[18] ), .Q(ex_wb_pc[18]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[19] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[19] ), .Q(ex_wb_pc[19]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[1] ), .Q(ex_wb_pc[1]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[20] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[20] ), .Q(ex_wb_pc[20]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[21] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[21] ), .Q(ex_wb_pc[21]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[22] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[22] ), .Q(ex_wb_pc[22]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[23] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[23] ), .Q(ex_wb_pc[23]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[24] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[24] ), .Q(ex_wb_pc[24]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[25] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[25] ), .Q(ex_wb_pc[25]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[26] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[26] ), .Q(ex_wb_pc[26]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[27] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[27] ), .Q(ex_wb_pc[27]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[28] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[28] ), .Q(ex_wb_pc[28]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[29] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[29] ), .Q(ex_wb_pc[29]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[2] ), .Q(ex_wb_pc[2]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[30] (.C(cpu_clk), .CE(\<const1> ), .D(imem_ena), .Q(ex_wb_pc[30]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[31] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[31] ), .Q(ex_wb_pc[31]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[3] ), .Q(ex_wb_pc[3]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[4] ), .Q(ex_wb_pc[4]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[5] ), .Q(ex_wb_pc[5]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[6] ), .Q(ex_wb_pc[6]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[7] ), .Q(ex_wb_pc[7]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[8] ), .Q(ex_wb_pc[8]), .R(ex_wb_pc0)); FDRE \ex_wb_pc_reg[9] (.C(cpu_clk), .CE(\<const1> ), .D(\f_ex_pc_reg_n_0_[9] ), .Q(ex_wb_pc[9]), .R(ex_wb_pc0)); FDRE \f_ex_imm_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_30), .Q(f_ex_imm[0]), .R(ex_flush)); FDRE \f_ex_imm_reg[10] (.C(cpu_clk), .CE(\<const1> ), .D(imm[10]), .Q(f_ex_imm[10]), .R(ex_flush)); FDRE \f_ex_imm_reg[11] (.C(cpu_clk), .CE(\<const1> ), .D(imm[11]), .Q(f_ex_imm[11]), .R(ex_flush)); FDRE \f_ex_imm_reg[12] (.C(cpu_clk), .CE(\<const1> ), .D(imm[12]), .Q(f_ex_imm[12]), .R(ex_flush)); FDRE \f_ex_imm_reg[13] (.C(cpu_clk), .CE(\<const1> ), .D(imm[13]), .Q(f_ex_imm[13]), .R(ex_flush)); FDRE \f_ex_imm_reg[14] (.C(cpu_clk), .CE(\<const1> ), .D(imm[14]), .Q(f_ex_imm[14]), .R(ex_flush)); FDRE \f_ex_imm_reg[15] (.C(cpu_clk), .CE(\<const1> ), .D(imm[15]), .Q(f_ex_imm[15]), .R(ex_flush)); FDRE \f_ex_imm_reg[16] (.C(cpu_clk), .CE(\<const1> ), .D(imm[16]), .Q(f_ex_imm[16]), .R(ex_flush)); FDRE \f_ex_imm_reg[17] (.C(cpu_clk), .CE(\<const1> ), .D(imm[17]), .Q(f_ex_imm[17]), .R(ex_flush)); FDRE \f_ex_imm_reg[18] (.C(cpu_clk), .CE(\<const1> ), .D(imm[18]), .Q(f_ex_imm[18]), .R(ex_flush)); FDRE \f_ex_imm_reg[19] (.C(cpu_clk), .CE(\<const1> ), .D(imm[19]), .Q(f_ex_imm[19]), .R(ex_flush)); FDRE \f_ex_imm_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(imm[1]), .Q(f_ex_imm[1]), .R(ex_flush)); FDRE \f_ex_imm_reg[20] (.C(cpu_clk), .CE(\<const1> ), .D(imm[20]), .Q(f_ex_imm[20]), .R(ex_flush)); FDRE \f_ex_imm_reg[21] (.C(cpu_clk), .CE(\<const1> ), .D(imm[21]), .Q(f_ex_imm[21]), .R(ex_flush)); FDRE \f_ex_imm_reg[22] (.C(cpu_clk), .CE(\<const1> ), .D(imm[22]), .Q(f_ex_imm[22]), .R(ex_flush)); FDRE \f_ex_imm_reg[23] (.C(cpu_clk), .CE(\<const1> ), .D(imm[23]), .Q(f_ex_imm[23]), .R(ex_flush)); FDRE \f_ex_imm_reg[24] (.C(cpu_clk), .CE(\<const1> ), .D(imm[24]), .Q(f_ex_imm[24]), .R(ex_flush)); FDRE \f_ex_imm_reg[25] (.C(cpu_clk), .CE(\<const1> ), .D(imm[25]), .Q(f_ex_imm[25]), .R(ex_flush)); FDRE \f_ex_imm_reg[26] (.C(cpu_clk), .CE(\<const1> ), .D(imm[26]), .Q(f_ex_imm[26]), .R(ex_flush)); FDRE \f_ex_imm_reg[27] (.C(cpu_clk), .CE(\<const1> ), .D(imm[27]), .Q(f_ex_imm[27]), .R(ex_flush)); FDRE \f_ex_imm_reg[28] (.C(cpu_clk), .CE(\<const1> ), .D(imm[28]), .Q(f_ex_imm[28]), .R(ex_flush)); FDRE \f_ex_imm_reg[29] (.C(cpu_clk), .CE(\<const1> ), .D(imm[29]), .Q(f_ex_imm[29]), .R(ex_flush)); FDRE \f_ex_imm_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(imm[2]), .Q(f_ex_imm[2]), .R(ex_flush)); FDRE \f_ex_imm_reg[30] (.C(cpu_clk), .CE(\<const1> ), .D(imm[30]), .Q(f_ex_imm[30]), .R(ex_flush)); FDRE \f_ex_imm_reg[31] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_163), .Q(f_ex_imm[31]), .R(ex_flush)); FDRE \f_ex_imm_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(imm[3]), .Q(f_ex_imm[3]), .R(ex_flush)); FDRE \f_ex_imm_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(imm[4]), .Q(f_ex_imm[4]), .R(ex_flush)); FDRE \f_ex_imm_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(imm[5]), .Q(f_ex_imm[5]), .R(ex_flush)); FDRE \f_ex_imm_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(imm[6]), .Q(f_ex_imm[6]), .R(ex_flush)); FDRE \f_ex_imm_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(imm[7]), .Q(f_ex_imm[7]), .R(ex_flush)); FDRE \f_ex_imm_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(imm[8]), .Q(f_ex_imm[8]), .R(ex_flush)); FDRE \f_ex_imm_reg[9] (.C(cpu_clk), .CE(\<const1> ), .D(imm[9]), .Q(f_ex_imm[9]), .R(ex_flush)); FDRE \f_ex_inst_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_61), .Q(f_ex_inst[0]), .R(ex_flush)); FDRE \f_ex_inst_reg[10] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_51), .Q(f_ex_inst[10]), .R(ex_flush)); FDRE \f_ex_inst_reg[11] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_50), .Q(f_ex_inst[11]), .R(ex_flush)); FDRE \f_ex_inst_reg[12] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_49), .Q(f_ex_inst[12]), .R(ex_flush)); FDRE \f_ex_inst_reg[13] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_48), .Q(f_ex_inst[13]), .R(ex_flush)); FDRE \f_ex_inst_reg[14] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_47), .Q(f_ex_inst[14]), .R(ex_flush)); FDRE \f_ex_inst_reg[15] (.C(cpu_clk), .CE(\<const1> ), .D(ra1[0]), .Q(f_ex_inst[15]), .R(ex_flush)); FDRE \f_ex_inst_reg[16] (.C(cpu_clk), .CE(\<const1> ), .D(ra1[1]), .Q(f_ex_inst[16]), .R(ex_flush)); FDRE \f_ex_inst_reg[17] (.C(cpu_clk), .CE(\<const1> ), .D(ra1[2]), .Q(f_ex_inst[17]), .R(ex_flush)); FDRE \f_ex_inst_reg[18] (.C(cpu_clk), .CE(\<const1> ), .D(ra1[3]), .Q(f_ex_inst[18]), .R(ex_flush)); FDRE \f_ex_inst_reg[19] (.C(cpu_clk), .CE(\<const1> ), .D(ra1[4]), .Q(f_ex_inst[19]), .R(ex_flush)); FDRE \f_ex_inst_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_60), .Q(f_ex_inst[1]), .R(ex_flush)); FDRE \f_ex_inst_reg[20] (.C(cpu_clk), .CE(\<const1> ), .D(ra2[0]), .Q(f_ex_inst[20]), .R(ex_flush)); FDRE \f_ex_inst_reg[21] (.C(cpu_clk), .CE(\<const1> ), .D(ra2[1]), .Q(f_ex_inst[21]), .R(ex_flush)); FDRE \f_ex_inst_reg[22] (.C(cpu_clk), .CE(\<const1> ), .D(ra2[2]), .Q(f_ex_inst[22]), .R(ex_flush)); FDRE \f_ex_inst_reg[23] (.C(cpu_clk), .CE(\<const1> ), .D(ra2[3]), .Q(f_ex_inst[23]), .R(ex_flush)); FDRE \f_ex_inst_reg[24] (.C(cpu_clk), .CE(\<const1> ), .D(ra2[4]), .Q(f_ex_inst[24]), .R(ex_flush)); FDRE \f_ex_inst_reg[25] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_36), .Q(f_ex_inst[25]), .R(ex_flush)); FDRE \f_ex_inst_reg[26] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_35), .Q(f_ex_inst[26]), .R(ex_flush)); FDRE \f_ex_inst_reg[27] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_34), .Q(f_ex_inst[27]), .R(ex_flush)); FDRE \f_ex_inst_reg[28] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_33), .Q(f_ex_inst[28]), .R(ex_flush)); FDRE \f_ex_inst_reg[29] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_32), .Q(f_ex_inst[29]), .R(ex_flush)); FDRE \f_ex_inst_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_59), .Q(f_ex_inst[2]), .R(ex_flush)); FDRE \f_ex_inst_reg[30] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_31), .Q(f_ex_inst[30]), .R(ex_flush)); FDRE \f_ex_inst_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_58), .Q(f_ex_inst[3]), .R(ex_flush)); FDRE \f_ex_inst_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_57), .Q(f_ex_inst[4]), .R(ex_flush)); FDRE \f_ex_inst_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_56), .Q(f_ex_inst[5]), .R(ex_flush)); FDRE \f_ex_inst_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_55), .Q(f_ex_inst[6]), .R(ex_flush)); FDRE \f_ex_inst_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_54), .Q(f_ex_inst[7]), .R(ex_flush)); FDRE \f_ex_inst_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_53), .Q(f_ex_inst[8]), .R(ex_flush)); FDRE \f_ex_inst_reg[9] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_52), .Q(f_ex_inst[9]), .R(ex_flush)); FDRE \f_ex_pc_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(pc[0]), .Q(\f_ex_pc_reg_n_0_[0] ), .R(ex_flush)); FDRE \f_ex_pc_reg[10] (.C(cpu_clk), .CE(\<const1> ), .D(pc[10]), .Q(\f_ex_pc_reg_n_0_[10] ), .R(ex_flush)); FDRE \f_ex_pc_reg[11] (.C(cpu_clk), .CE(\<const1> ), .D(pc[11]), .Q(\f_ex_pc_reg_n_0_[11] ), .R(ex_flush)); FDRE \f_ex_pc_reg[12] (.C(cpu_clk), .CE(\<const1> ), .D(pc[12]), .Q(\f_ex_pc_reg_n_0_[12] ), .R(ex_flush)); FDRE \f_ex_pc_reg[13] (.C(cpu_clk), .CE(\<const1> ), .D(pc[13]), .Q(\f_ex_pc_reg_n_0_[13] ), .R(ex_flush)); FDRE \f_ex_pc_reg[14] (.C(cpu_clk), .CE(\<const1> ), .D(pc[14]), .Q(\f_ex_pc_reg_n_0_[14] ), .R(ex_flush)); FDRE \f_ex_pc_reg[15] (.C(cpu_clk), .CE(\<const1> ), .D(pc[15]), .Q(\f_ex_pc_reg_n_0_[15] ), .R(ex_flush)); FDRE \f_ex_pc_reg[16] (.C(cpu_clk), .CE(\<const1> ), .D(pc[16]), .Q(\f_ex_pc_reg_n_0_[16] ), .R(ex_flush)); FDRE \f_ex_pc_reg[17] (.C(cpu_clk), .CE(\<const1> ), .D(pc[17]), .Q(\f_ex_pc_reg_n_0_[17] ), .R(ex_flush)); FDRE \f_ex_pc_reg[18] (.C(cpu_clk), .CE(\<const1> ), .D(pc[18]), .Q(\f_ex_pc_reg_n_0_[18] ), .R(ex_flush)); FDRE \f_ex_pc_reg[19] (.C(cpu_clk), .CE(\<const1> ), .D(pc[19]), .Q(\f_ex_pc_reg_n_0_[19] ), .R(ex_flush)); FDRE \f_ex_pc_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(pc[1]), .Q(\f_ex_pc_reg_n_0_[1] ), .R(ex_flush)); FDRE \f_ex_pc_reg[20] (.C(cpu_clk), .CE(\<const1> ), .D(pc[20]), .Q(\f_ex_pc_reg_n_0_[20] ), .R(ex_flush)); FDRE \f_ex_pc_reg[21] (.C(cpu_clk), .CE(\<const1> ), .D(pc[21]), .Q(\f_ex_pc_reg_n_0_[21] ), .R(ex_flush)); FDRE \f_ex_pc_reg[22] (.C(cpu_clk), .CE(\<const1> ), .D(pc[22]), .Q(\f_ex_pc_reg_n_0_[22] ), .R(ex_flush)); FDRE \f_ex_pc_reg[23] (.C(cpu_clk), .CE(\<const1> ), .D(pc[23]), .Q(\f_ex_pc_reg_n_0_[23] ), .R(ex_flush)); FDRE \f_ex_pc_reg[24] (.C(cpu_clk), .CE(\<const1> ), .D(pc[24]), .Q(\f_ex_pc_reg_n_0_[24] ), .R(ex_flush)); FDRE \f_ex_pc_reg[25] (.C(cpu_clk), .CE(\<const1> ), .D(pc[25]), .Q(\f_ex_pc_reg_n_0_[25] ), .R(ex_flush)); FDRE \f_ex_pc_reg[26] (.C(cpu_clk), .CE(\<const1> ), .D(pc[26]), .Q(\f_ex_pc_reg_n_0_[26] ), .R(ex_flush)); FDRE \f_ex_pc_reg[27] (.C(cpu_clk), .CE(\<const1> ), .D(pc[27]), .Q(\f_ex_pc_reg_n_0_[27] ), .R(ex_flush)); FDRE \f_ex_pc_reg[28] (.C(cpu_clk), .CE(\<const1> ), .D(pc[28]), .Q(\f_ex_pc_reg_n_0_[28] ), .R(ex_flush)); FDRE \f_ex_pc_reg[29] (.C(cpu_clk), .CE(\<const1> ), .D(pc[29]), .Q(\f_ex_pc_reg_n_0_[29] ), .R(ex_flush)); FDRE \f_ex_pc_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(pc[2]), .Q(\f_ex_pc_reg_n_0_[2] ), .R(ex_flush)); FDRE \f_ex_pc_reg[30] (.C(cpu_clk), .CE(\<const1> ), .D(pc[30]), .Q(imem_ena), .R(ex_flush)); FDRE \f_ex_pc_reg[31] (.C(cpu_clk), .CE(\<const1> ), .D(pc[31]), .Q(\f_ex_pc_reg_n_0_[31] ), .R(ex_flush)); FDRE \f_ex_pc_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(pc[3]), .Q(\f_ex_pc_reg_n_0_[3] ), .R(ex_flush)); FDRE \f_ex_pc_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(pc[4]), .Q(\f_ex_pc_reg_n_0_[4] ), .R(ex_flush)); FDRE \f_ex_pc_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(pc[5]), .Q(\f_ex_pc_reg_n_0_[5] ), .R(ex_flush)); FDRE \f_ex_pc_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(pc[6]), .Q(\f_ex_pc_reg_n_0_[6] ), .R(ex_flush)); FDRE \f_ex_pc_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(pc[7]), .Q(\f_ex_pc_reg_n_0_[7] ), .R(ex_flush)); FDRE \f_ex_pc_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(pc[8]), .Q(\f_ex_pc_reg_n_0_[8] ), .R(ex_flush)); FDRE \f_ex_pc_reg[9] (.C(cpu_clk), .CE(\<const1> ), .D(pc[9]), .Q(\f_ex_pc_reg_n_0_[9] ), .R(ex_flush)); FDRE \f_ex_rd1_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_94), .Q(f_ex_rd1[0]), .R(ex_flush)); FDRE \f_ex_rd1_reg[10] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_84), .Q(f_ex_rd1[10]), .R(ex_flush)); FDRE \f_ex_rd1_reg[11] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_83), .Q(f_ex_rd1[11]), .R(ex_flush)); FDRE \f_ex_rd1_reg[12] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_82), .Q(f_ex_rd1[12]), .R(ex_flush)); FDRE \f_ex_rd1_reg[13] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_81), .Q(f_ex_rd1[13]), .R(ex_flush)); FDRE \f_ex_rd1_reg[14] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_80), .Q(f_ex_rd1[14]), .R(ex_flush)); FDRE \f_ex_rd1_reg[15] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_79), .Q(f_ex_rd1[15]), .R(ex_flush)); FDRE \f_ex_rd1_reg[16] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_78), .Q(f_ex_rd1[16]), .R(ex_flush)); FDRE \f_ex_rd1_reg[17] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_77), .Q(f_ex_rd1[17]), .R(ex_flush)); FDRE \f_ex_rd1_reg[18] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_76), .Q(f_ex_rd1[18]), .R(ex_flush)); FDRE \f_ex_rd1_reg[19] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_75), .Q(f_ex_rd1[19]), .R(ex_flush)); FDRE \f_ex_rd1_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_93), .Q(f_ex_rd1[1]), .R(ex_flush)); FDRE \f_ex_rd1_reg[20] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_74), .Q(f_ex_rd1[20]), .R(ex_flush)); FDRE \f_ex_rd1_reg[21] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_73), .Q(f_ex_rd1[21]), .R(ex_flush)); FDRE \f_ex_rd1_reg[22] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_72), .Q(f_ex_rd1[22]), .R(ex_flush)); FDRE \f_ex_rd1_reg[23] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_71), .Q(f_ex_rd1[23]), .R(ex_flush)); FDRE \f_ex_rd1_reg[24] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_70), .Q(f_ex_rd1[24]), .R(ex_flush)); FDRE \f_ex_rd1_reg[25] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_69), .Q(f_ex_rd1[25]), .R(ex_flush)); FDRE \f_ex_rd1_reg[26] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_68), .Q(f_ex_rd1[26]), .R(ex_flush)); FDRE \f_ex_rd1_reg[27] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_67), .Q(f_ex_rd1[27]), .R(ex_flush)); FDRE \f_ex_rd1_reg[28] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_66), .Q(f_ex_rd1[28]), .R(ex_flush)); FDRE \f_ex_rd1_reg[29] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_65), .Q(f_ex_rd1[29]), .R(ex_flush)); FDRE \f_ex_rd1_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_92), .Q(f_ex_rd1[2]), .R(ex_flush)); FDRE \f_ex_rd1_reg[30] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_64), .Q(f_ex_rd1[30]), .R(ex_flush)); FDRE \f_ex_rd1_reg[31] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_63), .Q(f_ex_rd1[31]), .R(ex_flush)); FDRE \f_ex_rd1_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_91), .Q(f_ex_rd1[3]), .R(ex_flush)); FDRE \f_ex_rd1_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_90), .Q(f_ex_rd1[4]), .R(ex_flush)); FDRE \f_ex_rd1_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_89), .Q(f_ex_rd1[5]), .R(ex_flush)); FDRE \f_ex_rd1_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_88), .Q(f_ex_rd1[6]), .R(ex_flush)); FDRE \f_ex_rd1_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_87), .Q(f_ex_rd1[7]), .R(ex_flush)); FDRE \f_ex_rd1_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_86), .Q(f_ex_rd1[8]), .R(ex_flush)); FDRE \f_ex_rd1_reg[9] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_85), .Q(f_ex_rd1[9]), .R(ex_flush)); FDRE \f_ex_rd2_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_126), .Q(f_ex_rd2[0]), .R(ex_flush)); FDRE \f_ex_rd2_reg[10] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_116), .Q(f_ex_rd2[10]), .R(ex_flush)); FDRE \f_ex_rd2_reg[11] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_115), .Q(f_ex_rd2[11]), .R(ex_flush)); FDRE \f_ex_rd2_reg[12] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_114), .Q(f_ex_rd2[12]), .R(ex_flush)); FDRE \f_ex_rd2_reg[13] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_113), .Q(f_ex_rd2[13]), .R(ex_flush)); FDRE \f_ex_rd2_reg[14] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_112), .Q(f_ex_rd2[14]), .R(ex_flush)); FDRE \f_ex_rd2_reg[15] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_111), .Q(f_ex_rd2[15]), .R(ex_flush)); FDRE \f_ex_rd2_reg[16] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_110), .Q(f_ex_rd2[16]), .R(ex_flush)); FDRE \f_ex_rd2_reg[17] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_109), .Q(f_ex_rd2[17]), .R(ex_flush)); FDRE \f_ex_rd2_reg[18] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_108), .Q(f_ex_rd2[18]), .R(ex_flush)); FDRE \f_ex_rd2_reg[19] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_107), .Q(f_ex_rd2[19]), .R(ex_flush)); FDRE \f_ex_rd2_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_125), .Q(f_ex_rd2[1]), .R(ex_flush)); FDRE \f_ex_rd2_reg[20] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_106), .Q(f_ex_rd2[20]), .R(ex_flush)); FDRE \f_ex_rd2_reg[21] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_105), .Q(f_ex_rd2[21]), .R(ex_flush)); FDRE \f_ex_rd2_reg[22] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_104), .Q(f_ex_rd2[22]), .R(ex_flush)); FDRE \f_ex_rd2_reg[23] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_103), .Q(f_ex_rd2[23]), .R(ex_flush)); FDRE \f_ex_rd2_reg[24] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_102), .Q(f_ex_rd2[24]), .R(ex_flush)); FDRE \f_ex_rd2_reg[25] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_101), .Q(f_ex_rd2[25]), .R(ex_flush)); FDRE \f_ex_rd2_reg[26] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_100), .Q(f_ex_rd2[26]), .R(ex_flush)); FDRE \f_ex_rd2_reg[27] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_99), .Q(f_ex_rd2[27]), .R(ex_flush)); FDRE \f_ex_rd2_reg[28] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_98), .Q(f_ex_rd2[28]), .R(ex_flush)); FDRE \f_ex_rd2_reg[29] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_97), .Q(f_ex_rd2[29]), .R(ex_flush)); FDRE \f_ex_rd2_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_124), .Q(f_ex_rd2[2]), .R(ex_flush)); FDRE \f_ex_rd2_reg[30] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_96), .Q(f_ex_rd2[30]), .R(ex_flush)); FDRE \f_ex_rd2_reg[31] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_95), .Q(f_ex_rd2[31]), .R(ex_flush)); FDRE \f_ex_rd2_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_123), .Q(f_ex_rd2[3]), .R(ex_flush)); FDRE \f_ex_rd2_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_122), .Q(f_ex_rd2[4]), .R(ex_flush)); FDRE \f_ex_rd2_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_121), .Q(f_ex_rd2[5]), .R(ex_flush)); FDRE \f_ex_rd2_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_120), .Q(f_ex_rd2[6]), .R(ex_flush)); FDRE \f_ex_rd2_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_119), .Q(f_ex_rd2[7]), .R(ex_flush)); FDRE \f_ex_rd2_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_118), .Q(f_ex_rd2[8]), .R(ex_flush)); FDRE \f_ex_rd2_reg[9] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_117), .Q(f_ex_rd2[9]), .R(ex_flush)); imem imem (.ADDRARDADDR({bios_mem_n_178,bios_mem_n_179,bios_mem_n_180,bios_mem_n_181,bios_mem_n_182,bios_mem_n_183,bios_mem_n_184,bios_mem_n_185,bios_mem_n_186,bios_mem_n_187,bios_mem_n_188,bios_mem_n_189,bios_mem_n_190,bios_mem_n_191}), .ALUSel(ALUSel[3:1]), .ASel(ASel), .BSel(BSel), .CO(imem_n_166), .MemRW({MemRW[3],MemRW[1:0]}), .O({imem_n_167,imem_n_168,imem_n_169,imem_n_170}), .Q({p_2_in,p_1_in,\wb_alu_reg_n_0_[29] ,p_0_in10_in,\wb_alu_reg_n_0_[27] ,\wb_alu_reg_n_0_[26] ,\wb_alu_reg_n_0_[25] ,\wb_alu_reg_n_0_[24] ,\wb_alu_reg_n_0_[23] ,\wb_alu_reg_n_0_[22] ,\wb_alu_reg_n_0_[21] ,\wb_alu_reg_n_0_[20] ,\wb_alu_reg_n_0_[19] ,\wb_alu_reg_n_0_[18] ,\wb_alu_reg_n_0_[17] ,\wb_alu_reg_n_0_[16] ,\wb_alu_reg_n_0_[15] ,\wb_alu_reg_n_0_[14] ,\wb_alu_reg_n_0_[13] ,\wb_alu_reg_n_0_[12] ,\wb_alu_reg_n_0_[11] ,\wb_alu_reg_n_0_[10] ,\wb_alu_reg_n_0_[9] ,\wb_alu_reg_n_0_[8] ,\wb_alu_reg_n_0_[7] ,\wb_alu_reg_n_0_[6] ,\wb_alu_reg_n_0_[5] ,\wb_alu_reg_n_0_[4] ,\wb_alu_reg_n_0_[3] ,\wb_alu_reg_n_0_[2] ,\wb_alu_reg_n_0_[1] ,\wb_alu_reg_n_0_[0] }), .addra({bios_mem_n_192,bios_mem_n_193}), .br(br), .br_corr_cnt_reg({br_corr_cnt_reg[29:16],br_corr_cnt_reg[14:8]}), .br_inst_cnt_reg({br_inst_cnt_reg[29:16],br_inst_cnt_reg[14:8]}), .cpu_clk(cpu_clk), .cycle_cnt_reg({cycle_cnt_reg[29:16],cycle_cnt_reg[14:8]}), .\cycle_cnt_reg[21] (imem_n_140), .\cycle_cnt_reg[25] (imem_n_144), .\cycle_cnt_reg[28] (imem_n_147), .\cycle_cnt_reg[29] (imem_n_148), .cycle_cnt_reg_12_sp_1(imem_n_132), .cycle_cnt_reg_17_sp_1(imem_n_136), .cycle_cnt_reg_8_sp_1(imem_n_124), .data2(data2[16:1]), .data3(data3[16:1]), .douta_reg_0(ALUSel[0]), .douta_reg_0_0(\alu/data0 [7:6]), .doutb(imem_doutb), .ex_alu(ex_alu[13:4]), .\ex_wb_inst_reg[2] (imem_n_117), .\ex_wb_inst_reg[3] (imem_n_76), .\ex_wb_inst_reg[3]_0 (imem_n_77), .\ex_wb_inst_reg[3]_1 (imem_n_83), .\ex_wb_inst_reg[3]_10 (imem_n_109), .\ex_wb_inst_reg[3]_11 (imem_n_110), .\ex_wb_inst_reg[3]_12 (imem_n_111), .\ex_wb_inst_reg[3]_13 (imem_n_112), .\ex_wb_inst_reg[3]_14 (imem_n_113), .\ex_wb_inst_reg[3]_15 (imem_n_114), .\ex_wb_inst_reg[3]_16 (imem_n_115), .\ex_wb_inst_reg[3]_17 (imem_n_116), .\ex_wb_inst_reg[3]_2 (imem_n_101), .\ex_wb_inst_reg[3]_3 (imem_n_102), .\ex_wb_inst_reg[3]_4 (imem_n_103), .\ex_wb_inst_reg[3]_5 (imem_n_104), .\ex_wb_inst_reg[3]_6 (imem_n_105), .\ex_wb_inst_reg[3]_7 (imem_n_106), .\ex_wb_inst_reg[3]_8 (imem_n_107), .\ex_wb_inst_reg[3]_9 (imem_n_108), .\ex_wb_inst_reg[5] (imem_n_53), .\ex_wb_inst_reg[6] (imem_n_84), .\ex_wb_pc_reg[16] (imem_n_184), .\f_ex_inst_reg[12] (imem_n_1), .\f_ex_inst_reg[12]_0 (imem_n_80), .\f_ex_inst_reg[12]_1 (imem_n_81), .\f_ex_inst_reg[14] (imem_n_185), .\f_ex_inst_reg[19] (imem_n_54), .\f_ex_inst_reg[2] (imem_n_0), .\f_ex_inst_reg[2]_0 (imem_n_5), .\f_ex_inst_reg[2]_1 (imem_n_6), .\f_ex_inst_reg[2]_10 (imem_n_119), .\f_ex_inst_reg[2]_2 (imem_n_7), .\f_ex_inst_reg[2]_3 (imem_n_8), .\f_ex_inst_reg[2]_4 (imem_n_9), .\f_ex_inst_reg[2]_5 (imem_n_10), .\f_ex_inst_reg[2]_6 (imem_n_11), .\f_ex_inst_reg[2]_7 (imem_n_12), .\f_ex_inst_reg[2]_8 (imem_n_78), .\f_ex_inst_reg[2]_9 (imem_n_79), .\f_ex_inst_reg[3] (imem_n_51), .\f_ex_inst_reg[4] (imem_n_48), .\f_ex_inst_reg[6] (imem_n_118), .\f_ex_pc_reg[11] ({imem_n_175,imem_n_176,imem_n_177,imem_n_178}), .\f_ex_pc_reg[15] (imem_n_179), .\f_ex_pc_reg[15]_0 ({imem_n_180,imem_n_181,imem_n_182,imem_n_183}), .\f_ex_pc_reg[7] ({imem_n_171,imem_n_172,imem_n_173,imem_n_174}), .\f_ex_rd2_reg[0] ({\ex_wb_inst_reg_n_0_[14] ,\ex_wb_inst_reg_n_0_[12] ,wa,p_0_in}), .imem_wea(imem_wea), .insts_cnt_reg({insts_cnt_reg[29:16],insts_cnt_reg[14:8]}), .\insts_cnt_reg[22] (imem_n_141), .\insts_cnt_reg[23] (imem_n_142), .\insts_cnt_reg[24] (imem_n_143), .\insts_cnt_reg[26] (imem_n_145), .\insts_cnt_reg[27] (imem_n_146), .insts_cnt_reg_10_sp_1(imem_n_130), .insts_cnt_reg_11_sp_1(imem_n_131), .insts_cnt_reg_13_sp_1(imem_n_133), .insts_cnt_reg_14_sp_1(imem_n_134), .insts_cnt_reg_16_sp_1(imem_n_135), .insts_cnt_reg_18_sp_1(imem_n_137), .insts_cnt_reg_19_sp_1(imem_n_138), .insts_cnt_reg_20_sp_1(imem_n_139), .insts_cnt_reg_9_sp_1(imem_n_127), .mem_reg_0_0_i_25(ex_wb_pc[16:1]), .mem_reg_0_0_i_319_0({pprev_inst[11:7],pprev_inst[5:2]}), .mem_reg_0_0_i_42__0_0(f_ex_imm[15:0]), .mem_reg_3_3_0({imem_ena,\f_ex_pc_reg_n_0_[15] ,\f_ex_pc_reg_n_0_[14] ,\f_ex_pc_reg_n_0_[13] ,\f_ex_pc_reg_n_0_[12] ,\f_ex_pc_reg_n_0_[11] ,\f_ex_pc_reg_n_0_[10] ,\f_ex_pc_reg_n_0_[9] ,\f_ex_pc_reg_n_0_[8] ,\f_ex_pc_reg_n_0_[7] ,\f_ex_pc_reg_n_0_[6] ,\f_ex_pc_reg_n_0_[5] ,\f_ex_pc_reg_n_0_[4] ,\f_ex_pc_reg_n_0_[3] ,\f_ex_pc_reg_n_0_[2] ,\f_ex_pc_reg_n_0_[1] ,\f_ex_pc_reg_n_0_[0] }), .mem_reg_3_3_1({br_pred_n_144,br_pred_n_145,br_pred_n_146,br_pred_n_147,br_pred_n_148,br_pred_n_149,br_pred_n_150,br_pred_n_151,br_pred_n_152,br_pred_n_153,br_pred_n_154,br_pred_n_155,br_pred_n_156,br_pred_n_157}), .mem_reg_3_3_i_3(pprev_data), .mem_reg_3_3_i_3_0(f_ex_rd2), .mem_reg_r1_0_31_18_23_i_24(rf_n_102), .p_1_in(dmem_din), .\pc_reg[16] (pc[16:1]), .\pprev_data_reg[21] (data2[21:17]), .wb_BrEq(wb_BrEq), .wb_BrEq_i_33(f_ex_rd1[21:0]), .wb_BrLt(wb_BrLt), .\wb_alu[29]_i_2 ({\alu/data8 [29],\alu/data8 [15:14],\alu/data8 [12:10],\alu/data8 [7:6],\alu/data8 [4]}), .\wb_alu_reg[0] (imem_n_44), .\wb_alu_reg[0]_0 (imem_n_52), .\wb_alu_reg[0]_1 (imem_n_128), .\wb_alu_reg[0]_2 (imem_n_129), .\wb_alu_reg[10] (imem_n_34), .\wb_alu_reg[10]_0 (imem_n_64), .\wb_alu_reg[11] (imem_n_33), .\wb_alu_reg[11]_0 (imem_n_65), .\wb_alu_reg[12] (imem_n_32), .\wb_alu_reg[12]_0 (imem_n_66), .\wb_alu_reg[13] (imem_n_31), .\wb_alu_reg[13]_0 (imem_n_67), .\wb_alu_reg[13]_1 (imem_n_123), .\wb_alu_reg[14] (imem_n_30), .\wb_alu_reg[14]_0 (imem_n_68), .\wb_alu_reg[15] (imem_n_29), .\wb_alu_reg[15]_0 (imem_n_69), .\wb_alu_reg[16] (imem_n_28), .\wb_alu_reg[16]_0 (imem_n_70), .\wb_alu_reg[16]_1 (imem_n_122), .\wb_alu_reg[17] (imem_n_27), .\wb_alu_reg[17]_0 (imem_n_71), .\wb_alu_reg[18] (imem_n_26), .\wb_alu_reg[18]_0 (imem_n_72), .\wb_alu_reg[19] (imem_n_25), .\wb_alu_reg[19]_0 (imem_n_73), .\wb_alu_reg[1] (imem_n_43), .\wb_alu_reg[1]_0 (imem_n_55), .\wb_alu_reg[20] (imem_n_24), .\wb_alu_reg[20]_0 (imem_n_74), .\wb_alu_reg[21] (imem_n_23), .\wb_alu_reg[21]_0 (imem_n_75), .\wb_alu_reg[22] (imem_n_22), .\wb_alu_reg[23] (imem_n_21), .\wb_alu_reg[23]_0 (imem_n_120), .\wb_alu_reg[24] (imem_n_20), .\wb_alu_reg[25] (imem_n_19), .\wb_alu_reg[26] (imem_n_18), .\wb_alu_reg[27] (imem_n_17), .\wb_alu_reg[28] (imem_n_16), .\wb_alu_reg[29] (imem_n_15), .\wb_alu_reg[2] (imem_n_42), .\wb_alu_reg[2]_0 (imem_n_56), .\wb_alu_reg[2]_1 (imem_n_125), .\wb_alu_reg[30] (imem_n_14), .\wb_alu_reg[30]_0 (imem_n_121), .\wb_alu_reg[31] (imem_n_13), .\wb_alu_reg[31]_0 ({f_ex_inst[30],f_ex_inst[24:12],f_ex_inst[6:0]}), .\wb_alu_reg[3] (imem_n_41), .\wb_alu_reg[3]_0 (imem_n_57), .\wb_alu_reg[4] (imem_n_40), .\wb_alu_reg[4]_0 (imem_n_58), .\wb_alu_reg[4]_1 (imem_n_126), .\wb_alu_reg[4]_2 (imem_n_149), .\wb_alu_reg[5] (imem_n_39), .\wb_alu_reg[5]_0 (imem_n_59), .\wb_alu_reg[6] (imem_n_38), .\wb_alu_reg[6]_0 (imem_n_60), .\wb_alu_reg[7] (imem_n_37), .\wb_alu_reg[7]_0 (imem_n_61), .\wb_alu_reg[8] (imem_n_36), .\wb_alu_reg[8]_0 (imem_n_62), .\wb_alu_reg[9] (imem_n_35), .\wb_alu_reg[9]_0 (imem_n_63), .we(we)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \insts_cnt[0]_i_1 (.I0(\insts_cnt[0]_i_3_n_0 ), .I1(\insts_cnt[0]_i_4_n_0 ), .I2(\insts_cnt[0]_i_5_n_0 ), .I3(\insts_cnt[0]_i_6_n_0 ), .I4(\ex_wb_inst_reg_n_0_[15] ), .I5(\ex_wb_inst_reg_n_0_[26] ), .O(\insts_cnt[0]_i_1_n_0 )); LUT4 #( .INIT(16'hFFFE)) \insts_cnt[0]_i_10 (.I0(\ex_wb_inst_reg_n_0_[29] ), .I1(p_0_in[4]), .I2(\ex_wb_inst_reg_n_0_[28] ), .I3(\ex_wb_inst_reg_n_0_[27] ), .O(\insts_cnt[0]_i_10_n_0 )); LUT4 #( .INIT(16'hFFFE)) \insts_cnt[0]_i_11 (.I0(p_0_in[1]), .I1(p_0_in[0]), .I2(p_0_in[2]), .I3(p_0_in[3]), .O(\insts_cnt[0]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \insts_cnt[0]_i_3 (.I0(\insts_cnt[0]_i_8_n_0 ), .I1(\ex_wb_inst_reg_n_0_[13] ), .I2(\ex_wb_inst_reg_n_0_[1] ), .I3(\ex_wb_inst_reg_n_0_[24] ), .I4(\ex_wb_inst_reg_n_0_[0] ), .I5(\insts_cnt[0]_i_9_n_0 ), .O(\insts_cnt[0]_i_3_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \insts_cnt[0]_i_4 (.I0(\ex_wb_inst_reg_n_0_[14] ), .I1(\ex_wb_inst_reg_n_0_[19] ), .I2(\ex_wb_inst_reg_n_0_[31] ), .I3(\ex_wb_inst_reg_n_0_[21] ), .I4(\insts_cnt[0]_i_10_n_0 ), .O(\insts_cnt[0]_i_4_n_0 )); LUT4 #( .INIT(16'hFFFE)) \insts_cnt[0]_i_5 (.I0(\ex_wb_inst_reg_n_0_[20] ), .I1(\ex_wb_inst_reg_n_0_[23] ), .I2(\ex_wb_inst_reg_n_0_[17] ), .I3(\ex_wb_inst_reg_n_0_[18] ), .O(\insts_cnt[0]_i_5_n_0 )); LUT2 #( .INIT(4'hE)) \insts_cnt[0]_i_6 (.I0(wa[0]), .I1(wa[1]), .O(\insts_cnt[0]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \insts_cnt[0]_i_7 (.I0(insts_cnt_reg[0]), .O(\insts_cnt[0]_i_7_n_0 )); LUT4 #( .INIT(16'hFFFE)) \insts_cnt[0]_i_8 (.I0(\ex_wb_inst_reg_n_0_[30] ), .I1(wa[3]), .I2(\ex_wb_inst_reg_n_0_[16] ), .I3(wa[2]), .O(\insts_cnt[0]_i_8_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \insts_cnt[0]_i_9 (.I0(\insts_cnt[0]_i_11_n_0 ), .I1(\ex_wb_inst_reg_n_0_[22] ), .I2(\ex_wb_inst_reg_n_0_[25] ), .I3(\ex_wb_inst_reg_n_0_[12] ), .I4(wa[4]), .O(\insts_cnt[0]_i_9_n_0 )); FDRE \insts_cnt_reg[0] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[0]_i_2_n_7 ), .Q(insts_cnt_reg[0]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \insts_cnt_reg[0]_i_2 (.CI(\<const0> ), .CO({\insts_cnt_reg[0]_i_2_n_0 ,\insts_cnt_reg[0]_i_2_n_1 ,\insts_cnt_reg[0]_i_2_n_2 ,\insts_cnt_reg[0]_i_2_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const1> }), .O({\insts_cnt_reg[0]_i_2_n_4 ,\insts_cnt_reg[0]_i_2_n_5 ,\insts_cnt_reg[0]_i_2_n_6 ,\insts_cnt_reg[0]_i_2_n_7 }), .S({insts_cnt_reg[3:1],\insts_cnt[0]_i_7_n_0 })); FDRE \insts_cnt_reg[10] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[8]_i_1_n_5 ), .Q(insts_cnt_reg[10]), .R(cnt_reset)); FDRE \insts_cnt_reg[11] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[8]_i_1_n_4 ), .Q(insts_cnt_reg[11]), .R(cnt_reset)); FDRE \insts_cnt_reg[12] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[12]_i_1_n_7 ), .Q(insts_cnt_reg[12]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \insts_cnt_reg[12]_i_1 (.CI(\insts_cnt_reg[8]_i_1_n_0 ), .CO({\insts_cnt_reg[12]_i_1_n_0 ,\insts_cnt_reg[12]_i_1_n_1 ,\insts_cnt_reg[12]_i_1_n_2 ,\insts_cnt_reg[12]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\insts_cnt_reg[12]_i_1_n_4 ,\insts_cnt_reg[12]_i_1_n_5 ,\insts_cnt_reg[12]_i_1_n_6 ,\insts_cnt_reg[12]_i_1_n_7 }), .S(insts_cnt_reg[15:12])); FDRE \insts_cnt_reg[13] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[12]_i_1_n_6 ), .Q(insts_cnt_reg[13]), .R(cnt_reset)); FDRE \insts_cnt_reg[14] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[12]_i_1_n_5 ), .Q(insts_cnt_reg[14]), .R(cnt_reset)); FDRE \insts_cnt_reg[15] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[12]_i_1_n_4 ), .Q(insts_cnt_reg[15]), .R(cnt_reset)); FDRE \insts_cnt_reg[16] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[16]_i_1_n_7 ), .Q(insts_cnt_reg[16]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \insts_cnt_reg[16]_i_1 (.CI(\insts_cnt_reg[12]_i_1_n_0 ), .CO({\insts_cnt_reg[16]_i_1_n_0 ,\insts_cnt_reg[16]_i_1_n_1 ,\insts_cnt_reg[16]_i_1_n_2 ,\insts_cnt_reg[16]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\insts_cnt_reg[16]_i_1_n_4 ,\insts_cnt_reg[16]_i_1_n_5 ,\insts_cnt_reg[16]_i_1_n_6 ,\insts_cnt_reg[16]_i_1_n_7 }), .S(insts_cnt_reg[19:16])); FDRE \insts_cnt_reg[17] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[16]_i_1_n_6 ), .Q(insts_cnt_reg[17]), .R(cnt_reset)); FDRE \insts_cnt_reg[18] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[16]_i_1_n_5 ), .Q(insts_cnt_reg[18]), .R(cnt_reset)); FDRE \insts_cnt_reg[19] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[16]_i_1_n_4 ), .Q(insts_cnt_reg[19]), .R(cnt_reset)); FDRE \insts_cnt_reg[1] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[0]_i_2_n_6 ), .Q(insts_cnt_reg[1]), .R(cnt_reset)); FDRE \insts_cnt_reg[20] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[20]_i_1_n_7 ), .Q(insts_cnt_reg[20]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \insts_cnt_reg[20]_i_1 (.CI(\insts_cnt_reg[16]_i_1_n_0 ), .CO({\insts_cnt_reg[20]_i_1_n_0 ,\insts_cnt_reg[20]_i_1_n_1 ,\insts_cnt_reg[20]_i_1_n_2 ,\insts_cnt_reg[20]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\insts_cnt_reg[20]_i_1_n_4 ,\insts_cnt_reg[20]_i_1_n_5 ,\insts_cnt_reg[20]_i_1_n_6 ,\insts_cnt_reg[20]_i_1_n_7 }), .S(insts_cnt_reg[23:20])); FDRE \insts_cnt_reg[21] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[20]_i_1_n_6 ), .Q(insts_cnt_reg[21]), .R(cnt_reset)); FDRE \insts_cnt_reg[22] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[20]_i_1_n_5 ), .Q(insts_cnt_reg[22]), .R(cnt_reset)); FDRE \insts_cnt_reg[23] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[20]_i_1_n_4 ), .Q(insts_cnt_reg[23]), .R(cnt_reset)); FDRE \insts_cnt_reg[24] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[24]_i_1_n_7 ), .Q(insts_cnt_reg[24]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \insts_cnt_reg[24]_i_1 (.CI(\insts_cnt_reg[20]_i_1_n_0 ), .CO({\insts_cnt_reg[24]_i_1_n_0 ,\insts_cnt_reg[24]_i_1_n_1 ,\insts_cnt_reg[24]_i_1_n_2 ,\insts_cnt_reg[24]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\insts_cnt_reg[24]_i_1_n_4 ,\insts_cnt_reg[24]_i_1_n_5 ,\insts_cnt_reg[24]_i_1_n_6 ,\insts_cnt_reg[24]_i_1_n_7 }), .S(insts_cnt_reg[27:24])); FDRE \insts_cnt_reg[25] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[24]_i_1_n_6 ), .Q(insts_cnt_reg[25]), .R(cnt_reset)); FDRE \insts_cnt_reg[26] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[24]_i_1_n_5 ), .Q(insts_cnt_reg[26]), .R(cnt_reset)); FDRE \insts_cnt_reg[27] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[24]_i_1_n_4 ), .Q(insts_cnt_reg[27]), .R(cnt_reset)); FDRE \insts_cnt_reg[28] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[28]_i_1_n_7 ), .Q(insts_cnt_reg[28]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \insts_cnt_reg[28]_i_1 (.CI(\insts_cnt_reg[24]_i_1_n_0 ), .CO({\insts_cnt_reg[28]_i_1_n_1 ,\insts_cnt_reg[28]_i_1_n_2 ,\insts_cnt_reg[28]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\insts_cnt_reg[28]_i_1_n_4 ,\insts_cnt_reg[28]_i_1_n_5 ,\insts_cnt_reg[28]_i_1_n_6 ,\insts_cnt_reg[28]_i_1_n_7 }), .S(insts_cnt_reg[31:28])); FDRE \insts_cnt_reg[29] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[28]_i_1_n_6 ), .Q(insts_cnt_reg[29]), .R(cnt_reset)); FDRE \insts_cnt_reg[2] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[0]_i_2_n_5 ), .Q(insts_cnt_reg[2]), .R(cnt_reset)); FDRE \insts_cnt_reg[30] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[28]_i_1_n_5 ), .Q(insts_cnt_reg[30]), .R(cnt_reset)); FDRE \insts_cnt_reg[31] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[28]_i_1_n_4 ), .Q(insts_cnt_reg[31]), .R(cnt_reset)); FDRE \insts_cnt_reg[3] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[0]_i_2_n_4 ), .Q(insts_cnt_reg[3]), .R(cnt_reset)); FDRE \insts_cnt_reg[4] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[4]_i_1_n_7 ), .Q(insts_cnt_reg[4]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \insts_cnt_reg[4]_i_1 (.CI(\insts_cnt_reg[0]_i_2_n_0 ), .CO({\insts_cnt_reg[4]_i_1_n_0 ,\insts_cnt_reg[4]_i_1_n_1 ,\insts_cnt_reg[4]_i_1_n_2 ,\insts_cnt_reg[4]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\insts_cnt_reg[4]_i_1_n_4 ,\insts_cnt_reg[4]_i_1_n_5 ,\insts_cnt_reg[4]_i_1_n_6 ,\insts_cnt_reg[4]_i_1_n_7 }), .S(insts_cnt_reg[7:4])); FDRE \insts_cnt_reg[5] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[4]_i_1_n_6 ), .Q(insts_cnt_reg[5]), .R(cnt_reset)); FDRE \insts_cnt_reg[6] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[4]_i_1_n_5 ), .Q(insts_cnt_reg[6]), .R(cnt_reset)); FDRE \insts_cnt_reg[7] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[4]_i_1_n_4 ), .Q(insts_cnt_reg[7]), .R(cnt_reset)); FDRE \insts_cnt_reg[8] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[8]_i_1_n_7 ), .Q(insts_cnt_reg[8]), .R(cnt_reset)); (* ADDER_THRESHOLD = "11" *) CARRY4 \insts_cnt_reg[8]_i_1 (.CI(\insts_cnt_reg[4]_i_1_n_0 ), .CO({\insts_cnt_reg[8]_i_1_n_0 ,\insts_cnt_reg[8]_i_1_n_1 ,\insts_cnt_reg[8]_i_1_n_2 ,\insts_cnt_reg[8]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\insts_cnt_reg[8]_i_1_n_4 ,\insts_cnt_reg[8]_i_1_n_5 ,\insts_cnt_reg[8]_i_1_n_6 ,\insts_cnt_reg[8]_i_1_n_7 }), .S(insts_cnt_reg[11:8])); FDRE \insts_cnt_reg[9] (.C(cpu_clk), .CE(\insts_cnt[0]_i_1_n_0 ), .D(\insts_cnt_reg[8]_i_1_n_6 ), .Q(insts_cnt_reg[9]), .R(cnt_reset)); uart on_chip_uart (.ALUSel(ALUSel[3:1]), .Q({f_ex_inst[12],f_ex_inst[6:2]}), .SR(bios_mem_n_118), .\bit_counter[3]_i_21 ({\alu/data0 [31:30],\alu/data0 [23:20]}), .\bit_counter[3]_i_33 (imem_n_1), .\bit_counter[3]_i_33_0 ({\alu/data8 [27:24],\alu/data8 [1]}), .br_corr_cnt_reg({br_corr_cnt_reg[7:2],br_corr_cnt_reg[0]}), .\br_corr_cnt_reg[7] (on_chip_uart_n_44), .br_inst_cnt_reg(br_inst_cnt_reg[7:0]), .br_inst_cnt_reg_0_sp_1(on_chip_uart_n_37), .br_inst_cnt_reg_2_sp_1(on_chip_uart_n_46), .br_inst_cnt_reg_3_sp_1(on_chip_uart_n_47), .br_inst_cnt_reg_4_sp_1(on_chip_uart_n_48), .buttons_pressed(buttons_pressed), .cpu_clk(cpu_clk), .cpu_clk_locked(cpu_clk_locked), .cpu_reset(cpu_reset), .cycle_cnt_reg(cycle_cnt_reg[7:1]), .dout({dmem_dout[7],dmem_dout[1:0]}), .\f_ex_inst_reg[12] (ALUSel[0]), .\f_ex_inst_reg[12]_0 (on_chip_uart_n_29), .\f_ex_inst_reg[12]_1 (on_chip_uart_n_30), .\f_ex_inst_reg[12]_2 (on_chip_uart_n_31), .\f_ex_inst_reg[12]_3 (on_chip_uart_n_32), .\f_ex_inst_reg[13] (on_chip_uart_n_33), .\f_ex_inst_reg[14] (on_chip_uart_n_27), .\f_ex_inst_reg[14]_0 (on_chip_uart_n_28), .\f_ex_inst_reg[2] (on_chip_uart_n_8), .\f_ex_inst_reg[2]_0 (on_chip_uart_n_9), .\f_ex_inst_reg[2]_1 (on_chip_uart_n_10), .\f_ex_inst_reg[2]_2 (on_chip_uart_n_11), .\f_ex_inst_reg[2]_3 (on_chip_uart_n_12), .\f_ex_inst_reg[2]_4 (on_chip_uart_n_13), .has_byte_reg(imem_n_121), .has_byte_reg_0(p_0_in), .has_byte_reg_1(imem_n_122), .has_byte_reg_2(imem_n_123), .insts_cnt_reg(insts_cnt_reg[7:2]), .\insts_cnt_reg[6] (on_chip_uart_n_43), .\insts_cnt_reg[7] (on_chip_uart_n_45), .insts_cnt_reg_2_sp_1(on_chip_uart_n_39), .insts_cnt_reg_3_sp_1(on_chip_uart_n_40), .insts_cnt_reg_4_sp_1(on_chip_uart_n_41), .insts_cnt_reg_5_sp_1(on_chip_uart_n_42), .mem_reg_0_0_i_316(imem_n_149), .mem_reg_0_0_i_316_0(rf_n_99), .mem_reg_0_0_i_316_1(imem_n_125), .mem_reg_0_0_i_321(rf_n_95), .mem_reg_r1_0_31_0_5_i_14(imem_n_120), .mem_reg_r1_0_31_0_5_i_14_0(rf_n_102), .mem_reg_r1_0_31_0_5_i_14_1(rf_n_101), .mem_reg_r1_0_31_0_5_i_20(imem_n_128), .mem_reg_r1_0_31_0_5_i_58(imem_n_126), .mem_reg_r1_0_31_0_5_i_58_0(rf_n_100), .mem_reg_r1_0_31_12_17_i_14({doutb_reg[7],doutb_reg[1:0]}), .mem_reg_r1_0_31_6_11_i_7(imem_n_129), .mem_wb_mux({mem_wb_mux[7],mem_wb_mux[1:0]}), .\rx_shift_reg[2] (on_chip_uart_n_38), .serial_in(serial_in), .serial_out(serial_out), .start(\uatransmit/start ), .symbol_edge__7(\uatransmit/symbol_edge__7 ), .tx_running__2(\uatransmit/tx_running__2 ), .\tx_shift_reg[0] (bios_mem_n_116), .\tx_shift_reg[7] (p_1_in_0), .\tx_shift_reg[8] (tx_shift), .\tx_shift_reg[8]_0 (bios_mem_n_225), .wb_BrEq_i_35(imem_n_53), .wb_BrEq_i_35_0(imem_n_54), .wb_BrLt_i_14({p_2_in,p_1_in,\wb_alu_reg_n_0_[29] ,p_0_in10_in,\wb_alu_reg_n_0_[27] ,\wb_alu_reg_n_0_[26] ,\wb_alu_reg_n_0_[25] ,\wb_alu_reg_n_0_[24] ,\wb_alu_reg_n_0_[23] ,\wb_alu_reg_n_0_[22] ,\wb_alu_reg_n_0_[5] ,\wb_alu_reg_n_0_[4] ,\wb_alu_reg_n_0_[3] ,\wb_alu_reg_n_0_[2] ,\wb_alu_reg_n_0_[1] ,\wb_alu_reg_n_0_[0] }), .wb_BrLt_i_14_0(f_ex_rd1[31:22]), .wb_BrLt_i_14_1(pprev_data[31:22]), .\wb_alu_reg[22] (on_chip_uart_n_17), .\wb_alu_reg[23] (on_chip_uart_n_18), .\wb_alu_reg[24] (on_chip_uart_n_19), .\wb_alu_reg[25] (on_chip_uart_n_20), .\wb_alu_reg[26] (on_chip_uart_n_21), .\wb_alu_reg[27] (on_chip_uart_n_22), .\wb_alu_reg[28] (on_chip_uart_n_23), .\wb_alu_reg[29] (on_chip_uart_n_24), .\wb_alu_reg[30] (on_chip_uart_n_25), .\wb_alu_reg[31] (on_chip_uart_n_26)); FDRE \pc_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_159), .Q(pc[0]), .R(\<const0> )); FDRE \pc_reg[10] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_149), .Q(pc[10]), .R(\<const0> )); FDRE \pc_reg[11] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_148), .Q(pc[11]), .R(\<const0> )); FDRE \pc_reg[12] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_147), .Q(pc[12]), .R(\<const0> )); FDRE \pc_reg[13] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_146), .Q(pc[13]), .R(\<const0> )); FDRE \pc_reg[14] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_145), .Q(pc[14]), .R(\<const0> )); FDRE \pc_reg[15] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_144), .Q(pc[15]), .R(\<const0> )); FDRE \pc_reg[16] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_143), .Q(pc[16]), .R(\<const0> )); FDRE \pc_reg[17] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_142), .Q(pc[17]), .R(\<const0> )); FDRE \pc_reg[18] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_141), .Q(pc[18]), .R(\<const0> )); FDRE \pc_reg[19] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_140), .Q(pc[19]), .R(\<const0> )); FDRE \pc_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_158), .Q(pc[1]), .R(\<const0> )); FDRE \pc_reg[20] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_139), .Q(pc[20]), .R(\<const0> )); FDRE \pc_reg[21] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_138), .Q(pc[21]), .R(\<const0> )); FDRE \pc_reg[22] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_137), .Q(pc[22]), .R(\<const0> )); FDRE \pc_reg[23] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_136), .Q(pc[23]), .R(\<const0> )); FDRE \pc_reg[24] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_135), .Q(pc[24]), .R(\<const0> )); FDRE \pc_reg[25] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_134), .Q(pc[25]), .R(\<const0> )); FDRE \pc_reg[26] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_133), .Q(pc[26]), .R(\<const0> )); FDRE \pc_reg[27] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_132), .Q(pc[27]), .R(\<const0> )); FDRE \pc_reg[28] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_131), .Q(pc[28]), .R(\<const0> )); FDRE \pc_reg[29] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_130), .Q(pc[29]), .R(\<const0> )); FDRE \pc_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_157), .Q(pc[2]), .R(\<const0> )); FDRE \pc_reg[30] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_129), .Q(pc[30]), .R(\<const0> )); FDRE \pc_reg[31] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_128), .Q(pc[31]), .R(\<const0> )); FDRE \pc_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_156), .Q(pc[3]), .R(\<const0> )); FDRE \pc_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_155), .Q(pc[4]), .R(\<const0> )); FDRE \pc_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_154), .Q(pc[5]), .R(\<const0> )); FDRE \pc_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_153), .Q(pc[6]), .R(\<const0> )); FDRE \pc_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_152), .Q(pc[7]), .R(\<const0> )); FDRE \pc_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_151), .Q(pc[8]), .R(\<const0> )); FDRE \pc_reg[9] (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_n_150), .Q(pc[9]), .R(\<const0> )); FDRE \pprev_data_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[0]), .Q(pprev_data[0]), .R(cpu_reset)); FDRE \pprev_data_reg[10] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[10]), .Q(pprev_data[10]), .R(cpu_reset)); FDRE \pprev_data_reg[11] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[11]), .Q(pprev_data[11]), .R(cpu_reset)); FDRE \pprev_data_reg[12] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[12]), .Q(pprev_data[12]), .R(cpu_reset)); FDRE \pprev_data_reg[13] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[13]), .Q(pprev_data[13]), .R(cpu_reset)); FDRE \pprev_data_reg[14] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[14]), .Q(pprev_data[14]), .R(cpu_reset)); FDRE \pprev_data_reg[15] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[15]), .Q(pprev_data[15]), .R(cpu_reset)); FDRE \pprev_data_reg[16] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[16]), .Q(pprev_data[16]), .R(cpu_reset)); FDRE \pprev_data_reg[17] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[17]), .Q(pprev_data[17]), .R(cpu_reset)); FDRE \pprev_data_reg[18] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[18]), .Q(pprev_data[18]), .R(cpu_reset)); FDRE \pprev_data_reg[19] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[19]), .Q(pprev_data[19]), .R(cpu_reset)); FDRE \pprev_data_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[1]), .Q(pprev_data[1]), .R(cpu_reset)); FDRE \pprev_data_reg[20] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[20]), .Q(pprev_data[20]), .R(cpu_reset)); FDRE \pprev_data_reg[21] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[21]), .Q(pprev_data[21]), .R(cpu_reset)); FDRE \pprev_data_reg[22] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[22]), .Q(pprev_data[22]), .R(cpu_reset)); FDRE \pprev_data_reg[23] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[23]), .Q(pprev_data[23]), .R(cpu_reset)); FDRE \pprev_data_reg[24] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[24]), .Q(pprev_data[24]), .R(cpu_reset)); FDRE \pprev_data_reg[25] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[25]), .Q(pprev_data[25]), .R(cpu_reset)); FDRE \pprev_data_reg[26] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[26]), .Q(pprev_data[26]), .R(cpu_reset)); FDRE \pprev_data_reg[27] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[27]), .Q(pprev_data[27]), .R(cpu_reset)); FDRE \pprev_data_reg[28] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[28]), .Q(pprev_data[28]), .R(cpu_reset)); FDRE \pprev_data_reg[29] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[29]), .Q(pprev_data[29]), .R(cpu_reset)); FDRE \pprev_data_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[2]), .Q(pprev_data[2]), .R(cpu_reset)); FDRE \pprev_data_reg[30] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[30]), .Q(pprev_data[30]), .R(cpu_reset)); FDRE \pprev_data_reg[31] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[31]), .Q(pprev_data[31]), .R(cpu_reset)); FDRE \pprev_data_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[3]), .Q(pprev_data[3]), .R(cpu_reset)); FDRE \pprev_data_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[4]), .Q(pprev_data[4]), .R(cpu_reset)); FDRE \pprev_data_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[5]), .Q(pprev_data[5]), .R(cpu_reset)); FDRE \pprev_data_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[6]), .Q(pprev_data[6]), .R(cpu_reset)); FDRE \pprev_data_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[7]), .Q(pprev_data[7]), .R(cpu_reset)); FDRE \pprev_data_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[8]), .Q(pprev_data[8]), .R(cpu_reset)); FDRE \pprev_data_reg[9] (.C(cpu_clk), .CE(\<const1> ), .D(wb_mux[9]), .Q(pprev_data[9]), .R(cpu_reset)); FDRE \pprev_inst_reg[10] (.C(cpu_clk), .CE(\<const1> ), .D(wa[3]), .Q(pprev_inst[10]), .R(cpu_reset)); FDRE \pprev_inst_reg[11] (.C(cpu_clk), .CE(\<const1> ), .D(wa[4]), .Q(pprev_inst[11]), .R(cpu_reset)); FDRE \pprev_inst_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in[0]), .Q(pprev_inst[2]), .R(cpu_reset)); FDRE \pprev_inst_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in[1]), .Q(pprev_inst[3]), .R(cpu_reset)); FDRE \pprev_inst_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in[2]), .Q(pprev_inst[4]), .R(cpu_reset)); FDRE \pprev_inst_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in[3]), .Q(pprev_inst[5]), .R(cpu_reset)); FDRE \pprev_inst_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(wa[0]), .Q(pprev_inst[7]), .R(cpu_reset)); FDRE \pprev_inst_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(wa[1]), .Q(pprev_inst[8]), .R(cpu_reset)); FDRE \pprev_inst_reg[9] (.C(cpu_clk), .CE(\<const1> ), .D(wa[2]), .Q(pprev_inst[9]), .R(cpu_reset)); reg_file rf (.CO(imem_n_166), .D(wb_mux), .Q({wa,p_0_in}), .br_corr_cnt_reg({br_corr_cnt_reg[31:30],br_corr_cnt_reg[15],br_corr_cnt_reg[1]}), .br_corr_cnt_reg_1_sp_1(rf_n_99), .br_inst_cnt_reg({br_inst_cnt_reg[31:30],br_inst_cnt_reg[15]}), .cpu_clk(cpu_clk), .cycle_cnt_reg({cycle_cnt_reg[31:30],cycle_cnt_reg[15],cycle_cnt_reg[0]}), .data2(data2[4:1]), .data3(data3[31:17]), .\ex_wb_inst_reg[3] (rf_n_66), .\ex_wb_inst_reg[3]_0 (rf_n_67), .\ex_wb_inst_reg[3]_1 (rf_n_68), .\ex_wb_inst_reg[3]_10 (rf_n_92), .\ex_wb_inst_reg[3]_11 (rf_n_93), .\ex_wb_inst_reg[3]_12 (rf_n_94), .\ex_wb_inst_reg[3]_2 (rf_n_69), .\ex_wb_inst_reg[3]_3 (rf_n_70), .\ex_wb_inst_reg[3]_4 (rf_n_86), .\ex_wb_inst_reg[3]_5 (rf_n_87), .\ex_wb_inst_reg[3]_6 (rf_n_88), .\ex_wb_inst_reg[3]_7 (rf_n_89), .\ex_wb_inst_reg[3]_8 (rf_n_90), .\ex_wb_inst_reg[3]_9 (rf_n_91), .\ex_wb_pc_reg[0] (rf_n_65), .\ex_wb_pc_reg[31] (data2[31:17]), .f_ex_imm(f_ex_imm[31:16]), .\f_ex_pc_reg[19] ({rf_n_118,rf_n_119,rf_n_120,rf_n_121}), .\f_ex_pc_reg[23] ({rf_n_122,rf_n_123,rf_n_124,rf_n_125}), .\f_ex_pc_reg[27] ({rf_n_126,rf_n_127,rf_n_128,rf_n_129}), .\f_ex_pc_reg[30] ({rf_n_130,rf_n_131,rf_n_132,rf_n_133}), .\f_ex_rd2_reg[25] ({ra2,ra1}), .insts_cnt_reg({insts_cnt_reg[31:30],insts_cnt_reg[15],insts_cnt_reg[1:0]}), .\insts_cnt_reg[15] (rf_n_96), .\insts_cnt_reg[30] (rf_n_97), .\insts_cnt_reg[31] (rf_n_98), .insts_cnt_reg_0_sp_1(rf_n_95), .mem_reg_r1_0_31_0_5_i_58(imem_n_128), .mem_reg_r1_0_31_0_5_i_58_0(imem_n_129), .mem_reg_r1_0_31_6_11_i_36_0(imem_n_125), .mem_reg_r1_0_31_6_11_i_36_1(imem_n_126), .\pc[16]_i_2 (imem_n_179), .\pc[17]_i_2 (imem_n_184), .\pc[29]_i_2 ({ex_wb_pc[31:17],ex_wb_pc[0]}), .\pc_reg[31] (pc[31:17]), .\pc_reg[31]_i_4_0 ({\f_ex_pc_reg_n_0_[31] ,imem_ena,\f_ex_pc_reg_n_0_[29] ,\f_ex_pc_reg_n_0_[28] ,\f_ex_pc_reg_n_0_[27] ,\f_ex_pc_reg_n_0_[26] ,\f_ex_pc_reg_n_0_[25] ,\f_ex_pc_reg_n_0_[24] ,\f_ex_pc_reg_n_0_[23] ,\f_ex_pc_reg_n_0_[22] ,\f_ex_pc_reg_n_0_[21] ,\f_ex_pc_reg_n_0_[20] ,\f_ex_pc_reg_n_0_[19] ,\f_ex_pc_reg_n_0_[18] ,\f_ex_pc_reg_n_0_[17] ,\f_ex_pc_reg_n_0_[16] }), .\pprev_data_reg[0] (imem_n_84), .\pprev_data_reg[31] ({p_2_in,p_1_in,\wb_alu_reg_n_0_[29] ,p_0_in10_in,\wb_alu_reg_n_0_[27] ,\wb_alu_reg_n_0_[26] ,\wb_alu_reg_n_0_[25] ,\wb_alu_reg_n_0_[24] ,\wb_alu_reg_n_0_[23] ,\wb_alu_reg_n_0_[22] ,\wb_alu_reg_n_0_[5] ,\wb_alu_reg_n_0_[4] ,\wb_alu_reg_n_0_[3] ,\wb_alu_reg_n_0_[2] ,\wb_alu_reg_n_0_[1] ,\wb_alu_reg_n_0_[0] }), .rd10(rd10), .rd20(rd20), .\wb_alu_reg[29] (rf_n_101), .\wb_alu_reg[2] (rf_n_100), .\wb_alu_reg[31] (rf_n_102), .we(we)); LUT3 #( .INIT(8'hB8)) wb_BrEq_i_1 (.I0(bios_mem_n_199), .I1(f_ex_inst[13]), .I2(bios_mem_n_198), .O(BrEq)); FDRE wb_BrEq_reg (.C(cpu_clk), .CE(\<const1> ), .D(BrEq), .Q(wb_BrEq), .R(ex_wb_pc0)); FDRE wb_BrLt_reg (.C(cpu_clk), .CE(\<const1> ), .D(BrLt), .Q(wb_BrLt), .R(ex_wb_pc0)); FDRE \wb_alu_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[0]), .Q(\wb_alu_reg_n_0_[0] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[10] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[10]), .Q(\wb_alu_reg_n_0_[10] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[11] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[11]), .Q(\wb_alu_reg_n_0_[11] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[12] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[12]), .Q(\wb_alu_reg_n_0_[12] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[13] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[13]), .Q(\wb_alu_reg_n_0_[13] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[14] (.C(cpu_clk), .CE(\<const1> ), .D(bios_mem_n_179), .Q(\wb_alu_reg_n_0_[14] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[15] (.C(cpu_clk), .CE(\<const1> ), .D(bios_mem_n_178), .Q(\wb_alu_reg_n_0_[15] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[16] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[16]), .Q(\wb_alu_reg_n_0_[16] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[17] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[17]), .Q(\wb_alu_reg_n_0_[17] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[18] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[18]), .Q(\wb_alu_reg_n_0_[18] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[19] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[19]), .Q(\wb_alu_reg_n_0_[19] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[1]), .Q(\wb_alu_reg_n_0_[1] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[20] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[20]), .Q(\wb_alu_reg_n_0_[20] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[21] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[21]), .Q(\wb_alu_reg_n_0_[21] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[22] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[22]), .Q(\wb_alu_reg_n_0_[22] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[23] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[23]), .Q(\wb_alu_reg_n_0_[23] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[24] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[24]), .Q(\wb_alu_reg_n_0_[24] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[25] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[25]), .Q(\wb_alu_reg_n_0_[25] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[26] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[26]), .Q(\wb_alu_reg_n_0_[26] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[27] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[27]), .Q(\wb_alu_reg_n_0_[27] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[28] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[28]), .Q(p_0_in10_in), .R(ex_wb_pc0)); FDRE \wb_alu_reg[29] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[29]), .Q(\wb_alu_reg_n_0_[29] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[2]), .Q(\wb_alu_reg_n_0_[2] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[30] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[30]), .Q(p_1_in), .R(ex_wb_pc0)); FDRE \wb_alu_reg[31] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[31]), .Q(p_2_in), .R(ex_wb_pc0)); FDRE \wb_alu_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[3]), .Q(\wb_alu_reg_n_0_[3] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[4]), .Q(\wb_alu_reg_n_0_[4] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[5]), .Q(\wb_alu_reg_n_0_[5] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[6]), .Q(\wb_alu_reg_n_0_[6] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[7]), .Q(\wb_alu_reg_n_0_[7] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[8]), .Q(\wb_alu_reg_n_0_[8] ), .R(ex_wb_pc0)); FDRE \wb_alu_reg[9] (.C(cpu_clk), .CE(\<const1> ), .D(ex_alu[9]), .Q(\wb_alu_reg_n_0_[9] ), .R(ex_wb_pc0)); LUT5 #( .INIT(32'hFFFF1F40)) wb_br_taken_i_1 (.I0(br_pred_n_62), .I1(wb_br_taken), .I2(SWITCHES_IBUF), .I3(br), .I4(wb_br_taken_i_3_n_0), .O(ex_wb_pc0)); LUT6 #( .INIT(64'hDDDDFDDDDDDDDDDD)) wb_br_taken_i_3 (.I0(cpu_clk_locked), .I1(buttons_pressed), .I2(p_0_in[0]), .I3(p_0_in[3]), .I4(p_0_in[2]), .I5(p_0_in[4]), .O(wb_br_taken_i_3_n_0)); FDRE wb_br_taken_reg (.C(cpu_clk), .CE(\<const1> ), .D(br_pred_taken), .Q(wb_br_taken), .R(ex_wb_pc0)); endmodule module debouncer (\saturating_counter_reg[0][8]_0 , debounced_signals, cpu_clk, pulse, SR); output \saturating_counter_reg[0][8]_0 ; output [0:0]debounced_signals; input cpu_clk; input [0:0]pulse; input [0:0]SR; wire \<const0> ; wire \<const1> ; wire [0:0]SR; wire cpu_clk; wire [0:0]debounced_signals; wire en; wire [9:0]p_0_in; wire p_0_out; wire [0:0]pulse; wire \pulse[0]_i_2_n_0 ; wire \saturating_counter[0][9]_i_4_n_0 ; wire \saturating_counter_reg[0][8]_0 ; wire [9:3]\saturating_counter_reg[0]_0 ; wire \saturating_counter_reg_n_0_[0][0] ; wire \saturating_counter_reg_n_0_[0][1] ; wire \saturating_counter_reg_n_0_[0][2] ; wire \wrapping_counter[0]_i_3_n_0 ; wire \wrapping_counter[0]_i_4_n_0 ; wire \wrapping_counter[0]_i_5_n_0 ; wire [14:3]wrapping_counter_reg; wire \wrapping_counter_reg[0]_i_2_n_0 ; wire \wrapping_counter_reg[0]_i_2_n_1 ; wire \wrapping_counter_reg[0]_i_2_n_2 ; wire \wrapping_counter_reg[0]_i_2_n_3 ; wire \wrapping_counter_reg[0]_i_2_n_4 ; wire \wrapping_counter_reg[0]_i_2_n_5 ; wire \wrapping_counter_reg[0]_i_2_n_6 ; wire \wrapping_counter_reg[0]_i_2_n_7 ; wire \wrapping_counter_reg[12]_i_1_n_2 ; wire \wrapping_counter_reg[12]_i_1_n_3 ; wire \wrapping_counter_reg[12]_i_1_n_5 ; wire \wrapping_counter_reg[12]_i_1_n_6 ; wire \wrapping_counter_reg[12]_i_1_n_7 ; wire \wrapping_counter_reg[4]_i_1_n_0 ; wire \wrapping_counter_reg[4]_i_1_n_1 ; wire \wrapping_counter_reg[4]_i_1_n_2 ; wire \wrapping_counter_reg[4]_i_1_n_3 ; wire \wrapping_counter_reg[4]_i_1_n_4 ; wire \wrapping_counter_reg[4]_i_1_n_5 ; wire \wrapping_counter_reg[4]_i_1_n_6 ; wire \wrapping_counter_reg[4]_i_1_n_7 ; wire \wrapping_counter_reg[8]_i_1_n_0 ; wire \wrapping_counter_reg[8]_i_1_n_1 ; wire \wrapping_counter_reg[8]_i_1_n_2 ; wire \wrapping_counter_reg[8]_i_1_n_3 ; wire \wrapping_counter_reg[8]_i_1_n_4 ; wire \wrapping_counter_reg[8]_i_1_n_5 ; wire \wrapping_counter_reg[8]_i_1_n_6 ; wire \wrapping_counter_reg[8]_i_1_n_7 ; wire \wrapping_counter_reg_n_0_[0] ; wire \wrapping_counter_reg_n_0_[1] ; wire \wrapping_counter_reg_n_0_[2] ; GND GND (.G(\<const0> )); VCC VCC (.P(\<const1> )); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT4 #( .INIT(16'h00FE)) \out[0]_i_1 (.I0(\pulse[0]_i_2_n_0 ), .I1(\saturating_counter_reg[0]_0 [8]), .I2(\saturating_counter_reg[0]_0 [9]), .I3(pulse), .O(\saturating_counter_reg[0][8]_0 )); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT3 #( .INIT(8'hFE)) \pulse[0]_i_1 (.I0(\saturating_counter_reg[0]_0 [9]), .I1(\saturating_counter_reg[0]_0 [8]), .I2(\pulse[0]_i_2_n_0 ), .O(debounced_signals)); LUT5 #( .INIT(32'h88888880)) \pulse[0]_i_2 (.I0(\saturating_counter_reg[0]_0 [7]), .I1(\saturating_counter_reg[0]_0 [6]), .I2(\saturating_counter_reg[0]_0 [4]), .I3(\saturating_counter_reg[0]_0 [5]), .I4(\saturating_counter_reg[0]_0 [3]), .O(\pulse[0]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \saturating_counter[0][0]_i_1 (.I0(\saturating_counter_reg_n_0_[0][0] ), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT2 #( .INIT(4'h6)) \saturating_counter[0][1]_i_1 (.I0(\saturating_counter_reg_n_0_[0][0] ), .I1(\saturating_counter_reg_n_0_[0][1] ), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT3 #( .INIT(8'h78)) \saturating_counter[0][2]_i_1 (.I0(\saturating_counter_reg_n_0_[0][0] ), .I1(\saturating_counter_reg_n_0_[0][1] ), .I2(\saturating_counter_reg_n_0_[0][2] ), .O(p_0_in[2])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT4 #( .INIT(16'h7F80)) \saturating_counter[0][3]_i_1 (.I0(\saturating_counter_reg_n_0_[0][1] ), .I1(\saturating_counter_reg_n_0_[0][0] ), .I2(\saturating_counter_reg_n_0_[0][2] ), .I3(\saturating_counter_reg[0]_0 [3]), .O(p_0_in[3])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT5 #( .INIT(32'h7FFF8000)) \saturating_counter[0][4]_i_1 (.I0(\saturating_counter_reg[0]_0 [3]), .I1(\saturating_counter_reg_n_0_[0][2] ), .I2(\saturating_counter_reg_n_0_[0][0] ), .I3(\saturating_counter_reg_n_0_[0][1] ), .I4(\saturating_counter_reg[0]_0 [4]), .O(p_0_in[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \saturating_counter[0][5]_i_1 (.I0(\saturating_counter_reg_n_0_[0][1] ), .I1(\saturating_counter_reg_n_0_[0][0] ), .I2(\saturating_counter_reg_n_0_[0][2] ), .I3(\saturating_counter_reg[0]_0 [3]), .I4(\saturating_counter_reg[0]_0 [4]), .I5(\saturating_counter_reg[0]_0 [5]), .O(p_0_in[5])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT2 #( .INIT(4'h9)) \saturating_counter[0][6]_i_1 (.I0(\saturating_counter[0][9]_i_4_n_0 ), .I1(\saturating_counter_reg[0]_0 [6]), .O(p_0_in[6])); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT3 #( .INIT(8'hB4)) \saturating_counter[0][7]_i_1 (.I0(\saturating_counter[0][9]_i_4_n_0 ), .I1(\saturating_counter_reg[0]_0 [6]), .I2(\saturating_counter_reg[0]_0 [7]), .O(p_0_in[7])); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT4 #( .INIT(16'hF708)) \saturating_counter[0][8]_i_1 (.I0(\saturating_counter_reg[0]_0 [7]), .I1(\saturating_counter_reg[0]_0 [6]), .I2(\saturating_counter[0][9]_i_4_n_0 ), .I3(\saturating_counter_reg[0]_0 [8]), .O(p_0_in[8])); LUT3 #( .INIT(8'h80)) \saturating_counter[0][9]_i_2 (.I0(wrapping_counter_reg[13]), .I1(wrapping_counter_reg[14]), .I2(\wrapping_counter[0]_i_3_n_0 ), .O(p_0_out)); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( .INIT(32'hDFFF2000)) \saturating_counter[0][9]_i_3 (.I0(\saturating_counter_reg[0]_0 [8]), .I1(\saturating_counter[0][9]_i_4_n_0 ), .I2(\saturating_counter_reg[0]_0 [6]), .I3(\saturating_counter_reg[0]_0 [7]), .I4(\saturating_counter_reg[0]_0 [9]), .O(p_0_in[9])); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \saturating_counter[0][9]_i_4 (.I0(\saturating_counter_reg_n_0_[0][1] ), .I1(\saturating_counter_reg_n_0_[0][0] ), .I2(\saturating_counter_reg_n_0_[0][2] ), .I3(\saturating_counter_reg[0]_0 [3]), .I4(\saturating_counter_reg[0]_0 [4]), .I5(\saturating_counter_reg[0]_0 [5]), .O(\saturating_counter[0][9]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \saturating_counter_reg[0][0] (.C(cpu_clk), .CE(p_0_out), .D(p_0_in[0]), .Q(\saturating_counter_reg_n_0_[0][0] ), .R(SR)); FDRE #( .INIT(1'b0)) \saturating_counter_reg[0][1] (.C(cpu_clk), .CE(p_0_out), .D(p_0_in[1]), .Q(\saturating_counter_reg_n_0_[0][1] ), .R(SR)); FDRE #( .INIT(1'b0)) \saturating_counter_reg[0][2] (.C(cpu_clk), .CE(p_0_out), .D(p_0_in[2]), .Q(\saturating_counter_reg_n_0_[0][2] ), .R(SR)); FDRE #( .INIT(1'b0)) \saturating_counter_reg[0][3] (.C(cpu_clk), .CE(p_0_out), .D(p_0_in[3]), .Q(\saturating_counter_reg[0]_0 [3]), .R(SR)); FDRE #( .INIT(1'b0)) \saturating_counter_reg[0][4] (.C(cpu_clk), .CE(p_0_out), .D(p_0_in[4]), .Q(\saturating_counter_reg[0]_0 [4]), .R(SR)); FDRE #( .INIT(1'b0)) \saturating_counter_reg[0][5] (.C(cpu_clk), .CE(p_0_out), .D(p_0_in[5]), .Q(\saturating_counter_reg[0]_0 [5]), .R(SR)); FDRE #( .INIT(1'b0)) \saturating_counter_reg[0][6] (.C(cpu_clk), .CE(p_0_out), .D(p_0_in[6]), .Q(\saturating_counter_reg[0]_0 [6]), .R(SR)); FDRE #( .INIT(1'b0)) \saturating_counter_reg[0][7] (.C(cpu_clk), .CE(p_0_out), .D(p_0_in[7]), .Q(\saturating_counter_reg[0]_0 [7]), .R(SR)); FDRE #( .INIT(1'b0)) \saturating_counter_reg[0][8] (.C(cpu_clk), .CE(p_0_out), .D(p_0_in[8]), .Q(\saturating_counter_reg[0]_0 [8]), .R(SR)); FDRE #( .INIT(1'b0)) \saturating_counter_reg[0][9] (.C(cpu_clk), .CE(p_0_out), .D(p_0_in[9]), .Q(\saturating_counter_reg[0]_0 [9]), .R(SR)); LUT3 #( .INIT(8'h80)) \wrapping_counter[0]_i_1 (.I0(wrapping_counter_reg[14]), .I1(wrapping_counter_reg[13]), .I2(\wrapping_counter[0]_i_3_n_0 ), .O(en)); LUT5 #( .INIT(32'hFFFFFFFE)) \wrapping_counter[0]_i_3 (.I0(\wrapping_counter[0]_i_5_n_0 ), .I1(wrapping_counter_reg[10]), .I2(wrapping_counter_reg[11]), .I3(wrapping_counter_reg[12]), .I4(wrapping_counter_reg[9]), .O(\wrapping_counter[0]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \wrapping_counter[0]_i_4 (.I0(\wrapping_counter_reg_n_0_[0] ), .O(\wrapping_counter[0]_i_4_n_0 )); LUT6 #( .INIT(64'h8888888080808080)) \wrapping_counter[0]_i_5 (.I0(wrapping_counter_reg[8]), .I1(wrapping_counter_reg[7]), .I2(wrapping_counter_reg[6]), .I3(wrapping_counter_reg[3]), .I4(wrapping_counter_reg[4]), .I5(wrapping_counter_reg[5]), .O(\wrapping_counter[0]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[0]_i_2_n_7 ), .Q(\wrapping_counter_reg_n_0_[0] ), .R(en)); (* ADDER_THRESHOLD = "11" *) CARRY4 \wrapping_counter_reg[0]_i_2 (.CI(\<const0> ), .CO({\wrapping_counter_reg[0]_i_2_n_0 ,\wrapping_counter_reg[0]_i_2_n_1 ,\wrapping_counter_reg[0]_i_2_n_2 ,\wrapping_counter_reg[0]_i_2_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const1> }), .O({\wrapping_counter_reg[0]_i_2_n_4 ,\wrapping_counter_reg[0]_i_2_n_5 ,\wrapping_counter_reg[0]_i_2_n_6 ,\wrapping_counter_reg[0]_i_2_n_7 }), .S({wrapping_counter_reg[3],\wrapping_counter_reg_n_0_[2] ,\wrapping_counter_reg_n_0_[1] ,\wrapping_counter[0]_i_4_n_0 })); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[10] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[8]_i_1_n_5 ), .Q(wrapping_counter_reg[10]), .R(en)); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[11] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[8]_i_1_n_4 ), .Q(wrapping_counter_reg[11]), .R(en)); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[12] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[12]_i_1_n_7 ), .Q(wrapping_counter_reg[12]), .R(en)); (* ADDER_THRESHOLD = "11" *) CARRY4 \wrapping_counter_reg[12]_i_1 (.CI(\wrapping_counter_reg[8]_i_1_n_0 ), .CO({\wrapping_counter_reg[12]_i_1_n_2 ,\wrapping_counter_reg[12]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\wrapping_counter_reg[12]_i_1_n_5 ,\wrapping_counter_reg[12]_i_1_n_6 ,\wrapping_counter_reg[12]_i_1_n_7 }), .S({\<const0> ,wrapping_counter_reg[14:12]})); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[13] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[12]_i_1_n_6 ), .Q(wrapping_counter_reg[13]), .R(en)); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[14] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[12]_i_1_n_5 ), .Q(wrapping_counter_reg[14]), .R(en)); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[0]_i_2_n_6 ), .Q(\wrapping_counter_reg_n_0_[1] ), .R(en)); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[0]_i_2_n_5 ), .Q(\wrapping_counter_reg_n_0_[2] ), .R(en)); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[0]_i_2_n_4 ), .Q(wrapping_counter_reg[3]), .R(en)); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[4]_i_1_n_7 ), .Q(wrapping_counter_reg[4]), .R(en)); (* ADDER_THRESHOLD = "11" *) CARRY4 \wrapping_counter_reg[4]_i_1 (.CI(\wrapping_counter_reg[0]_i_2_n_0 ), .CO({\wrapping_counter_reg[4]_i_1_n_0 ,\wrapping_counter_reg[4]_i_1_n_1 ,\wrapping_counter_reg[4]_i_1_n_2 ,\wrapping_counter_reg[4]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\wrapping_counter_reg[4]_i_1_n_4 ,\wrapping_counter_reg[4]_i_1_n_5 ,\wrapping_counter_reg[4]_i_1_n_6 ,\wrapping_counter_reg[4]_i_1_n_7 }), .S(wrapping_counter_reg[7:4])); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[4]_i_1_n_6 ), .Q(wrapping_counter_reg[5]), .R(en)); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[4]_i_1_n_5 ), .Q(wrapping_counter_reg[6]), .R(en)); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[4]_i_1_n_4 ), .Q(wrapping_counter_reg[7]), .R(en)); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[8]_i_1_n_7 ), .Q(wrapping_counter_reg[8]), .R(en)); (* ADDER_THRESHOLD = "11" *) CARRY4 \wrapping_counter_reg[8]_i_1 (.CI(\wrapping_counter_reg[4]_i_1_n_0 ), .CO({\wrapping_counter_reg[8]_i_1_n_0 ,\wrapping_counter_reg[8]_i_1_n_1 ,\wrapping_counter_reg[8]_i_1_n_2 ,\wrapping_counter_reg[8]_i_1_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O({\wrapping_counter_reg[8]_i_1_n_4 ,\wrapping_counter_reg[8]_i_1_n_5 ,\wrapping_counter_reg[8]_i_1_n_6 ,\wrapping_counter_reg[8]_i_1_n_7 }), .S(wrapping_counter_reg[11:8])); FDRE #( .INIT(1'b0)) \wrapping_counter_reg[9] (.C(cpu_clk), .CE(\<const1> ), .D(\wrapping_counter_reg[8]_i_1_n_6 ), .Q(wrapping_counter_reg[9]), .R(en)); endmodule module dmem (\f_ex_inst_reg[2] , \f_ex_inst_reg[2]_0 , \f_ex_inst_reg[2]_1 , \ex_wb_inst_reg[12] , wb_mux, \ex_wb_inst_reg[12]_0 , \ex_wb_inst_reg[12]_1 , \ex_wb_inst_reg[12]_2 , DI, \f_ex_imm_reg[31] , \f_ex_imm_reg[31]_0 , \f_ex_pc_reg[31] , D, \f_ex_pc_reg[31]_0 , \f_ex_inst_reg[14] , \f_ex_inst_reg[2]_2 , \f_ex_pc_reg[31]_1 , \f_ex_pc_reg[31]_2 , S, mem_reg_3_3_0, dout, mem_reg_3_3_1, \wb_alu_reg[31] , ALUSel, wb_BrLt_reg_i_3, wb_BrLt_reg_i_3_0, wb_BrLt_reg_i_3_1, mem_reg_3_3_2, mem_reg_3_3_3, \wb_alu_reg[31]_0 , \wb_alu_reg[31]_1 , \wb_alu_reg[31]_2 , \bit_counter[3]_i_35 , Q, \pprev_data_reg[31] , \pprev_data_reg[31]_0 , \wb_alu[0]_i_33 , ASel, \wb_alu[0]_i_33_0 , BSel, \pprev_data_reg[31]_1 , \pprev_data_reg[31]_2 , \pprev_data_reg[31]_3 , \pprev_data[31]_i_2_0 , \pprev_data[31]_i_2_1 , \pprev_data[31]_i_2_2 , \pprev_data[31]_i_2_3 , \pprev_data[31]_i_2_4 , mem_reg_r1_0_31_6_11_i_14, mem_reg_r1_0_31_6_11_i_11, mem_reg_r1_0_31_6_11_i_20, mem_reg_r1_0_31_6_11_i_17, mem_reg_r1_0_31_12_17_i_10, mem_reg_r1_0_31_12_17_i_7, mem_reg_r1_0_31_12_17_i_16, mem_reg_r1_0_31_12_17_i_13, mem_reg_r1_0_31_24_29_i_9, mem_reg_r1_0_31_24_29_i_7, mem_reg_r1_0_31_24_29_i_13, mem_reg_r1_0_31_24_29_i_11, mem_reg_r1_0_31_24_29_i_17, mem_reg_r1_0_31_24_29_i_15, \pprev_data[30]_i_2 , \pprev_data[31]_i_2_5 , cpu_clk, ADDRARDADDR, p_1_in, dmem_we, ex_alu, mem_reg_3_3_4, addr); output \f_ex_inst_reg[2] ; output \f_ex_inst_reg[2]_0 ; output \f_ex_inst_reg[2]_1 ; output \ex_wb_inst_reg[12] ; output [0:0]wb_mux; output [0:0]\ex_wb_inst_reg[12]_0 ; output \ex_wb_inst_reg[12]_1 ; output [0:0]\ex_wb_inst_reg[12]_2 ; output [0:0]DI; output [0:0]\f_ex_imm_reg[31] ; output [0:0]\f_ex_imm_reg[31]_0 ; output [0:0]\f_ex_pc_reg[31] ; output [0:0]D; output \f_ex_pc_reg[31]_0 ; output \f_ex_inst_reg[14] ; output \f_ex_inst_reg[2]_2 ; output \f_ex_pc_reg[31]_1 ; output \f_ex_pc_reg[31]_2 ; output [0:0]S; output [14:0]mem_reg_3_3_0; output [31:0]dout; input mem_reg_3_3_1; input [3:0]\wb_alu_reg[31] ; input [3:0]ALUSel; input wb_BrLt_reg_i_3; input wb_BrLt_reg_i_3_0; input wb_BrLt_reg_i_3_1; input mem_reg_3_3_2; input mem_reg_3_3_3; input \wb_alu_reg[31]_0 ; input \wb_alu_reg[31]_1 ; input \wb_alu_reg[31]_2 ; input [2:0]\bit_counter[3]_i_35 ; input [2:0]Q; input [1:0]\pprev_data_reg[31] ; input \pprev_data_reg[31]_0 ; input [0:0]\wb_alu[0]_i_33 ; input ASel; input [0:0]\wb_alu[0]_i_33_0 ; input BSel; input \pprev_data_reg[31]_1 ; input \pprev_data_reg[31]_2 ; input \pprev_data_reg[31]_3 ; input \pprev_data[31]_i_2_0 ; input \pprev_data[31]_i_2_1 ; input \pprev_data[31]_i_2_2 ; input [16:0]\pprev_data[31]_i_2_3 ; input \pprev_data[31]_i_2_4 ; input mem_reg_r1_0_31_6_11_i_14; input mem_reg_r1_0_31_6_11_i_11; input mem_reg_r1_0_31_6_11_i_20; input mem_reg_r1_0_31_6_11_i_17; input mem_reg_r1_0_31_12_17_i_10; input mem_reg_r1_0_31_12_17_i_7; input mem_reg_r1_0_31_12_17_i_16; input mem_reg_r1_0_31_12_17_i_13; input mem_reg_r1_0_31_24_29_i_9; input mem_reg_r1_0_31_24_29_i_7; input mem_reg_r1_0_31_24_29_i_13; input mem_reg_r1_0_31_24_29_i_11; input mem_reg_r1_0_31_24_29_i_17; input mem_reg_r1_0_31_24_29_i_15; input \pprev_data[30]_i_2 ; input \pprev_data[31]_i_2_5 ; input cpu_clk; input [13:0]ADDRARDADDR; input [31:0]p_1_in; input [3:0]dmem_we; input [0:0]ex_alu; input [8:0]mem_reg_3_3_4; input [1:0]addr; wire \<const0> ; wire \<const1> ; wire [13:0]ADDRARDADDR; wire [3:0]ALUSel; wire ASel; wire BSel; wire [0:0]D; wire [0:0]DI; wire [2:0]Q; wire [0:0]S; wire [1:0]addr; wire [2:0]\bit_counter[3]_i_35 ; wire cpu_clk; wire [3:0]dmem_we; wire [31:0]dout; wire [0:0]ex_alu; wire \ex_wb_inst_reg[12] ; wire [0:0]\ex_wb_inst_reg[12]_0 ; wire \ex_wb_inst_reg[12]_1 ; wire [0:0]\ex_wb_inst_reg[12]_2 ; wire [0:0]\f_ex_imm_reg[31] ; wire [0:0]\f_ex_imm_reg[31]_0 ; wire \f_ex_inst_reg[14] ; wire \f_ex_inst_reg[2] ; wire \f_ex_inst_reg[2]_0 ; wire \f_ex_inst_reg[2]_1 ; wire \f_ex_inst_reg[2]_2 ; wire [0:0]\f_ex_pc_reg[31] ; wire \f_ex_pc_reg[31]_0 ; wire \f_ex_pc_reg[31]_1 ; wire \f_ex_pc_reg[31]_2 ; wire [14:0]mem_reg_3_3_0; wire mem_reg_3_3_1; wire mem_reg_3_3_2; wire mem_reg_3_3_3; wire [8:0]mem_reg_3_3_4; wire mem_reg_r1_0_31_12_17_i_10; wire mem_reg_r1_0_31_12_17_i_13; wire mem_reg_r1_0_31_12_17_i_16; wire mem_reg_r1_0_31_12_17_i_7; wire mem_reg_r1_0_31_24_29_i_11; wire mem_reg_r1_0_31_24_29_i_13; wire mem_reg_r1_0_31_24_29_i_15; wire mem_reg_r1_0_31_24_29_i_17; wire mem_reg_r1_0_31_24_29_i_7; wire mem_reg_r1_0_31_24_29_i_9; wire mem_reg_r1_0_31_6_11_i_11; wire mem_reg_r1_0_31_6_11_i_14; wire mem_reg_r1_0_31_6_11_i_17; wire mem_reg_r1_0_31_6_11_i_20; wire [31:15]mem_wb_mux; wire [31:0]p_1_in; wire \pprev_data[30]_i_2 ; wire \pprev_data[31]_i_2_0 ; wire \pprev_data[31]_i_2_1 ; wire \pprev_data[31]_i_2_2 ; wire [16:0]\pprev_data[31]_i_2_3 ; wire \pprev_data[31]_i_2_4 ; wire \pprev_data[31]_i_2_5 ; wire \pprev_data[31]_i_2_n_0 ; wire [1:0]\pprev_data_reg[31] ; wire \pprev_data_reg[31]_0 ; wire \pprev_data_reg[31]_1 ; wire \pprev_data_reg[31]_2 ; wire \pprev_data_reg[31]_3 ; wire wb_BrLt_reg_i_3; wire wb_BrLt_reg_i_3_0; wire wb_BrLt_reg_i_3_1; wire [0:0]\wb_alu[0]_i_33 ; wire [0:0]\wb_alu[0]_i_33_0 ; wire [3:0]\wb_alu_reg[31] ; wire \wb_alu_reg[31]_0 ; wire \wb_alu_reg[31]_1 ; wire \wb_alu_reg[31]_2 ; wire [0:0]wb_mux; GND GND (.G(\<const0> )); VCC VCC (.P(\<const1> )); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT2 #( .INIT(4'h7)) \bit_counter[3]_i_48 (.I0(\f_ex_pc_reg[31] ), .I1(\bit_counter[3]_i_35 [0]), .O(\f_ex_pc_reg[31]_2 )); LUT4 #( .INIT(16'h8808)) \bit_counter[3]_i_64 (.I0(\f_ex_pc_reg[31]_1 ), .I1(ALUSel[3]), .I2(ALUSel[1]), .I3(\bit_counter[3]_i_35 [2]), .O(\f_ex_inst_reg[2]_2 )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "1" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_0_0 (.ADDRARDADDR({\<const1> ,ADDRARDADDR,\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[1:0]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[1:0]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[0],dmem_we[0],dmem_we[0],dmem_we[0]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT3 #( .INIT(8'hEC)) mem_reg_0_0_i_106 (.I0(\f_ex_pc_reg[31] ), .I1(ALUSel[1]), .I2(\bit_counter[3]_i_35 [1]), .O(\f_ex_pc_reg[31]_1 )); LUT3 #( .INIT(8'h4F)) mem_reg_0_0_i_219 (.I0(mem_reg_3_3_1), .I1(\wb_alu_reg[31] [0]), .I2(ALUSel[3]), .O(\f_ex_inst_reg[2]_1 )); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT3 #( .INIT(8'h4F)) mem_reg_0_0_i_32__0 (.I0(mem_reg_3_3_1), .I1(\wb_alu_reg[31] [1]), .I2(ALUSel[3]), .O(\f_ex_inst_reg[2]_0 )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "2" *) (* ram_slice_end = "3" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_0_1 (.ADDRARDADDR({\<const1> ,ADDRARDADDR,\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[3:2]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[3:2]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[0],dmem_we[0],dmem_we[0],dmem_we[0]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "4" *) (* ram_slice_end = "5" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_0_2 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu,ADDRARDADDR[10:0],\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[5:4]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[5:4]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[0],dmem_we[0],dmem_we[0],dmem_we[0]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "6" *) (* ram_slice_end = "7" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_0_3 (.ADDRARDADDR({\<const1> ,ADDRARDADDR,\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[7:6]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[7:6]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[0],dmem_we[0],dmem_we[0],dmem_we[0]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "8" *) (* ram_slice_end = "9" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_1_0 (.ADDRARDADDR({\<const1> ,ADDRARDADDR,\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[9:8]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[9:8]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[1],dmem_we[1],dmem_we[1],dmem_we[1]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "10" *) (* ram_slice_end = "11" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_1_1 (.ADDRARDADDR({\<const1> ,ADDRARDADDR,\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[11:10]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[11:10]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[1],dmem_we[1],dmem_we[1],dmem_we[1]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "12" *) (* ram_slice_end = "13" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_1_2 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu,ADDRARDADDR[10:0],\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[13:12]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[13:12]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[1],dmem_we[1],dmem_we[1],dmem_we[1]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "14" *) (* ram_slice_end = "15" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_1_3 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu,ADDRARDADDR[10:0],\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[15:14]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[15:14]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[1],dmem_we[1],dmem_we[1],dmem_we[1]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "16" *) (* ram_slice_end = "17" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_2_0 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:11],mem_reg_3_3_4,ADDRARDADDR[1:0],\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[17:16]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[17:16]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[2],dmem_we[2],dmem_we[2],dmem_we[2]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "18" *) (* ram_slice_end = "19" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_2_1 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:11],mem_reg_3_3_4,ADDRARDADDR[1:0],\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[19:18]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[19:18]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[2],dmem_we[2],dmem_we[2],dmem_we[2]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "20" *) (* ram_slice_end = "21" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_2_2 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu,mem_reg_3_3_4,addr,\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[21:20]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[21:20]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[2],dmem_we[2],dmem_we[2],dmem_we[2]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "22" *) (* ram_slice_end = "23" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_2_3 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:11],mem_reg_3_3_4,addr,\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[23:22]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[23:22]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[2],dmem_we[2],dmem_we[2],dmem_we[2]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "24" *) (* ram_slice_end = "25" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_3_0 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:11],mem_reg_3_3_4,addr,\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[25:24]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[25:24]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[3],dmem_we[3],dmem_we[3],dmem_we[3]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "26" *) (* ram_slice_end = "27" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_3_1 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:11],mem_reg_3_3_4,addr,\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[27:26]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[27:26]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[3],dmem_we[3],dmem_we[3],dmem_we[3]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "28" *) (* ram_slice_end = "29" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_3_2 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu,mem_reg_3_3_4,addr,\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[29:28]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[29:28]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[3],dmem_we[3],dmem_we[3],dmem_we[3]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "30" *) (* ram_slice_end = "31" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"), .READ_WIDTH_A(2), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(0)) mem_reg_3_3 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu,mem_reg_3_3_4,addr,\<const1> }), .ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const0> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(\<const0> ), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[31:30]}), .DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const1> ,\<const1> ,\<const1> ,\<const1> }), .DOADO(dout[31:30]), .ENARDEN(\<const1> ), .ENBWREN(\<const0> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({dmem_we[3],dmem_we[3],dmem_we[3],dmem_we[3]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT3 #( .INIT(8'hB8)) mem_reg_3_3_i_3 (.I0(wb_mux), .I1(mem_reg_3_3_2), .I2(mem_reg_3_3_3), .O(\ex_wb_inst_reg[12]_0 )); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_0_5_i_29 (.I0(mem_reg_r1_0_31_6_11_i_11), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[17]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [2]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[1])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_0_5_i_32 (.I0(mem_reg_r1_0_31_6_11_i_14), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[16]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [1]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[0])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_0_5_i_35 (.I0(mem_reg_r1_0_31_6_11_i_17), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[19]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [4]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[3])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_0_5_i_39 (.I0(mem_reg_r1_0_31_6_11_i_20), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[18]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [3]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[2])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_0_5_i_43 (.I0(mem_reg_r1_0_31_12_17_i_7), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[21]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [6]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[5])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_0_5_i_47 (.I0(mem_reg_r1_0_31_12_17_i_10), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[20]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [5]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[4])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_24_29_i_19 (.I0(mem_reg_r1_0_31_24_29_i_7), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[25]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [10]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[9])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_24_29_i_21 (.I0(mem_reg_r1_0_31_24_29_i_9), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[24]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [9]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[8])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_24_29_i_22 (.I0(mem_reg_r1_0_31_24_29_i_11), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[27]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [12]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[11])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_24_29_i_23 (.I0(mem_reg_r1_0_31_24_29_i_13), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[26]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [11]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[10])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_24_29_i_24 (.I0(mem_reg_r1_0_31_24_29_i_15), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[29]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [14]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[13])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_24_29_i_26 (.I0(mem_reg_r1_0_31_24_29_i_17), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[28]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [13]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[12])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_6_11_i_24 (.I0(mem_reg_r1_0_31_12_17_i_13), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[23]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [8]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[7])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_6_11_i_28 (.I0(mem_reg_r1_0_31_12_17_i_16), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[22]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [7]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[6])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) \pprev_data[30]_i_4 (.I0(\pprev_data[30]_i_2 ), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[30]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [15]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_reg_3_3_0[14])); LUT6 #( .INIT(64'hFFFFFFFF00005404)) \pprev_data[31]_i_1 (.I0(\pprev_data_reg[31]_1 ), .I1(\pprev_data[31]_i_2_n_0 ), .I2(Q[0]), .I3(\pprev_data_reg[31]_2 ), .I4(Q[2]), .I5(\pprev_data_reg[31]_3 ), .O(wb_mux)); LUT6 #( .INIT(64'h45405D5D45400808)) \pprev_data[31]_i_2 (.I0(Q[1]), .I1(mem_wb_mux[31]), .I2(\pprev_data_reg[31] [1]), .I3(mem_wb_mux[15]), .I4(\pprev_data_reg[31] [0]), .I5(\pprev_data_reg[31]_0 ), .O(\pprev_data[31]_i_2_n_0 )); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) \pprev_data[31]_i_4 (.I0(\pprev_data[31]_i_2_5 ), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[31]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [16]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_wb_mux[31])); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) \pprev_data[31]_i_5 (.I0(\pprev_data[31]_i_2_0 ), .I1(\pprev_data[31]_i_2_1 ), .I2(dout[15]), .I3(\pprev_data[31]_i_2_2 ), .I4(\pprev_data[31]_i_2_3 [0]), .I5(\pprev_data[31]_i_2_4 ), .O(mem_wb_mux[15])); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT4 #( .INIT(16'hB847)) wb_BrEq_i_17 (.I0(wb_mux), .I1(wb_BrLt_reg_i_3), .I2(wb_BrLt_reg_i_3_0), .I3(\ex_wb_inst_reg[12]_0 ), .O(\ex_wb_inst_reg[12]_1 )); LUT5 #( .INIT(32'hB800FFB8)) wb_BrLt_i_14 (.I0(wb_mux), .I1(wb_BrLt_reg_i_3), .I2(wb_BrLt_reg_i_3_0), .I3(wb_BrLt_reg_i_3_1), .I4(\ex_wb_inst_reg[12]_0 ), .O(DI)); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT4 #( .INIT(16'hB847)) wb_BrLt_i_32 (.I0(wb_mux), .I1(wb_BrLt_reg_i_3), .I2(wb_BrLt_reg_i_3_0), .I3(\ex_wb_inst_reg[12]_0 ), .O(\ex_wb_inst_reg[12] )); LUT5 #( .INIT(32'hFF474700)) wb_BrLt_i_5 (.I0(wb_mux), .I1(wb_BrLt_reg_i_3), .I2(wb_BrLt_reg_i_3_0), .I3(wb_BrLt_reg_i_3_1), .I4(\ex_wb_inst_reg[12]_0 ), .O(\ex_wb_inst_reg[12]_2 )); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT3 #( .INIT(8'h4F)) \wb_alu[28]_i_6 (.I0(mem_reg_3_3_1), .I1(\wb_alu_reg[31] [2]), .I2(ALUSel[3]), .O(\f_ex_inst_reg[2] )); LUT2 #( .INIT(4'h6)) \wb_alu[29]_i_14 (.I0(\f_ex_imm_reg[31]_0 ), .I1(\f_ex_pc_reg[31] ), .O(S)); LUT5 #( .INIT(32'hBBBB8B88)) \wb_alu[31]_i_1 (.I0(\f_ex_pc_reg[31]_0 ), .I1(ALUSel[3]), .I2(\wb_alu_reg[31]_0 ), .I3(\wb_alu_reg[31]_1 ), .I4(\f_ex_inst_reg[14] ), .O(D)); LUT2 #( .INIT(4'h9)) \wb_alu[31]_i_15 (.I0(\f_ex_imm_reg[31]_0 ), .I1(\f_ex_pc_reg[31] ), .O(\f_ex_imm_reg[31] )); LUT6 #( .INIT(64'hC000A00FC000A000)) \wb_alu[31]_i_2 (.I0(\f_ex_pc_reg[31] ), .I1(\f_ex_imm_reg[31]_0 ), .I2(ALUSel[0]), .I3(ALUSel[2]), .I4(ALUSel[1]), .I5(\wb_alu_reg[31] [3]), .O(\f_ex_pc_reg[31]_0 )); LUT6 #( .INIT(64'hCC880C8C0C8C0088)) \wb_alu[31]_i_5 (.I0(\wb_alu_reg[31]_2 ), .I1(ALUSel[2]), .I2(ALUSel[0]), .I3(ALUSel[1]), .I4(\f_ex_imm_reg[31]_0 ), .I5(\f_ex_pc_reg[31] ), .O(\f_ex_inst_reg[14] )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[31]_i_6 (.I0(\wb_alu[0]_i_33 ), .I1(ASel), .I2(wb_mux), .I3(wb_BrLt_reg_i_3), .I4(wb_BrLt_reg_i_3_0), .O(\f_ex_pc_reg[31] )); LUT3 #( .INIT(8'hB8)) \wb_alu[31]_i_7 (.I0(\wb_alu[0]_i_33_0 ), .I1(BSel), .I2(\ex_wb_inst_reg[12]_0 ), .O(\f_ex_imm_reg[31]_0 )); endmodule module edge_detector (pulse, buttons_pressed, cpu_reset, debounced_signals, cpu_clk, \out_reg[0]_0 , cpu_clk_locked); output [0:0]pulse; output buttons_pressed; output cpu_reset; input [0:0]debounced_signals; input cpu_clk; input \out_reg[0]_0 ; input cpu_clk_locked; wire \<const0> ; wire \<const1> ; wire buttons_pressed; wire cpu_clk; wire cpu_clk_locked; wire cpu_reset; wire [0:0]debounced_signals; wire \out_reg[0]_0 ; wire [0:0]pulse; GND GND (.G(\<const0> )); VCC VCC (.P(\<const1> )); LUT2 #( .INIT(4'hB)) \bit_counter[3]_i_1 (.I0(buttons_pressed), .I1(cpu_clk_locked), .O(cpu_reset)); FDRE #( .INIT(1'b0)) \out_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(\out_reg[0]_0 ), .Q(buttons_pressed), .R(\<const0> )); FDRE #( .INIT(1'b0)) \pulse_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(debounced_signals), .Q(pulse), .R(\<const0> )); endmodule module imem (\f_ex_inst_reg[2] , \f_ex_inst_reg[12] , ALUSel, \f_ex_inst_reg[2]_0 , \f_ex_inst_reg[2]_1 , \f_ex_inst_reg[2]_2 , \f_ex_inst_reg[2]_3 , \f_ex_inst_reg[2]_4 , \f_ex_inst_reg[2]_5 , \f_ex_inst_reg[2]_6 , \f_ex_inst_reg[2]_7 , \wb_alu_reg[31] , \wb_alu_reg[30] , \wb_alu_reg[29] , \wb_alu_reg[28] , \wb_alu_reg[27] , \wb_alu_reg[26] , \wb_alu_reg[25] , \wb_alu_reg[24] , \wb_alu_reg[23] , \wb_alu_reg[22] , \wb_alu_reg[21] , \wb_alu_reg[20] , \wb_alu_reg[19] , \wb_alu_reg[18] , \wb_alu_reg[17] , \wb_alu_reg[16] , \wb_alu_reg[15] , \wb_alu_reg[14] , \wb_alu_reg[13] , \wb_alu_reg[12] , \wb_alu_reg[11] , \wb_alu_reg[10] , \wb_alu_reg[9] , \wb_alu_reg[8] , \wb_alu_reg[7] , \wb_alu_reg[6] , \wb_alu_reg[5] , \wb_alu_reg[4] , \wb_alu_reg[3] , \wb_alu_reg[2] , \wb_alu_reg[1] , \wb_alu_reg[0] , MemRW, \f_ex_inst_reg[4] , ASel, BSel, \f_ex_inst_reg[3] , \wb_alu_reg[0]_0 , \ex_wb_inst_reg[5] , \f_ex_inst_reg[19] , \wb_alu_reg[1]_0 , \wb_alu_reg[2]_0 , \wb_alu_reg[3]_0 , \wb_alu_reg[4]_0 , \wb_alu_reg[5]_0 , \wb_alu_reg[6]_0 , \wb_alu_reg[7]_0 , \wb_alu_reg[8]_0 , \wb_alu_reg[9]_0 , \wb_alu_reg[10]_0 , \wb_alu_reg[11]_0 , \wb_alu_reg[12]_0 , \wb_alu_reg[13]_0 , \wb_alu_reg[14]_0 , \wb_alu_reg[15]_0 , \wb_alu_reg[16]_0 , \wb_alu_reg[17]_0 , \wb_alu_reg[18]_0 , \wb_alu_reg[19]_0 , \wb_alu_reg[20]_0 , \wb_alu_reg[21]_0 , \ex_wb_inst_reg[3] , \ex_wb_inst_reg[3]_0 , \f_ex_inst_reg[2]_8 , \f_ex_inst_reg[2]_9 , \f_ex_inst_reg[12]_0 , \f_ex_inst_reg[12]_1 , br, \ex_wb_inst_reg[3]_1 , \ex_wb_inst_reg[6] , data2, \ex_wb_inst_reg[3]_2 , \ex_wb_inst_reg[3]_3 , \ex_wb_inst_reg[3]_4 , \ex_wb_inst_reg[3]_5 , \ex_wb_inst_reg[3]_6 , \ex_wb_inst_reg[3]_7 , \ex_wb_inst_reg[3]_8 , \ex_wb_inst_reg[3]_9 , \ex_wb_inst_reg[3]_10 , \ex_wb_inst_reg[3]_11 , \ex_wb_inst_reg[3]_12 , \ex_wb_inst_reg[3]_13 , \ex_wb_inst_reg[3]_14 , \ex_wb_inst_reg[3]_15 , \ex_wb_inst_reg[3]_16 , \ex_wb_inst_reg[3]_17 , \ex_wb_inst_reg[2] , \f_ex_inst_reg[6] , \f_ex_inst_reg[2]_10 , \wb_alu_reg[23]_0 , \wb_alu_reg[30]_0 , \wb_alu_reg[16]_1 , \wb_alu_reg[13]_1 , .cycle_cnt_reg_8_sp_1(cycle_cnt_reg_8_sn_1), \wb_alu_reg[2]_1 , \wb_alu_reg[4]_1 , .insts_cnt_reg_9_sp_1(insts_cnt_reg_9_sn_1), \wb_alu_reg[0]_1 , \wb_alu_reg[0]_2 , .insts_cnt_reg_10_sp_1(insts_cnt_reg_10_sn_1), .insts_cnt_reg_11_sp_1(insts_cnt_reg_11_sn_1), .cycle_cnt_reg_12_sp_1(cycle_cnt_reg_12_sn_1), .insts_cnt_reg_13_sp_1(insts_cnt_reg_13_sn_1), .insts_cnt_reg_14_sp_1(insts_cnt_reg_14_sn_1), .insts_cnt_reg_16_sp_1(insts_cnt_reg_16_sn_1), .cycle_cnt_reg_17_sp_1(cycle_cnt_reg_17_sn_1), .insts_cnt_reg_18_sp_1(insts_cnt_reg_18_sn_1), .insts_cnt_reg_19_sp_1(insts_cnt_reg_19_sn_1), .insts_cnt_reg_20_sp_1(insts_cnt_reg_20_sn_1), \cycle_cnt_reg[21] , \insts_cnt_reg[22] , \insts_cnt_reg[23] , \insts_cnt_reg[24] , \cycle_cnt_reg[25] , \insts_cnt_reg[26] , \insts_cnt_reg[27] , \cycle_cnt_reg[28] , \cycle_cnt_reg[29] , \wb_alu_reg[4]_2 , data3, CO, O, \f_ex_pc_reg[7] , \f_ex_pc_reg[11] , \f_ex_pc_reg[15] , \f_ex_pc_reg[15]_0 , \ex_wb_pc_reg[16] , \f_ex_inst_reg[14] , doutb, \wb_alu[29]_i_2 , douta_reg_0, Q, mem_reg_3_3_i_3, mem_reg_3_3_i_3_0, mem_reg_0_0_i_25, \wb_alu_reg[31]_0 , wb_BrEq_i_33, \f_ex_rd2_reg[0] , mem_reg_0_0_i_319_0, douta_reg_0_0, we, wb_BrLt, wb_BrEq, \pprev_data_reg[21] , \pc_reg[16] , mem_reg_r1_0_31_18_23_i_24, cycle_cnt_reg, br_inst_cnt_reg, insts_cnt_reg, br_corr_cnt_reg, mem_reg_3_3_0, mem_reg_0_0_i_42__0_0, cpu_clk, ADDRARDADDR, ex_alu, mem_reg_3_3_1, p_1_in, imem_wea, addra); output \f_ex_inst_reg[2] ; output \f_ex_inst_reg[12] ; output [2:0]ALUSel; output \f_ex_inst_reg[2]_0 ; output \f_ex_inst_reg[2]_1 ; output \f_ex_inst_reg[2]_2 ; output \f_ex_inst_reg[2]_3 ; output \f_ex_inst_reg[2]_4 ; output \f_ex_inst_reg[2]_5 ; output \f_ex_inst_reg[2]_6 ; output \f_ex_inst_reg[2]_7 ; output \wb_alu_reg[31] ; output \wb_alu_reg[30] ; output \wb_alu_reg[29] ; output \wb_alu_reg[28] ; output \wb_alu_reg[27] ; output \wb_alu_reg[26] ; output \wb_alu_reg[25] ; output \wb_alu_reg[24] ; output \wb_alu_reg[23] ; output \wb_alu_reg[22] ; output \wb_alu_reg[21] ; output \wb_alu_reg[20] ; output \wb_alu_reg[19] ; output \wb_alu_reg[18] ; output \wb_alu_reg[17] ; output \wb_alu_reg[16] ; output \wb_alu_reg[15] ; output \wb_alu_reg[14] ; output \wb_alu_reg[13] ; output \wb_alu_reg[12] ; output \wb_alu_reg[11] ; output \wb_alu_reg[10] ; output \wb_alu_reg[9] ; output \wb_alu_reg[8] ; output \wb_alu_reg[7] ; output \wb_alu_reg[6] ; output \wb_alu_reg[5] ; output \wb_alu_reg[4] ; output \wb_alu_reg[3] ; output \wb_alu_reg[2] ; output \wb_alu_reg[1] ; output \wb_alu_reg[0] ; output [2:0]MemRW; output \f_ex_inst_reg[4] ; output ASel; output BSel; output \f_ex_inst_reg[3] ; output \wb_alu_reg[0]_0 ; output \ex_wb_inst_reg[5] ; output \f_ex_inst_reg[19] ; output \wb_alu_reg[1]_0 ; output \wb_alu_reg[2]_0 ; output \wb_alu_reg[3]_0 ; output \wb_alu_reg[4]_0 ; output \wb_alu_reg[5]_0 ; output \wb_alu_reg[6]_0 ; output \wb_alu_reg[7]_0 ; output \wb_alu_reg[8]_0 ; output \wb_alu_reg[9]_0 ; output \wb_alu_reg[10]_0 ; output \wb_alu_reg[11]_0 ; output \wb_alu_reg[12]_0 ; output \wb_alu_reg[13]_0 ; output \wb_alu_reg[14]_0 ; output \wb_alu_reg[15]_0 ; output \wb_alu_reg[16]_0 ; output \wb_alu_reg[17]_0 ; output \wb_alu_reg[18]_0 ; output \wb_alu_reg[19]_0 ; output \wb_alu_reg[20]_0 ; output \wb_alu_reg[21]_0 ; output \ex_wb_inst_reg[3] ; output \ex_wb_inst_reg[3]_0 ; output \f_ex_inst_reg[2]_8 ; output \f_ex_inst_reg[2]_9 ; output \f_ex_inst_reg[12]_0 ; output \f_ex_inst_reg[12]_1 ; output br; output \ex_wb_inst_reg[3]_1 ; output \ex_wb_inst_reg[6] ; output [15:0]data2; output \ex_wb_inst_reg[3]_2 ; output \ex_wb_inst_reg[3]_3 ; output \ex_wb_inst_reg[3]_4 ; output \ex_wb_inst_reg[3]_5 ; output \ex_wb_inst_reg[3]_6 ; output \ex_wb_inst_reg[3]_7 ; output \ex_wb_inst_reg[3]_8 ; output \ex_wb_inst_reg[3]_9 ; output \ex_wb_inst_reg[3]_10 ; output \ex_wb_inst_reg[3]_11 ; output \ex_wb_inst_reg[3]_12 ; output \ex_wb_inst_reg[3]_13 ; output \ex_wb_inst_reg[3]_14 ; output \ex_wb_inst_reg[3]_15 ; output \ex_wb_inst_reg[3]_16 ; output \ex_wb_inst_reg[3]_17 ; output \ex_wb_inst_reg[2] ; output \f_ex_inst_reg[6] ; output \f_ex_inst_reg[2]_10 ; output \wb_alu_reg[23]_0 ; output \wb_alu_reg[30]_0 ; output \wb_alu_reg[16]_1 ; output \wb_alu_reg[13]_1 ; output \wb_alu_reg[2]_1 ; output \wb_alu_reg[4]_1 ; output \wb_alu_reg[0]_1 ; output \wb_alu_reg[0]_2 ; output \cycle_cnt_reg[21] ; output \insts_cnt_reg[22] ; output \insts_cnt_reg[23] ; output \insts_cnt_reg[24] ; output \cycle_cnt_reg[25] ; output \insts_cnt_reg[26] ; output \insts_cnt_reg[27] ; output \cycle_cnt_reg[28] ; output \cycle_cnt_reg[29] ; output \wb_alu_reg[4]_2 ; output [15:0]data3; output [0:0]CO; output [3:0]O; output [3:0]\f_ex_pc_reg[7] ; output [3:0]\f_ex_pc_reg[11] ; output [0:0]\f_ex_pc_reg[15] ; output [3:0]\f_ex_pc_reg[15]_0 ; output [0:0]\ex_wb_pc_reg[16] ; output \f_ex_inst_reg[14] ; output [31:0]doutb; input [8:0]\wb_alu[29]_i_2 ; input [0:0]douta_reg_0; input [31:0]Q; input [31:0]mem_reg_3_3_i_3; input [31:0]mem_reg_3_3_i_3_0; input [15:0]mem_reg_0_0_i_25; input [20:0]\wb_alu_reg[31]_0 ; input [21:0]wb_BrEq_i_33; input [11:0]\f_ex_rd2_reg[0] ; input [8:0]mem_reg_0_0_i_319_0; input [1:0]douta_reg_0_0; input we; input wb_BrLt; input wb_BrEq; input [4:0]\pprev_data_reg[21] ; input [15:0]\pc_reg[16] ; input mem_reg_r1_0_31_18_23_i_24; input [20:0]cycle_cnt_reg; input [20:0]br_inst_cnt_reg; input [20:0]insts_cnt_reg; input [20:0]br_corr_cnt_reg; input [16:0]mem_reg_3_3_0; input [15:0]mem_reg_0_0_i_42__0_0; input cpu_clk; input [13:0]ADDRARDADDR; input [9:0]ex_alu; input [13:0]mem_reg_3_3_1; input [31:0]p_1_in; input [3:0]imem_wea; input [1:0]addra; output cycle_cnt_reg_8_sn_1; output insts_cnt_reg_9_sn_1; output insts_cnt_reg_10_sn_1; output insts_cnt_reg_11_sn_1; output cycle_cnt_reg_12_sn_1; output insts_cnt_reg_13_sn_1; output insts_cnt_reg_14_sn_1; output insts_cnt_reg_16_sn_1; output cycle_cnt_reg_17_sn_1; output insts_cnt_reg_18_sn_1; output insts_cnt_reg_19_sn_1; output insts_cnt_reg_20_sn_1; wire \<const0> ; wire \<const1> ; wire [13:0]ADDRARDADDR; wire [2:0]ALUSel; wire ASel; wire BSel; wire [0:0]CO; wire [2:0]MemRW; wire [3:0]O; wire [31:0]Q; wire [1:0]addra; wire br; wire [20:0]br_corr_cnt_reg; wire [20:0]br_inst_cnt_reg; wire cpu_clk; wire [20:0]cycle_cnt_reg; wire \cycle_cnt_reg[21] ; wire \cycle_cnt_reg[25] ; wire \cycle_cnt_reg[28] ; wire \cycle_cnt_reg[29] ; wire cycle_cnt_reg_12_sn_1; wire cycle_cnt_reg_17_sn_1; wire cycle_cnt_reg_8_sn_1; wire [15:0]data2; wire [15:0]data3; wire [0:0]douta_reg_0; wire [1:0]douta_reg_0_0; wire [31:0]doutb; wire [9:0]ex_alu; wire \ex_wb_inst_reg[2] ; wire \ex_wb_inst_reg[3] ; wire \ex_wb_inst_reg[3]_0 ; wire \ex_wb_inst_reg[3]_1 ; wire \ex_wb_inst_reg[3]_10 ; wire \ex_wb_inst_reg[3]_11 ; wire \ex_wb_inst_reg[3]_12 ; wire \ex_wb_inst_reg[3]_13 ; wire \ex_wb_inst_reg[3]_14 ; wire \ex_wb_inst_reg[3]_15 ; wire \ex_wb_inst_reg[3]_16 ; wire \ex_wb_inst_reg[3]_17 ; wire \ex_wb_inst_reg[3]_2 ; wire \ex_wb_inst_reg[3]_3 ; wire \ex_wb_inst_reg[3]_4 ; wire \ex_wb_inst_reg[3]_5 ; wire \ex_wb_inst_reg[3]_6 ; wire \ex_wb_inst_reg[3]_7 ; wire \ex_wb_inst_reg[3]_8 ; wire \ex_wb_inst_reg[3]_9 ; wire \ex_wb_inst_reg[5] ; wire \ex_wb_inst_reg[6] ; wire [0:0]\ex_wb_pc_reg[16] ; wire \f_ex_inst_reg[12] ; wire \f_ex_inst_reg[12]_0 ; wire \f_ex_inst_reg[12]_1 ; wire \f_ex_inst_reg[14] ; wire \f_ex_inst_reg[19] ; wire \f_ex_inst_reg[2] ; wire \f_ex_inst_reg[2]_0 ; wire \f_ex_inst_reg[2]_1 ; wire \f_ex_inst_reg[2]_10 ; wire \f_ex_inst_reg[2]_2 ; wire \f_ex_inst_reg[2]_3 ; wire \f_ex_inst_reg[2]_4 ; wire \f_ex_inst_reg[2]_5 ; wire \f_ex_inst_reg[2]_6 ; wire \f_ex_inst_reg[2]_7 ; wire \f_ex_inst_reg[2]_8 ; wire \f_ex_inst_reg[2]_9 ; wire \f_ex_inst_reg[3] ; wire \f_ex_inst_reg[4] ; wire \f_ex_inst_reg[6] ; wire [3:0]\f_ex_pc_reg[11] ; wire [0:0]\f_ex_pc_reg[15] ; wire [3:0]\f_ex_pc_reg[15]_0 ; wire [3:0]\f_ex_pc_reg[7] ; wire [11:0]\f_ex_rd2_reg[0] ; wire has_byte_i_10_n_0; wire has_byte_i_11_n_0; wire has_byte_i_9_n_0; wire [3:0]imem_wea; wire [20:0]insts_cnt_reg; wire \insts_cnt_reg[22] ; wire \insts_cnt_reg[23] ; wire \insts_cnt_reg[24] ; wire \insts_cnt_reg[26] ; wire \insts_cnt_reg[27] ; wire insts_cnt_reg_10_sn_1; wire insts_cnt_reg_11_sn_1; wire insts_cnt_reg_13_sn_1; wire insts_cnt_reg_14_sn_1; wire insts_cnt_reg_16_sn_1; wire insts_cnt_reg_18_sn_1; wire insts_cnt_reg_19_sn_1; wire insts_cnt_reg_20_sn_1; wire insts_cnt_reg_9_sn_1; wire mem_reg_0_0_i_154_n_0; wire mem_reg_0_0_i_20_n_1; wire mem_reg_0_0_i_20_n_2; wire mem_reg_0_0_i_20_n_3; wire [15:0]mem_reg_0_0_i_25; wire mem_reg_0_0_i_26_n_0; wire mem_reg_0_0_i_26_n_1; wire mem_reg_0_0_i_26_n_2; wire mem_reg_0_0_i_26_n_3; wire mem_reg_0_0_i_317_n_0; wire mem_reg_0_0_i_318_n_0; wire [8:0]mem_reg_0_0_i_319_0; wire mem_reg_0_0_i_319_n_0; wire mem_reg_0_0_i_31_n_0; wire mem_reg_0_0_i_31_n_1; wire mem_reg_0_0_i_31_n_2; wire mem_reg_0_0_i_31_n_3; wire mem_reg_0_0_i_320_n_0; wire mem_reg_0_0_i_322_n_0; wire mem_reg_0_0_i_326_n_0; wire mem_reg_0_0_i_327_n_0; wire mem_reg_0_0_i_328_n_0; wire mem_reg_0_0_i_329_n_0; wire mem_reg_0_0_i_330_n_0; wire mem_reg_0_0_i_332_n_0; wire mem_reg_0_0_i_333_n_0; wire mem_reg_0_0_i_334_n_0; wire mem_reg_0_0_i_335_n_0; wire mem_reg_0_0_i_336_n_0; wire mem_reg_0_0_i_337_n_0; wire mem_reg_0_0_i_36__0_n_0; wire mem_reg_0_0_i_36__0_n_1; wire mem_reg_0_0_i_36__0_n_2; wire mem_reg_0_0_i_36__0_n_3; wire mem_reg_0_0_i_40__0_n_1; wire mem_reg_0_0_i_40__0_n_2; wire mem_reg_0_0_i_40__0_n_3; wire [15:0]mem_reg_0_0_i_42__0_0; wire mem_reg_0_0_i_42__0_n_1; wire mem_reg_0_0_i_42__0_n_2; wire mem_reg_0_0_i_42__0_n_3; wire mem_reg_0_0_i_43_n_0; wire mem_reg_0_0_i_43_n_1; wire mem_reg_0_0_i_43_n_2; wire mem_reg_0_0_i_43_n_3; wire mem_reg_0_0_i_44_n_0; wire mem_reg_0_0_i_44_n_1; wire mem_reg_0_0_i_44_n_2; wire mem_reg_0_0_i_44_n_3; wire mem_reg_0_0_i_45__0_n_0; wire mem_reg_0_0_i_45__0_n_1; wire mem_reg_0_0_i_45__0_n_2; wire mem_reg_0_0_i_45__0_n_3; wire mem_reg_0_0_i_46__0_n_0; wire mem_reg_0_0_i_46__0_n_1; wire mem_reg_0_0_i_46__0_n_2; wire mem_reg_0_0_i_46__0_n_3; wire mem_reg_0_0_i_47_n_0; wire mem_reg_0_0_i_48__0_n_0; wire mem_reg_0_0_i_48__0_n_1; wire mem_reg_0_0_i_48__0_n_2; wire mem_reg_0_0_i_48__0_n_3; wire mem_reg_0_0_i_49__0_n_0; wire mem_reg_0_0_i_49__0_n_1; wire mem_reg_0_0_i_49__0_n_2; wire mem_reg_0_0_i_49__0_n_3; wire mem_reg_0_0_i_50__0_n_0; wire mem_reg_0_0_i_51__0_n_0; wire mem_reg_0_0_i_52_n_0; wire mem_reg_0_0_i_53__0_n_0; wire mem_reg_0_0_i_54__0_n_0; wire mem_reg_0_0_i_55_n_0; wire mem_reg_0_0_i_56__0_n_0; wire mem_reg_0_0_i_57__0_n_0; wire mem_reg_0_0_i_58__0_n_0; wire mem_reg_0_0_i_59__0_n_0; wire mem_reg_0_0_i_60__0_n_0; wire mem_reg_0_0_i_61__0_n_0; wire mem_reg_0_0_i_62_n_0; wire mem_reg_0_0_i_63__0_n_0; wire mem_reg_0_0_i_64__0_n_0; wire mem_reg_0_0_i_65__0_n_0; wire mem_reg_0_0_i_66_n_0; wire [16:0]mem_reg_3_3_0; wire [13:0]mem_reg_3_3_1; wire [31:0]mem_reg_3_3_i_3; wire [31:0]mem_reg_3_3_i_3_0; wire mem_reg_r1_0_31_0_5_i_100_n_0; wire mem_reg_r1_0_31_0_5_i_103_n_0; wire mem_reg_r1_0_31_0_5_i_104_n_0; wire mem_reg_r1_0_31_0_5_i_105_n_0; wire mem_reg_r1_0_31_0_5_i_106_n_0; wire mem_reg_r1_0_31_0_5_i_107_n_0; wire mem_reg_r1_0_31_0_5_i_108_n_0; wire mem_reg_r1_0_31_0_5_i_109_n_0; wire mem_reg_r1_0_31_0_5_i_110_n_0; wire mem_reg_r1_0_31_0_5_i_111_n_0; wire mem_reg_r1_0_31_0_5_i_112_n_0; wire mem_reg_r1_0_31_0_5_i_113_n_0; wire mem_reg_r1_0_31_0_5_i_114_n_0; wire mem_reg_r1_0_31_0_5_i_92_n_0; wire mem_reg_r1_0_31_0_5_i_93_n_0; wire mem_reg_r1_0_31_0_5_i_94_n_0; wire mem_reg_r1_0_31_0_5_i_98_n_0; wire mem_reg_r1_0_31_0_5_i_99_n_0; wire mem_reg_r1_0_31_18_23_i_24; wire mem_reg_r1_0_31_6_11_i_57_n_0; wire mem_reg_r1_0_31_6_11_i_59_n_0; wire mem_reg_r1_0_31_6_11_i_60_n_0; wire [31:0]p_1_in; wire [15:0]\pc_reg[16] ; wire [4:0]\pprev_data_reg[21] ; wire wb_BrEq; wire [21:0]wb_BrEq_i_33; wire wb_BrLt; wire [8:0]\wb_alu[29]_i_2 ; wire \wb_alu_reg[0] ; wire \wb_alu_reg[0]_0 ; wire \wb_alu_reg[0]_1 ; wire \wb_alu_reg[0]_2 ; wire \wb_alu_reg[10] ; wire \wb_alu_reg[10]_0 ; wire \wb_alu_reg[11] ; wire \wb_alu_reg[11]_0 ; wire \wb_alu_reg[12] ; wire \wb_alu_reg[12]_0 ; wire \wb_alu_reg[13] ; wire \wb_alu_reg[13]_0 ; wire \wb_alu_reg[13]_1 ; wire \wb_alu_reg[14] ; wire \wb_alu_reg[14]_0 ; wire \wb_alu_reg[15] ; wire \wb_alu_reg[15]_0 ; wire \wb_alu_reg[16] ; wire \wb_alu_reg[16]_0 ; wire \wb_alu_reg[16]_1 ; wire \wb_alu_reg[17] ; wire \wb_alu_reg[17]_0 ; wire \wb_alu_reg[18] ; wire \wb_alu_reg[18]_0 ; wire \wb_alu_reg[19] ; wire \wb_alu_reg[19]_0 ; wire \wb_alu_reg[1] ; wire \wb_alu_reg[1]_0 ; wire \wb_alu_reg[20] ; wire \wb_alu_reg[20]_0 ; wire \wb_alu_reg[21] ; wire \wb_alu_reg[21]_0 ; wire \wb_alu_reg[22] ; wire \wb_alu_reg[23] ; wire \wb_alu_reg[23]_0 ; wire \wb_alu_reg[24] ; wire \wb_alu_reg[25] ; wire \wb_alu_reg[26] ; wire \wb_alu_reg[27] ; wire \wb_alu_reg[28] ; wire \wb_alu_reg[29] ; wire \wb_alu_reg[2] ; wire \wb_alu_reg[2]_0 ; wire \wb_alu_reg[2]_1 ; wire \wb_alu_reg[30] ; wire \wb_alu_reg[30]_0 ; wire \wb_alu_reg[31] ; wire [20:0]\wb_alu_reg[31]_0 ; wire \wb_alu_reg[3] ; wire \wb_alu_reg[3]_0 ; wire \wb_alu_reg[4] ; wire \wb_alu_reg[4]_0 ; wire \wb_alu_reg[4]_1 ; wire \wb_alu_reg[4]_2 ; wire \wb_alu_reg[5] ; wire \wb_alu_reg[5]_0 ; wire \wb_alu_reg[6] ; wire \wb_alu_reg[6]_0 ; wire \wb_alu_reg[7] ; wire \wb_alu_reg[7]_0 ; wire \wb_alu_reg[8] ; wire \wb_alu_reg[8]_0 ; wire \wb_alu_reg[9] ; wire \wb_alu_reg[9]_0 ; wire we; GND GND (.G(\<const0> )); VCC VCC (.P(\<const1> )); LUT6 #( .INIT(64'h0400044440444000)) data_reg_0_7_0_0_i_4 (.I0(we), .I1(\f_ex_rd2_reg[0] [4]), .I2(wb_BrLt), .I3(\f_ex_rd2_reg[0] [11]), .I4(wb_BrEq), .I5(\f_ex_rd2_reg[0] [10]), .O(br)); LUT4 #( .INIT(16'hFFFE)) has_byte_i_10 (.I0(Q[14]), .I1(Q[15]), .I2(Q[10]), .I3(Q[21]), .O(has_byte_i_10_n_0)); LUT4 #( .INIT(16'hFFFD)) has_byte_i_11 (.I0(Q[31]), .I1(Q[26]), .I2(Q[6]), .I3(Q[9]), .O(has_byte_i_11_n_0)); LUT6 #( .INIT(64'h0000000000000001)) has_byte_i_5 (.I0(Q[30]), .I1(Q[20]), .I2(Q[27]), .I3(Q[18]), .I4(has_byte_i_9_n_0), .I5(has_byte_i_10_n_0), .O(\wb_alu_reg[30]_0 )); LUT4 #( .INIT(16'hFFFE)) has_byte_i_7 (.I0(Q[16]), .I1(Q[25]), .I2(Q[17]), .I3(Q[24]), .O(\wb_alu_reg[16]_1 )); LUT5 #( .INIT(32'hFFFFFFFE)) has_byte_i_8 (.I0(Q[13]), .I1(Q[12]), .I2(Q[8]), .I3(Q[7]), .I4(has_byte_i_11_n_0), .O(\wb_alu_reg[13]_1 )); LUT4 #( .INIT(16'hFFFE)) has_byte_i_9 (.I0(Q[29]), .I1(Q[28]), .I2(Q[11]), .I3(Q[19]), .O(has_byte_i_9_n_0)); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "1" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_0_0 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu,ADDRARDADDR[1:0],\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[1:0]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[1:0]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[0],imem_wea[0],imem_wea[0],imem_wea[0]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT3 #( .INIT(8'hEF)) mem_reg_0_0_i_154 (.I0(\wb_alu_reg[31]_0 [6]), .I1(\wb_alu_reg[31]_0 [3]), .I2(\wb_alu_reg[31]_0 [4]), .O(mem_reg_0_0_i_154_n_0)); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_20 (.CI(mem_reg_0_0_i_26_n_0), .CO({CO,mem_reg_0_0_i_20_n_1,mem_reg_0_0_i_20_n_2,mem_reg_0_0_i_20_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(data3[15:12]), .S(\pc_reg[16] [15:12])); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT3 #( .INIT(8'h4F)) mem_reg_0_0_i_200 (.I0(\f_ex_inst_reg[12] ), .I1(\wb_alu[29]_i_2 [0]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2]_7 )); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT3 #( .INIT(8'h4F)) mem_reg_0_0_i_21 (.I0(\f_ex_inst_reg[12] ), .I1(\wb_alu[29]_i_2 [7]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2]_0 )); LUT6 #( .INIT(64'h0000000000000001)) mem_reg_0_0_i_225 (.I0(\f_ex_rd2_reg[0] [1]), .I1(\f_ex_rd2_reg[0] [2]), .I2(\f_ex_rd2_reg[0] [0]), .I3(\f_ex_rd2_reg[0] [4]), .I4(\f_ex_rd2_reg[0] [3]), .I5(mem_reg_0_0_i_317_n_0), .O(\ex_wb_inst_reg[3]_0 )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_0_0_i_226 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[1]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[1]), .I5(mem_reg_3_3_i_3_0[1]), .O(\wb_alu_reg[1] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_0_0_i_228 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[0]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[0]), .I5(mem_reg_3_3_i_3_0[0]), .O(\wb_alu_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT3 #( .INIT(8'h04)) mem_reg_0_0_i_229 (.I0(\wb_alu_reg[31]_0 [4]), .I1(\wb_alu_reg[31]_0 [5]), .I2(\wb_alu_reg[31]_0 [2]), .O(\f_ex_inst_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT5 #( .INIT(32'hFFFFFDFF)) mem_reg_0_0_i_238 (.I0(\wb_alu_reg[31]_0 [5]), .I1(\wb_alu_reg[31]_0 [6]), .I2(\wb_alu_reg[31]_0 [3]), .I3(\wb_alu_reg[31]_0 [4]), .I4(\wb_alu_reg[31]_0 [2]), .O(BSel)); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT4 #( .INIT(16'hDFFF)) mem_reg_0_0_i_23__0 (.I0(\f_ex_rd2_reg[0] [4]), .I1(\f_ex_rd2_reg[0] [2]), .I2(\f_ex_rd2_reg[0] [3]), .I3(\f_ex_rd2_reg[0] [0]), .O(\ex_wb_inst_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT5 #( .INIT(32'h00900200)) mem_reg_0_0_i_242 (.I0(\wb_alu_reg[31]_0 [2]), .I1(\wb_alu_reg[31]_0 [3]), .I2(\wb_alu_reg[31]_0 [6]), .I3(\wb_alu_reg[31]_0 [4]), .I4(\wb_alu_reg[31]_0 [5]), .O(ASel)); LUT6 #( .INIT(64'h0000000100000000)) mem_reg_0_0_i_243 (.I0(\f_ex_rd2_reg[0] [1]), .I1(\f_ex_rd2_reg[0] [2]), .I2(\f_ex_rd2_reg[0] [0]), .I3(\f_ex_rd2_reg[0] [4]), .I4(\f_ex_rd2_reg[0] [3]), .I5(mem_reg_0_0_i_322_n_0), .O(\ex_wb_inst_reg[3] )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_244 (.I0(Q[15]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[15]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[15]), .O(\wb_alu_reg[15]_0 )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_255 (.I0(Q[14]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[14]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[14]), .O(\wb_alu_reg[14]_0 )); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_26 (.CI(mem_reg_0_0_i_31_n_0), .CO({mem_reg_0_0_i_26_n_0,mem_reg_0_0_i_26_n_1,mem_reg_0_0_i_26_n_2,mem_reg_0_0_i_26_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(data3[11:8]), .S(\pc_reg[16] [11:8])); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_268 (.I0(Q[13]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[13]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[13]), .O(\wb_alu_reg[13]_0 )); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT3 #( .INIT(8'h4F)) mem_reg_0_0_i_26__0 (.I0(\f_ex_inst_reg[12] ), .I1(\wb_alu[29]_i_2 [6]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2]_1 )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_276 (.I0(Q[12]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[12]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[12]), .O(\wb_alu_reg[12]_0 )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_284 (.I0(Q[11]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[11]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[11]), .O(\wb_alu_reg[11]_0 )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_288 (.I0(Q[10]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[10]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[10]), .O(\wb_alu_reg[10]_0 )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_291 (.I0(Q[9]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[9]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[9]), .O(\wb_alu_reg[9]_0 )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_292 (.I0(Q[8]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[8]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[8]), .O(\wb_alu_reg[8]_0 )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_301 (.I0(Q[7]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[7]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[7]), .O(\wb_alu_reg[7]_0 )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_302 (.I0(Q[6]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[6]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[6]), .O(\wb_alu_reg[6]_0 )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_303 (.I0(Q[5]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[5]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[5]), .O(\wb_alu_reg[5]_0 )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_304 (.I0(Q[4]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[4]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[4]), .O(\wb_alu_reg[4]_0 )); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_31 (.CI(mem_reg_0_0_i_36__0_n_0), .CO({mem_reg_0_0_i_31_n_0,mem_reg_0_0_i_31_n_1,mem_reg_0_0_i_31_n_2,mem_reg_0_0_i_31_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(data3[7:4]), .S(\pc_reg[16] [7:4])); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_311 (.I0(Q[3]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[3]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[3]), .O(\wb_alu_reg[3]_0 )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_312 (.I0(Q[2]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[2]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[2]), .O(\wb_alu_reg[2]_0 )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_313 (.I0(Q[1]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[1]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[1]), .O(\wb_alu_reg[1]_0 )); LUT5 #( .INIT(32'hB8BBB888)) mem_reg_0_0_i_314 (.I0(Q[0]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[0]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[0]), .O(\wb_alu_reg[0]_0 )); LUT6 #( .INIT(64'hFFBEFFFFFFFFFFBE)) mem_reg_0_0_i_317 (.I0(mem_reg_0_0_i_326_n_0), .I1(\wb_alu_reg[31]_0 [19]), .I2(\f_ex_rd2_reg[0] [9]), .I3(mem_reg_0_0_i_327_n_0), .I4(\f_ex_rd2_reg[0] [8]), .I5(\wb_alu_reg[31]_0 [18]), .O(mem_reg_0_0_i_317_n_0)); LUT5 #( .INIT(32'h0000FFFD)) mem_reg_0_0_i_318 (.I0(mem_reg_0_0_i_319_0[3]), .I1(mem_reg_0_0_i_319_0[0]), .I2(mem_reg_0_0_i_319_0[1]), .I3(mem_reg_0_0_i_319_0[2]), .I4(mem_reg_0_0_i_328_n_0), .O(mem_reg_0_0_i_318_n_0)); LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) mem_reg_0_0_i_319 (.I0(mem_reg_0_0_i_329_n_0), .I1(\wb_alu_reg[31]_0 [18]), .I2(mem_reg_0_0_i_319_0[7]), .I3(\wb_alu_reg[31]_0 [15]), .I4(mem_reg_0_0_i_319_0[4]), .I5(mem_reg_0_0_i_330_n_0), .O(mem_reg_0_0_i_319_n_0)); LUT5 #( .INIT(32'h0000FFFD)) mem_reg_0_0_i_320 (.I0(\f_ex_rd2_reg[0] [3]), .I1(\f_ex_rd2_reg[0] [1]), .I2(\f_ex_rd2_reg[0] [2]), .I3(\f_ex_rd2_reg[0] [0]), .I4(mem_reg_0_0_i_317_n_0), .O(mem_reg_0_0_i_320_n_0)); LUT6 #( .INIT(64'h0000000004000004)) mem_reg_0_0_i_322 (.I0(mem_reg_0_0_i_332_n_0), .I1(mem_reg_0_0_i_333_n_0), .I2(mem_reg_0_0_i_334_n_0), .I3(\f_ex_rd2_reg[0] [6]), .I4(\wb_alu_reg[31]_0 [11]), .I5(mem_reg_0_0_i_335_n_0), .O(mem_reg_0_0_i_322_n_0)); LUT5 #( .INIT(32'hAAAAAAA2)) mem_reg_0_0_i_323 (.I0(mem_reg_0_0_i_322_n_0), .I1(\f_ex_rd2_reg[0] [3]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [0]), .O(\ex_wb_inst_reg[5] )); LUT6 #( .INIT(64'hFFFFFFFFF6FFFFF6)) mem_reg_0_0_i_324 (.I0(\wb_alu_reg[31]_0 [14]), .I1(mem_reg_0_0_i_319_0[8]), .I2(mem_reg_0_0_i_336_n_0), .I3(mem_reg_0_0_i_319_0[7]), .I4(\wb_alu_reg[31]_0 [13]), .I5(mem_reg_0_0_i_337_n_0), .O(\f_ex_inst_reg[19] )); LUT6 #( .INIT(64'hFFFFFFFF00000001)) mem_reg_0_0_i_326 (.I0(\f_ex_rd2_reg[0] [9]), .I1(\f_ex_rd2_reg[0] [6]), .I2(\f_ex_rd2_reg[0] [5]), .I3(\f_ex_rd2_reg[0] [7]), .I4(\f_ex_rd2_reg[0] [8]), .I5(mem_reg_0_0_i_330_n_0), .O(mem_reg_0_0_i_326_n_0)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) mem_reg_0_0_i_327 (.I0(\wb_alu_reg[31]_0 [15]), .I1(\f_ex_rd2_reg[0] [5]), .I2(\f_ex_rd2_reg[0] [7]), .I3(\wb_alu_reg[31]_0 [17]), .I4(\f_ex_rd2_reg[0] [6]), .I5(\wb_alu_reg[31]_0 [16]), .O(mem_reg_0_0_i_327_n_0)); LUT5 #( .INIT(32'h00000001)) mem_reg_0_0_i_328 (.I0(mem_reg_0_0_i_319_0[7]), .I1(mem_reg_0_0_i_319_0[5]), .I2(mem_reg_0_0_i_319_0[4]), .I3(mem_reg_0_0_i_319_0[8]), .I4(mem_reg_0_0_i_319_0[6]), .O(mem_reg_0_0_i_328_n_0)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) mem_reg_0_0_i_329 (.I0(mem_reg_0_0_i_319_0[6]), .I1(\wb_alu_reg[31]_0 [17]), .I2(mem_reg_0_0_i_319_0[8]), .I3(\wb_alu_reg[31]_0 [19]), .I4(\wb_alu_reg[31]_0 [16]), .I5(mem_reg_0_0_i_319_0[5]), .O(mem_reg_0_0_i_329_n_0)); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT5 #( .INIT(32'hFFF8FFFF)) mem_reg_0_0_i_330 (.I0(\wb_alu_reg[31]_0 [4]), .I1(\wb_alu_reg[31]_0 [6]), .I2(\wb_alu_reg[31]_0 [3]), .I3(\wb_alu_reg[31]_0 [2]), .I4(\wb_alu_reg[31]_0 [5]), .O(mem_reg_0_0_i_330_n_0)); LUT4 #( .INIT(16'h6FF6)) mem_reg_0_0_i_332 (.I0(\f_ex_rd2_reg[0] [9]), .I1(\wb_alu_reg[31]_0 [14]), .I2(\f_ex_rd2_reg[0] [7]), .I3(\wb_alu_reg[31]_0 [12]), .O(mem_reg_0_0_i_332_n_0)); LUT4 #( .INIT(16'h9009)) mem_reg_0_0_i_333 (.I0(\f_ex_rd2_reg[0] [8]), .I1(\wb_alu_reg[31]_0 [13]), .I2(\f_ex_rd2_reg[0] [5]), .I3(\wb_alu_reg[31]_0 [10]), .O(mem_reg_0_0_i_333_n_0)); LUT5 #( .INIT(32'h00000001)) mem_reg_0_0_i_334 (.I0(\f_ex_rd2_reg[0] [8]), .I1(\f_ex_rd2_reg[0] [7]), .I2(\f_ex_rd2_reg[0] [5]), .I3(\f_ex_rd2_reg[0] [6]), .I4(\f_ex_rd2_reg[0] [9]), .O(mem_reg_0_0_i_334_n_0)); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT5 #( .INIT(32'h00508000)) mem_reg_0_0_i_335 (.I0(\wb_alu_reg[31]_0 [3]), .I1(\wb_alu_reg[31]_0 [5]), .I2(\wb_alu_reg[31]_0 [2]), .I3(\wb_alu_reg[31]_0 [6]), .I4(\wb_alu_reg[31]_0 [4]), .O(mem_reg_0_0_i_335_n_0)); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) mem_reg_0_0_i_336 (.I0(\wb_alu_reg[31]_0 [10]), .I1(mem_reg_0_0_i_319_0[4]), .I2(mem_reg_0_0_i_319_0[5]), .I3(\wb_alu_reg[31]_0 [11]), .I4(mem_reg_0_0_i_319_0[6]), .I5(\wb_alu_reg[31]_0 [12]), .O(mem_reg_0_0_i_336_n_0)); LUT6 #( .INIT(64'h40002020FFFFFFFF)) mem_reg_0_0_i_337 (.I0(\wb_alu_reg[31]_0 [4]), .I1(\wb_alu_reg[31]_0 [6]), .I2(\wb_alu_reg[31]_0 [2]), .I3(\wb_alu_reg[31]_0 [5]), .I4(\wb_alu_reg[31]_0 [3]), .I5(mem_reg_0_0_i_318_n_0), .O(mem_reg_0_0_i_337_n_0)); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_36__0 (.CI(\<const0> ), .CO({mem_reg_0_0_i_36__0_n_0,mem_reg_0_0_i_36__0_n_1,mem_reg_0_0_i_36__0_n_2,mem_reg_0_0_i_36__0_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\pc_reg[16] [1],\<const0> }), .O(data3[3:0]), .S({\pc_reg[16] [3:2],mem_reg_0_0_i_47_n_0,\pc_reg[16] [0]})); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT3 #( .INIT(8'h4F)) mem_reg_0_0_i_38__0 (.I0(\f_ex_inst_reg[12] ), .I1(\wb_alu[29]_i_2 [5]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2]_2 )); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_40__0 (.CI(mem_reg_0_0_i_43_n_0), .CO({\ex_wb_pc_reg[16] ,mem_reg_0_0_i_40__0_n_1,mem_reg_0_0_i_40__0_n_2,mem_reg_0_0_i_40__0_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(data2[15:12]), .S(mem_reg_0_0_i_25[15:12])); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_42__0 (.CI(mem_reg_0_0_i_44_n_0), .CO({\f_ex_pc_reg[15] ,mem_reg_0_0_i_42__0_n_1,mem_reg_0_0_i_42__0_n_2,mem_reg_0_0_i_42__0_n_3}), .CYINIT(\<const0> ), .DI(mem_reg_3_3_0[15:12]), .O(\f_ex_pc_reg[15]_0 ), .S({mem_reg_0_0_i_50__0_n_0,mem_reg_0_0_i_51__0_n_0,mem_reg_0_0_i_52_n_0,mem_reg_0_0_i_53__0_n_0})); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_43 (.CI(mem_reg_0_0_i_45__0_n_0), .CO({mem_reg_0_0_i_43_n_0,mem_reg_0_0_i_43_n_1,mem_reg_0_0_i_43_n_2,mem_reg_0_0_i_43_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(data2[11:8]), .S(mem_reg_0_0_i_25[11:8])); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_44 (.CI(mem_reg_0_0_i_46__0_n_0), .CO({mem_reg_0_0_i_44_n_0,mem_reg_0_0_i_44_n_1,mem_reg_0_0_i_44_n_2,mem_reg_0_0_i_44_n_3}), .CYINIT(\<const0> ), .DI(mem_reg_3_3_0[11:8]), .O(\f_ex_pc_reg[11] ), .S({mem_reg_0_0_i_54__0_n_0,mem_reg_0_0_i_55_n_0,mem_reg_0_0_i_56__0_n_0,mem_reg_0_0_i_57__0_n_0})); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT3 #( .INIT(8'h4F)) mem_reg_0_0_i_44__0 (.I0(\f_ex_inst_reg[12] ), .I1(\wb_alu[29]_i_2 [4]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2]_3 )); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_45__0 (.CI(mem_reg_0_0_i_48__0_n_0), .CO({mem_reg_0_0_i_45__0_n_0,mem_reg_0_0_i_45__0_n_1,mem_reg_0_0_i_45__0_n_2,mem_reg_0_0_i_45__0_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(data2[7:4]), .S(mem_reg_0_0_i_25[7:4])); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_46__0 (.CI(mem_reg_0_0_i_49__0_n_0), .CO({mem_reg_0_0_i_46__0_n_0,mem_reg_0_0_i_46__0_n_1,mem_reg_0_0_i_46__0_n_2,mem_reg_0_0_i_46__0_n_3}), .CYINIT(\<const0> ), .DI(mem_reg_3_3_0[7:4]), .O(\f_ex_pc_reg[7] ), .S({mem_reg_0_0_i_58__0_n_0,mem_reg_0_0_i_59__0_n_0,mem_reg_0_0_i_60__0_n_0,mem_reg_0_0_i_61__0_n_0})); LUT1 #( .INIT(2'h1)) mem_reg_0_0_i_47 (.I0(\pc_reg[16] [1]), .O(mem_reg_0_0_i_47_n_0)); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT3 #( .INIT(8'h4F)) mem_reg_0_0_i_47__0 (.I0(\f_ex_inst_reg[12] ), .I1(\wb_alu[29]_i_2 [3]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2]_4 )); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_48__0 (.CI(\<const0> ), .CO({mem_reg_0_0_i_48__0_n_0,mem_reg_0_0_i_48__0_n_1,mem_reg_0_0_i_48__0_n_2,mem_reg_0_0_i_48__0_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,mem_reg_0_0_i_25[1],\<const0> }), .O(data2[3:0]), .S({mem_reg_0_0_i_25[3:2],mem_reg_0_0_i_62_n_0,mem_reg_0_0_i_25[0]})); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_0_0_i_49__0 (.CI(\<const0> ), .CO({mem_reg_0_0_i_49__0_n_0,mem_reg_0_0_i_49__0_n_1,mem_reg_0_0_i_49__0_n_2,mem_reg_0_0_i_49__0_n_3}), .CYINIT(\<const0> ), .DI(mem_reg_3_3_0[3:0]), .O(O), .S({mem_reg_0_0_i_63__0_n_0,mem_reg_0_0_i_64__0_n_0,mem_reg_0_0_i_65__0_n_0,mem_reg_0_0_i_66_n_0})); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_50__0 (.I0(mem_reg_3_3_0[15]), .I1(mem_reg_0_0_i_42__0_0[15]), .O(mem_reg_0_0_i_50__0_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_51__0 (.I0(mem_reg_3_3_0[14]), .I1(mem_reg_0_0_i_42__0_0[14]), .O(mem_reg_0_0_i_51__0_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_52 (.I0(mem_reg_3_3_0[13]), .I1(mem_reg_0_0_i_42__0_0[13]), .O(mem_reg_0_0_i_52_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_53__0 (.I0(mem_reg_3_3_0[12]), .I1(mem_reg_0_0_i_42__0_0[12]), .O(mem_reg_0_0_i_53__0_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_54__0 (.I0(mem_reg_3_3_0[11]), .I1(mem_reg_0_0_i_42__0_0[11]), .O(mem_reg_0_0_i_54__0_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_55 (.I0(mem_reg_3_3_0[10]), .I1(mem_reg_0_0_i_42__0_0[10]), .O(mem_reg_0_0_i_55_n_0)); (* SOFT_HLUTNM = "soft_lutpair127" *) LUT3 #( .INIT(8'hFE)) mem_reg_0_0_i_55__0 (.I0(douta_reg_0), .I1(ALUSel[1]), .I2(ALUSel[0]), .O(\f_ex_inst_reg[12] )); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_56__0 (.I0(mem_reg_3_3_0[9]), .I1(mem_reg_0_0_i_42__0_0[9]), .O(mem_reg_0_0_i_56__0_n_0)); LUT6 #( .INIT(64'h00FF000400AA0000)) mem_reg_0_0_i_57 (.I0(\wb_alu_reg[31]_0 [2]), .I1(\wb_alu_reg[31]_0 [7]), .I2(\wb_alu_reg[31]_0 [8]), .I3(mem_reg_0_0_i_154_n_0), .I4(\wb_alu_reg[31]_0 [5]), .I5(\wb_alu_reg[31]_0 [20]), .O(ALUSel[2])); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_57__0 (.I0(mem_reg_3_3_0[8]), .I1(mem_reg_0_0_i_42__0_0[8]), .O(mem_reg_0_0_i_57__0_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_58__0 (.I0(mem_reg_3_3_0[7]), .I1(mem_reg_0_0_i_42__0_0[7]), .O(mem_reg_0_0_i_58__0_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_59__0 (.I0(mem_reg_3_3_0[6]), .I1(mem_reg_0_0_i_42__0_0[6]), .O(mem_reg_0_0_i_59__0_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_60__0 (.I0(mem_reg_3_3_0[5]), .I1(mem_reg_0_0_i_42__0_0[5]), .O(mem_reg_0_0_i_60__0_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_61__0 (.I0(mem_reg_3_3_0[4]), .I1(mem_reg_0_0_i_42__0_0[4]), .O(mem_reg_0_0_i_61__0_n_0)); LUT1 #( .INIT(2'h1)) mem_reg_0_0_i_62 (.I0(mem_reg_0_0_i_25[1]), .O(mem_reg_0_0_i_62_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_63__0 (.I0(mem_reg_3_3_0[3]), .I1(mem_reg_0_0_i_42__0_0[3]), .O(mem_reg_0_0_i_63__0_n_0)); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT3 #( .INIT(8'hBA)) mem_reg_0_0_i_64 (.I0(ALUSel[2]), .I1(\f_ex_inst_reg[12] ), .I2(douta_reg_0_0[1]), .O(\f_ex_inst_reg[2]_8 )); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_64__0 (.I0(mem_reg_3_3_0[2]), .I1(mem_reg_0_0_i_42__0_0[2]), .O(mem_reg_0_0_i_64__0_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_65__0 (.I0(mem_reg_3_3_0[1]), .I1(mem_reg_0_0_i_42__0_0[1]), .O(mem_reg_0_0_i_65__0_n_0)); LUT2 #( .INIT(4'h6)) mem_reg_0_0_i_66 (.I0(mem_reg_3_3_0[0]), .I1(mem_reg_0_0_i_42__0_0[0]), .O(mem_reg_0_0_i_66_n_0)); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT3 #( .INIT(8'h4F)) mem_reg_0_0_i_66__0 (.I0(\f_ex_inst_reg[12] ), .I1(\wb_alu[29]_i_2 [2]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2]_5 )); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT3 #( .INIT(8'hBA)) mem_reg_0_0_i_69 (.I0(ALUSel[2]), .I1(\f_ex_inst_reg[12] ), .I2(douta_reg_0_0[0]), .O(\f_ex_inst_reg[2]_9 )); LUT3 #( .INIT(8'h4F)) mem_reg_0_0_i_71 (.I0(\f_ex_inst_reg[12] ), .I1(\wb_alu[29]_i_2 [1]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2]_6 )); LUT6 #( .INIT(64'h000C000000080008)) mem_reg_0_0_i_78 (.I0(\wb_alu_reg[31]_0 [9]), .I1(\wb_alu_reg[31]_0 [4]), .I2(\wb_alu_reg[31]_0 [3]), .I3(\wb_alu_reg[31]_0 [6]), .I4(\wb_alu_reg[31]_0 [5]), .I5(\wb_alu_reg[31]_0 [2]), .O(ALUSel[1])); LUT6 #( .INIT(64'h0000000700000000)) mem_reg_0_0_i_94 (.I0(\wb_alu_reg[31]_0 [7]), .I1(\wb_alu_reg[31]_0 [8]), .I2(\wb_alu_reg[31]_0 [6]), .I3(\wb_alu_reg[31]_0 [3]), .I4(\wb_alu_reg[31]_0 [9]), .I5(\f_ex_inst_reg[4] ), .O(MemRW[0])); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "2" *) (* ram_slice_end = "3" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_0_1 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:11],ex_alu[8:0],ADDRARDADDR[1:0],\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[3:2]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[3:2]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[0],imem_wea[0],imem_wea[0],imem_wea[0]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_0_1_i_6 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[3]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[3]), .I5(mem_reg_3_3_i_3_0[3]), .O(\wb_alu_reg[3] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_0_1_i_8 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[2]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[2]), .I5(mem_reg_3_3_i_3_0[2]), .O(\wb_alu_reg[2] )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "4" *) (* ram_slice_end = "5" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_0_2 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu,ADDRARDADDR[1:0],\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[5:4]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[5:4]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[0],imem_wea[0],imem_wea[0],imem_wea[0]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_0_2_i_6 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[5]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[5]), .I5(mem_reg_3_3_i_3_0[5]), .O(\wb_alu_reg[5] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_0_2_i_8 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[4]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[4]), .I5(mem_reg_3_3_i_3_0[4]), .O(\wb_alu_reg[4] )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "6" *) (* ram_slice_end = "7" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_0_3 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu,ADDRARDADDR[1:0],\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[7:6]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[7:6]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[0],imem_wea[0],imem_wea[0],imem_wea[0]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_0_3_i_5 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[7]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[7]), .I5(mem_reg_3_3_i_3_0[7]), .O(\wb_alu_reg[7] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_0_3_i_6 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[6]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[6]), .I5(mem_reg_3_3_i_3_0[6]), .O(\wb_alu_reg[6] )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "8" *) (* ram_slice_end = "9" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_1_0 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu,ADDRARDADDR[1:0],\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[9:8]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[9:8]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[1],imem_wea[1],imem_wea[1],imem_wea[1]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_1_0_i_10 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[8]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[8]), .I5(mem_reg_3_3_i_3_0[8]), .O(\wb_alu_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT2 #( .INIT(4'hE)) mem_reg_1_0_i_11 (.I0(\wb_alu_reg[31]_0 [3]), .I1(\wb_alu_reg[31]_0 [6]), .O(\f_ex_inst_reg[3] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_1_0_i_9 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[9]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[9]), .I5(mem_reg_3_3_i_3_0[9]), .O(\wb_alu_reg[9] )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "10" *) (* ram_slice_end = "11" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_1_1 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:11],ex_alu[8:0],ADDRARDADDR[1:0],\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[11:10]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[11:10]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[1],imem_wea[1],imem_wea[1],imem_wea[1]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_1_1_i_5 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[11]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[11]), .I5(mem_reg_3_3_i_3_0[11]), .O(\wb_alu_reg[11] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_1_1_i_6 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[10]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[10]), .I5(mem_reg_3_3_i_3_0[10]), .O(\wb_alu_reg[10] )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "12" *) (* ram_slice_end = "13" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_1_2 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:11],ex_alu[8:0],ADDRARDADDR[1:0],\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[13:12]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[13:12]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[1],imem_wea[1],imem_wea[1],imem_wea[1]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_1_2_i_5 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[13]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[13]), .I5(mem_reg_3_3_i_3_0[13]), .O(\wb_alu_reg[13] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_1_2_i_6 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[12]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[12]), .I5(mem_reg_3_3_i_3_0[12]), .O(\wb_alu_reg[12] )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "14" *) (* ram_slice_end = "15" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_1_3 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:11],ex_alu[8:0],ADDRARDADDR[1:0],\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[15:14]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[15:14]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[1],imem_wea[1],imem_wea[1],imem_wea[1]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_1_3_i_5 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[15]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[15]), .I5(mem_reg_3_3_i_3_0[15]), .O(\wb_alu_reg[15] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_1_3_i_6 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[14]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[14]), .I5(mem_reg_3_3_i_3_0[14]), .O(\wb_alu_reg[14] )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "16" *) (* ram_slice_end = "17" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_2_0 (.ADDRARDADDR({\<const1> ,ADDRARDADDR,\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[17:16]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[17:16]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[2],imem_wea[2],imem_wea[2],imem_wea[2]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'h0000010000000000)) mem_reg_2_0_i_19 (.I0(\wb_alu_reg[31]_0 [3]), .I1(\wb_alu_reg[31]_0 [6]), .I2(\wb_alu_reg[31]_0 [9]), .I3(\wb_alu_reg[31]_0 [8]), .I4(\wb_alu_reg[31]_0 [7]), .I5(\f_ex_inst_reg[4] ), .O(MemRW[2])); LUT6 #( .INIT(64'h0000011000000000)) mem_reg_2_0_i_20 (.I0(\wb_alu_reg[31]_0 [3]), .I1(\wb_alu_reg[31]_0 [6]), .I2(\wb_alu_reg[31]_0 [8]), .I3(\wb_alu_reg[31]_0 [7]), .I4(\wb_alu_reg[31]_0 [9]), .I5(\f_ex_inst_reg[4] ), .O(MemRW[1])); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_2_0_i_21 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[17]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[17]), .I5(mem_reg_3_3_i_3_0[17]), .O(\wb_alu_reg[17] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_2_0_i_22 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[16]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[16]), .I5(mem_reg_3_3_i_3_0[16]), .O(\wb_alu_reg[16] )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "18" *) (* ram_slice_end = "19" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_2_1 (.ADDRARDADDR({\<const1> ,ADDRARDADDR,\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[19:18]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[19:18]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[2],imem_wea[2],imem_wea[2],imem_wea[2]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_2_1_i_7 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[19]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[19]), .I5(mem_reg_3_3_i_3_0[19]), .O(\wb_alu_reg[19] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_2_1_i_8 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[18]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[18]), .I5(mem_reg_3_3_i_3_0[18]), .O(\wb_alu_reg[18] )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "20" *) (* ram_slice_end = "21" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_2_2 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu[9],ADDRARDADDR[10:2],addra,\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[21:20]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[21:20]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[2],imem_wea[2],imem_wea[2],imem_wea[2]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_2_2_i_10 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[20]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[20]), .I5(mem_reg_3_3_i_3_0[20]), .O(\wb_alu_reg[20] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_2_2_i_9 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[21]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[21]), .I5(mem_reg_3_3_i_3_0[21]), .O(\wb_alu_reg[21] )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "22" *) (* ram_slice_end = "23" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_2_3 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu[9],ADDRARDADDR[10:2],addra,\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[23:22]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[23:22]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[2],imem_wea[2],imem_wea[2],imem_wea[2]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_2_3_i_7 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[23]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[23]), .I5(mem_reg_3_3_i_3_0[23]), .O(\wb_alu_reg[23] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_2_3_i_8 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[22]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[22]), .I5(mem_reg_3_3_i_3_0[22]), .O(\wb_alu_reg[22] )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "24" *) (* ram_slice_end = "25" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_3_0 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu[9],ADDRARDADDR[10:2],addra,\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[25:24]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[25:24]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[3],imem_wea[3],imem_wea[3],imem_wea[3]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_3_0_i_10 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[25]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[25]), .I5(mem_reg_3_3_i_3_0[25]), .O(\wb_alu_reg[25] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_3_0_i_11 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[24]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[24]), .I5(mem_reg_3_3_i_3_0[24]), .O(\wb_alu_reg[24] )); (* SOFT_HLUTNM = "soft_lutpair128" *) LUT3 #( .INIT(8'h04)) mem_reg_3_0_i_12 (.I0(\wb_alu_reg[31]_0 [9]), .I1(\wb_alu_reg[31]_0 [8]), .I2(\wb_alu_reg[31]_0 [7]), .O(\f_ex_inst_reg[14] )); (* SOFT_HLUTNM = "soft_lutpair128" *) LUT3 #( .INIT(8'h04)) mem_reg_3_0_i_4 (.I0(\wb_alu_reg[31]_0 [7]), .I1(\wb_alu_reg[31]_0 [8]), .I2(\wb_alu_reg[31]_0 [9]), .O(\f_ex_inst_reg[12]_1 )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "26" *) (* ram_slice_end = "27" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_3_1 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu[9],ADDRARDADDR[10:2],addra,\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[27:26]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[27:26]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[3],imem_wea[3],imem_wea[3],imem_wea[3]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_3_1_i_5 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[27]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[27]), .I5(mem_reg_3_3_i_3_0[27]), .O(\wb_alu_reg[27] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_3_1_i_6 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[26]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[26]), .I5(mem_reg_3_3_i_3_0[26]), .O(\wb_alu_reg[26] )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "28" *) (* ram_slice_end = "29" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_3_2 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu[9],ADDRARDADDR[10:2],addra,\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[29:28]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[29:28]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[3],imem_wea[3],imem_wea[3],imem_wea[3]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_3_2_i_5 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[29]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[29]), .I5(mem_reg_3_3_i_3_0[29]), .O(\wb_alu_reg[29] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_3_2_i_6 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[28]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[28]), .I5(mem_reg_3_3_i_3_0[28]), .O(\wb_alu_reg[28] )); (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d2" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d2" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-15 {cell *THIS*} {string {address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.}}} {SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "524288" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "16383" *) (* ram_offset = "0" *) (* ram_slice_begin = "30" *) (* ram_slice_end = "31" *) RAMB36E1 #( .DOA_REG(0), .DOB_REG(0), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .RAM_EXTENSION_A("NONE"), .RAM_EXTENSION_B("NONE"), .RAM_MODE("TDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(2), .READ_WIDTH_B(2), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("WRITE_FIRST"), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2)) mem_reg_3_3 (.ADDRARDADDR({\<const1> ,ADDRARDADDR[13:12],ex_alu[9],ADDRARDADDR[10:2],addra,\<const1> }), .ADDRBWRADDR({\<const1> ,mem_reg_3_3_1,\<const1> }), .CASCADEINA(\<const1> ), .CASCADEINB(\<const1> ), .CLKARDCLK(cpu_clk), .CLKBWRCLK(cpu_clk), .DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_1_in[31:30]}), .DIBDI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> }), .DIPADIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DIPBDIP({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .DOBDO(doutb[31:30]), .ENARDEN(mem_reg_3_3_0[16]), .ENBWREN(\<const1> ), .REGCEAREGCE(\<const0> ), .REGCEB(\<const0> ), .RSTRAMARSTRAM(\<const0> ), .RSTRAMB(\<const0> ), .RSTREGARSTREG(\<const0> ), .RSTREGB(\<const0> ), .WEA({imem_wea[3],imem_wea[3],imem_wea[3],imem_wea[3]}), .WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> })); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_3_3_i_5 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[31]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[31]), .I5(mem_reg_3_3_i_3_0[31]), .O(\wb_alu_reg[31] )); LUT6 #( .INIT(64'hF0FFF0DDF022F000)) mem_reg_3_3_i_6 (.I0(mem_reg_0_0_i_318_n_0), .I1(mem_reg_0_0_i_319_n_0), .I2(Q[30]), .I3(mem_reg_0_0_i_320_n_0), .I4(mem_reg_3_3_i_3[30]), .I5(mem_reg_3_3_i_3_0[30]), .O(\wb_alu_reg[30] )); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_100 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[7]), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[7]), .O(mem_reg_r1_0_31_0_5_i_100_n_0)); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_103 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[18]), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[18]), .O(mem_reg_r1_0_31_0_5_i_103_n_0)); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_104 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[3]), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[3]), .O(mem_reg_r1_0_31_0_5_i_104_n_0)); LUT4 #( .INIT(16'hF444)) mem_reg_r1_0_31_0_5_i_105 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[10]), .I2(\wb_alu_reg[0]_2 ), .I3(br_corr_cnt_reg[10]), .O(mem_reg_r1_0_31_0_5_i_105_n_0)); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_106 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[17]), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[17]), .O(mem_reg_r1_0_31_0_5_i_106_n_0)); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_107 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[2]), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[2]), .O(mem_reg_r1_0_31_0_5_i_107_n_0)); LUT4 #( .INIT(16'hF444)) mem_reg_r1_0_31_0_5_i_108 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[9]), .I2(\wb_alu_reg[0]_2 ), .I3(br_corr_cnt_reg[9]), .O(mem_reg_r1_0_31_0_5_i_108_n_0)); LUT4 #( .INIT(16'hF444)) mem_reg_r1_0_31_0_5_i_109 (.I0(\wb_alu_reg[0]_1 ), .I1(insts_cnt_reg[20]), .I2(\wb_alu_reg[0]_2 ), .I3(br_corr_cnt_reg[20]), .O(mem_reg_r1_0_31_0_5_i_109_n_0)); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_110 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[5]), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[5]), .O(mem_reg_r1_0_31_0_5_i_110_n_0)); LUT4 #( .INIT(16'hF444)) mem_reg_r1_0_31_0_5_i_111 (.I0(\wb_alu_reg[0]_1 ), .I1(insts_cnt_reg[12]), .I2(\wb_alu_reg[0]_2 ), .I3(br_corr_cnt_reg[12]), .O(mem_reg_r1_0_31_0_5_i_111_n_0)); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_112 (.I0(\wb_alu_reg[0]_1 ), .I1(insts_cnt_reg[19]), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[19]), .O(mem_reg_r1_0_31_0_5_i_112_n_0)); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_113 (.I0(\wb_alu_reg[0]_1 ), .I1(insts_cnt_reg[4]), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[4]), .O(mem_reg_r1_0_31_0_5_i_113_n_0)); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_114 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[11]), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[11]), .O(mem_reg_r1_0_31_0_5_i_114_n_0)); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT5 #( .INIT(32'h00800F80)) mem_reg_r1_0_31_0_5_i_13 (.I0(\f_ex_rd2_reg[0] [0]), .I1(\f_ex_rd2_reg[0] [3]), .I2(\f_ex_rd2_reg[0] [4]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [1]), .O(\ex_wb_inst_reg[2] )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_0_5_i_23 (.I0(\ex_wb_inst_reg[6] ), .I1(data2[4]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[5]), .O(\ex_wb_inst_reg[3]_1 )); LUT5 #( .INIT(32'h0000D0DD)) mem_reg_r1_0_31_0_5_i_50 (.I0(cycle_cnt_reg[16]), .I1(\wb_alu_reg[2]_1 ), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[16]), .I4(mem_reg_r1_0_31_0_5_i_92_n_0), .O(\cycle_cnt_reg[25] )); LUT5 #( .INIT(32'h0000D0DD)) mem_reg_r1_0_31_0_5_i_52 (.I0(insts_cnt_reg[1]), .I1(\wb_alu_reg[0]_1 ), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[1]), .I4(mem_reg_r1_0_31_0_5_i_93_n_0), .O(insts_cnt_reg_9_sn_1)); LUT6 #( .INIT(64'h0000000000020000)) mem_reg_r1_0_31_0_5_i_53 (.I0(\wb_alu_reg[30]_0 ), .I1(Q[23]), .I2(Q[22]), .I3(\wb_alu_reg[16]_1 ), .I4(mem_reg_r1_0_31_18_23_i_24), .I5(\wb_alu_reg[13]_1 ), .O(\wb_alu_reg[23]_0 )); LUT5 #( .INIT(32'h0000D0DD)) mem_reg_r1_0_31_0_5_i_55 (.I0(cycle_cnt_reg[8]), .I1(\wb_alu_reg[2]_1 ), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[8]), .I4(mem_reg_r1_0_31_0_5_i_94_n_0), .O(cycle_cnt_reg_17_sn_1)); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_0_5_i_59 (.I0(insts_cnt_reg[15]), .I1(\wb_alu_reg[0]_1 ), .I2(br_corr_cnt_reg[15]), .I3(\wb_alu_reg[0]_2 ), .I4(mem_reg_r1_0_31_0_5_i_98_n_0), .O(\insts_cnt_reg[24] )); LUT5 #( .INIT(32'h0000D0DD)) mem_reg_r1_0_31_0_5_i_61 (.I0(cycle_cnt_reg[0]), .I1(\wb_alu_reg[2]_1 ), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[0]), .I4(mem_reg_r1_0_31_0_5_i_99_n_0), .O(cycle_cnt_reg_8_sn_1)); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_0_5_i_63 (.I0(insts_cnt_reg[7]), .I1(\wb_alu_reg[0]_1 ), .I2(br_corr_cnt_reg[7]), .I3(\wb_alu_reg[0]_2 ), .I4(mem_reg_r1_0_31_0_5_i_100_n_0), .O(insts_cnt_reg_16_sn_1)); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_0_5_i_65 (.I0(insts_cnt_reg[18]), .I1(\wb_alu_reg[0]_1 ), .I2(br_corr_cnt_reg[18]), .I3(\wb_alu_reg[0]_2 ), .I4(mem_reg_r1_0_31_0_5_i_103_n_0), .O(\insts_cnt_reg[27] )); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_0_5_i_67 (.I0(insts_cnt_reg[3]), .I1(\wb_alu_reg[0]_1 ), .I2(br_corr_cnt_reg[3]), .I3(\wb_alu_reg[0]_2 ), .I4(mem_reg_r1_0_31_0_5_i_104_n_0), .O(insts_cnt_reg_11_sn_1)); LUT5 #( .INIT(32'h0000D0DD)) mem_reg_r1_0_31_0_5_i_69 (.I0(insts_cnt_reg[10]), .I1(\wb_alu_reg[0]_1 ), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[10]), .I4(mem_reg_r1_0_31_0_5_i_105_n_0), .O(insts_cnt_reg_19_sn_1)); LUT6 #( .INIT(64'hFFFEFFFFFFFFFFFF)) mem_reg_r1_0_31_0_5_i_71 (.I0(Q[0]), .I1(Q[1]), .I2(Q[3]), .I3(Q[5]), .I4(Q[4]), .I5(Q[2]), .O(\wb_alu_reg[0]_1 )); LUT6 #( .INIT(64'hFFFFFFFFFDFFFFFF)) mem_reg_r1_0_31_0_5_i_72 (.I0(Q[4]), .I1(Q[1]), .I2(Q[0]), .I3(Q[3]), .I4(Q[2]), .I5(Q[5]), .O(\wb_alu_reg[4]_1 )); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_0_5_i_73 (.I0(insts_cnt_reg[17]), .I1(\wb_alu_reg[0]_1 ), .I2(br_corr_cnt_reg[17]), .I3(\wb_alu_reg[0]_2 ), .I4(mem_reg_r1_0_31_0_5_i_106_n_0), .O(\insts_cnt_reg[26] )); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_0_5_i_75 (.I0(insts_cnt_reg[2]), .I1(\wb_alu_reg[0]_1 ), .I2(br_corr_cnt_reg[2]), .I3(\wb_alu_reg[0]_2 ), .I4(mem_reg_r1_0_31_0_5_i_107_n_0), .O(insts_cnt_reg_10_sn_1)); LUT5 #( .INIT(32'h0000D0DD)) mem_reg_r1_0_31_0_5_i_77 (.I0(insts_cnt_reg[9]), .I1(\wb_alu_reg[0]_1 ), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[9]), .I4(mem_reg_r1_0_31_0_5_i_108_n_0), .O(insts_cnt_reg_18_sn_1)); LUT5 #( .INIT(32'h0000D0DD)) mem_reg_r1_0_31_0_5_i_79 (.I0(cycle_cnt_reg[20]), .I1(\wb_alu_reg[2]_1 ), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[20]), .I4(mem_reg_r1_0_31_0_5_i_109_n_0), .O(\cycle_cnt_reg[29] )); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_0_5_i_81 (.I0(insts_cnt_reg[5]), .I1(\wb_alu_reg[0]_1 ), .I2(br_corr_cnt_reg[5]), .I3(\wb_alu_reg[0]_2 ), .I4(mem_reg_r1_0_31_0_5_i_110_n_0), .O(insts_cnt_reg_13_sn_1)); LUT5 #( .INIT(32'h0000D0DD)) mem_reg_r1_0_31_0_5_i_83 (.I0(cycle_cnt_reg[12]), .I1(\wb_alu_reg[2]_1 ), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[12]), .I4(mem_reg_r1_0_31_0_5_i_111_n_0), .O(\cycle_cnt_reg[21] )); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_0_5_i_85 (.I0(cycle_cnt_reg[19]), .I1(\wb_alu_reg[2]_1 ), .I2(br_corr_cnt_reg[19]), .I3(\wb_alu_reg[0]_2 ), .I4(mem_reg_r1_0_31_0_5_i_112_n_0), .O(\cycle_cnt_reg[28] )); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_0_5_i_87 (.I0(cycle_cnt_reg[4]), .I1(\wb_alu_reg[2]_1 ), .I2(br_corr_cnt_reg[4]), .I3(\wb_alu_reg[0]_2 ), .I4(mem_reg_r1_0_31_0_5_i_113_n_0), .O(cycle_cnt_reg_12_sn_1)); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_0_5_i_89 (.I0(insts_cnt_reg[11]), .I1(\wb_alu_reg[0]_1 ), .I2(br_corr_cnt_reg[11]), .I3(\wb_alu_reg[0]_2 ), .I4(mem_reg_r1_0_31_0_5_i_114_n_0), .O(insts_cnt_reg_20_sn_1)); LUT6 #( .INIT(64'hFFFFFFFEFFFFFFFF)) mem_reg_r1_0_31_0_5_i_91 (.I0(Q[2]), .I1(Q[5]), .I2(Q[3]), .I3(Q[1]), .I4(Q[0]), .I5(Q[4]), .O(\wb_alu_reg[2]_1 )); LUT4 #( .INIT(16'hF444)) mem_reg_r1_0_31_0_5_i_92 (.I0(\wb_alu_reg[0]_1 ), .I1(insts_cnt_reg[16]), .I2(\wb_alu_reg[0]_2 ), .I3(br_corr_cnt_reg[16]), .O(mem_reg_r1_0_31_0_5_i_92_n_0)); LUT4 #( .INIT(16'hF444)) mem_reg_r1_0_31_0_5_i_93 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[1]), .I2(\wb_alu_reg[0]_2 ), .I3(br_corr_cnt_reg[1]), .O(mem_reg_r1_0_31_0_5_i_93_n_0)); LUT4 #( .INIT(16'hF444)) mem_reg_r1_0_31_0_5_i_94 (.I0(\wb_alu_reg[0]_1 ), .I1(insts_cnt_reg[8]), .I2(\wb_alu_reg[0]_2 ), .I3(br_corr_cnt_reg[8]), .O(mem_reg_r1_0_31_0_5_i_94_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFEFFFF)) mem_reg_r1_0_31_0_5_i_97 (.I0(Q[4]), .I1(Q[1]), .I2(Q[0]), .I3(Q[3]), .I4(Q[2]), .I5(Q[5]), .O(\wb_alu_reg[4]_2 )); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_98 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[15]), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[15]), .O(mem_reg_r1_0_31_0_5_i_98_n_0)); LUT4 #( .INIT(16'hF444)) mem_reg_r1_0_31_0_5_i_99 (.I0(\wb_alu_reg[0]_1 ), .I1(insts_cnt_reg[0]), .I2(\wb_alu_reg[0]_2 ), .I3(br_corr_cnt_reg[0]), .O(mem_reg_r1_0_31_0_5_i_99_n_0)); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_12_17_i_12 (.I0(\ex_wb_inst_reg[6] ), .I1(data2[11]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[12]), .O(\ex_wb_inst_reg[3]_8 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_12_17_i_15 (.I0(\ex_wb_inst_reg[6] ), .I1(data2[14]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[15]), .O(\ex_wb_inst_reg[3]_11 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_12_17_i_18 (.I0(\ex_wb_inst_reg[6] ), .I1(data2[13]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[14]), .O(\ex_wb_inst_reg[3]_10 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_12_17_i_20 (.I0(\ex_wb_inst_reg[6] ), .I1(\pprev_data_reg[21] [0]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[17]), .O(\ex_wb_inst_reg[3]_13 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_12_17_i_22 (.I0(\ex_wb_inst_reg[6] ), .I1(data2[15]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[16]), .O(\ex_wb_inst_reg[3]_12 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_12_17_i_9 (.I0(\ex_wb_inst_reg[6] ), .I1(data2[12]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[13]), .O(\ex_wb_inst_reg[3]_9 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_18_23_i_10 (.I0(\ex_wb_inst_reg[6] ), .I1(\pprev_data_reg[21] [1]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[18]), .O(\ex_wb_inst_reg[3]_14 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_18_23_i_12 (.I0(\ex_wb_inst_reg[6] ), .I1(\pprev_data_reg[21] [4]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[21]), .O(\ex_wb_inst_reg[3]_17 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_18_23_i_14 (.I0(\ex_wb_inst_reg[6] ), .I1(\pprev_data_reg[21] [3]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[20]), .O(\ex_wb_inst_reg[3]_16 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_18_23_i_8 (.I0(\ex_wb_inst_reg[6] ), .I1(\pprev_data_reg[21] [2]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[19]), .O(\ex_wb_inst_reg[3]_15 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_6_11_i_10 (.I0(\ex_wb_inst_reg[6] ), .I1(data2[5]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[6]), .O(\ex_wb_inst_reg[3]_2 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_6_11_i_13 (.I0(\ex_wb_inst_reg[6] ), .I1(data2[8]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[9]), .O(\ex_wb_inst_reg[3]_5 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_6_11_i_16 (.I0(\ex_wb_inst_reg[6] ), .I1(data2[7]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[8]), .O(\ex_wb_inst_reg[3]_4 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_6_11_i_19 (.I0(\ex_wb_inst_reg[6] ), .I1(data2[10]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[11]), .O(\ex_wb_inst_reg[3]_7 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_6_11_i_22 (.I0(\ex_wb_inst_reg[6] ), .I1(data2[9]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[10]), .O(\ex_wb_inst_reg[3]_6 )); LUT5 #( .INIT(32'h0000D0DD)) mem_reg_r1_0_31_6_11_i_40 (.I0(insts_cnt_reg[14]), .I1(\wb_alu_reg[0]_1 ), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[14]), .I4(mem_reg_r1_0_31_6_11_i_57_n_0), .O(\insts_cnt_reg[23] )); LUT6 #( .INIT(64'h0000000000000100)) mem_reg_r1_0_31_6_11_i_42 (.I0(Q[0]), .I1(Q[1]), .I2(Q[4]), .I3(Q[5]), .I4(Q[3]), .I5(Q[2]), .O(\wb_alu_reg[0]_2 )); LUT5 #( .INIT(32'h0000D0DD)) mem_reg_r1_0_31_6_11_i_45 (.I0(insts_cnt_reg[6]), .I1(\wb_alu_reg[0]_1 ), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[6]), .I4(mem_reg_r1_0_31_6_11_i_59_n_0), .O(insts_cnt_reg_14_sn_1)); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_6_11_i_47 (.I0(insts_cnt_reg[13]), .I1(\wb_alu_reg[0]_1 ), .I2(br_corr_cnt_reg[13]), .I3(\wb_alu_reg[0]_2 ), .I4(mem_reg_r1_0_31_6_11_i_60_n_0), .O(\insts_cnt_reg[22] )); LUT4 #( .INIT(16'hF444)) mem_reg_r1_0_31_6_11_i_57 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[14]), .I2(\wb_alu_reg[0]_2 ), .I3(br_corr_cnt_reg[14]), .O(mem_reg_r1_0_31_6_11_i_57_n_0)); LUT4 #( .INIT(16'hF444)) mem_reg_r1_0_31_6_11_i_59 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[6]), .I2(\wb_alu_reg[0]_2 ), .I3(br_corr_cnt_reg[6]), .O(mem_reg_r1_0_31_6_11_i_59_n_0)); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_6_11_i_60 (.I0(\wb_alu_reg[2]_1 ), .I1(cycle_cnt_reg[13]), .I2(\wb_alu_reg[4]_1 ), .I3(br_inst_cnt_reg[13]), .O(mem_reg_r1_0_31_6_11_i_60_n_0)); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_6_11_i_8 (.I0(\ex_wb_inst_reg[6] ), .I1(data2[6]), .I2(\f_ex_rd2_reg[0] [1]), .I3(\f_ex_rd2_reg[0] [2]), .I4(\f_ex_rd2_reg[0] [4]), .I5(Q[7]), .O(\ex_wb_inst_reg[3]_3 )); (* SOFT_HLUTNM = "soft_lutpair127" *) LUT2 #( .INIT(4'h8)) \wb_alu[16]_i_4 (.I0(douta_reg_0), .I1(ALUSel[1]), .O(\f_ex_inst_reg[12]_0 )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[19]_i_20 (.I0(Q[19]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[19]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[19]), .O(\wb_alu_reg[19]_0 )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[19]_i_21 (.I0(Q[18]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[18]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[18]), .O(\wb_alu_reg[18]_0 )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[19]_i_22 (.I0(Q[17]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[17]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[17]), .O(\wb_alu_reg[17]_0 )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[19]_i_23 (.I0(Q[16]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[16]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[16]), .O(\wb_alu_reg[16]_0 )); LUT6 #( .INIT(64'h000C000000080008)) \wb_alu[21]_i_4 (.I0(\wb_alu_reg[31]_0 [8]), .I1(\wb_alu_reg[31]_0 [4]), .I2(\wb_alu_reg[31]_0 [3]), .I3(\wb_alu_reg[31]_0 [6]), .I4(\wb_alu_reg[31]_0 [5]), .I5(\wb_alu_reg[31]_0 [2]), .O(ALUSel[0])); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[23]_i_21 (.I0(Q[21]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[21]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[21]), .O(\wb_alu_reg[21]_0 )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[23]_i_22 (.I0(Q[20]), .I1(\ex_wb_inst_reg[5] ), .I2(wb_BrEq_i_33[20]), .I3(\f_ex_inst_reg[19] ), .I4(mem_reg_3_3_i_3[20]), .O(\wb_alu_reg[20]_0 )); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT3 #( .INIT(8'h4F)) \wb_alu[29]_i_8 (.I0(\f_ex_inst_reg[12] ), .I1(\wb_alu[29]_i_2 [8]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT4 #( .INIT(16'h8000)) wb_br_taken_i_4 (.I0(\f_ex_inst_reg[2]_10 ), .I1(\wb_alu_reg[31]_0 [6]), .I2(\wb_alu_reg[31]_0 [1]), .I3(\wb_alu_reg[31]_0 [0]), .O(\f_ex_inst_reg[6] )); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT4 #( .INIT(16'h0004)) wb_br_taken_i_7 (.I0(\wb_alu_reg[31]_0 [2]), .I1(\wb_alu_reg[31]_0 [5]), .I2(\wb_alu_reg[31]_0 [3]), .I3(\wb_alu_reg[31]_0 [4]), .O(\f_ex_inst_reg[2]_10 )); endmodule module reg_file (rd10, we, rd20, \ex_wb_pc_reg[0] , \ex_wb_inst_reg[3] , \ex_wb_inst_reg[3]_0 , \ex_wb_inst_reg[3]_1 , \ex_wb_inst_reg[3]_2 , \ex_wb_inst_reg[3]_3 , \ex_wb_pc_reg[31] , \ex_wb_inst_reg[3]_4 , \ex_wb_inst_reg[3]_5 , \ex_wb_inst_reg[3]_6 , \ex_wb_inst_reg[3]_7 , \ex_wb_inst_reg[3]_8 , \ex_wb_inst_reg[3]_9 , \ex_wb_inst_reg[3]_10 , \ex_wb_inst_reg[3]_11 , \ex_wb_inst_reg[3]_12 , .insts_cnt_reg_0_sp_1(insts_cnt_reg_0_sn_1), \insts_cnt_reg[15] , \insts_cnt_reg[30] , \insts_cnt_reg[31] , .br_corr_cnt_reg_1_sp_1(br_corr_cnt_reg_1_sn_1), \wb_alu_reg[2] , \wb_alu_reg[29] , \wb_alu_reg[31] , data3, \f_ex_pc_reg[19] , \f_ex_pc_reg[23] , \f_ex_pc_reg[27] , \f_ex_pc_reg[30] , cpu_clk, D, Q, \f_ex_rd2_reg[25] , \pprev_data_reg[0] , \pc[29]_i_2 , \pprev_data_reg[31] , data2, mem_reg_r1_0_31_0_5_i_58, insts_cnt_reg, mem_reg_r1_0_31_6_11_i_36_0, cycle_cnt_reg, br_corr_cnt_reg, mem_reg_r1_0_31_0_5_i_58_0, mem_reg_r1_0_31_6_11_i_36_1, br_inst_cnt_reg, \pc_reg[31]_i_4_0 , f_ex_imm, CO, \pc_reg[31] , \pc[16]_i_2 , \pc[17]_i_2 ); output [31:0]rd10; output we; output [31:0]rd20; output \ex_wb_pc_reg[0] ; output \ex_wb_inst_reg[3] ; output \ex_wb_inst_reg[3]_0 ; output \ex_wb_inst_reg[3]_1 ; output \ex_wb_inst_reg[3]_2 ; output \ex_wb_inst_reg[3]_3 ; output [14:0]\ex_wb_pc_reg[31] ; output \ex_wb_inst_reg[3]_4 ; output \ex_wb_inst_reg[3]_5 ; output \ex_wb_inst_reg[3]_6 ; output \ex_wb_inst_reg[3]_7 ; output \ex_wb_inst_reg[3]_8 ; output \ex_wb_inst_reg[3]_9 ; output \ex_wb_inst_reg[3]_10 ; output \ex_wb_inst_reg[3]_11 ; output \ex_wb_inst_reg[3]_12 ; output \insts_cnt_reg[15] ; output \insts_cnt_reg[30] ; output \insts_cnt_reg[31] ; output \wb_alu_reg[2] ; output \wb_alu_reg[29] ; output \wb_alu_reg[31] ; output [14:0]data3; output [3:0]\f_ex_pc_reg[19] ; output [3:0]\f_ex_pc_reg[23] ; output [3:0]\f_ex_pc_reg[27] ; output [3:0]\f_ex_pc_reg[30] ; input cpu_clk; input [31:0]D; input [9:0]Q; input [9:0]\f_ex_rd2_reg[25] ; input \pprev_data_reg[0] ; input [15:0]\pc[29]_i_2 ; input [15:0]\pprev_data_reg[31] ; input [3:0]data2; input mem_reg_r1_0_31_0_5_i_58; input [4:0]insts_cnt_reg; input mem_reg_r1_0_31_6_11_i_36_0; input [3:0]cycle_cnt_reg; input [3:0]br_corr_cnt_reg; input mem_reg_r1_0_31_0_5_i_58_0; input mem_reg_r1_0_31_6_11_i_36_1; input [2:0]br_inst_cnt_reg; input [15:0]\pc_reg[31]_i_4_0 ; input [15:0]f_ex_imm; input [0:0]CO; input [14:0]\pc_reg[31] ; input [0:0]\pc[16]_i_2 ; input [0:0]\pc[17]_i_2 ; output insts_cnt_reg_0_sn_1; output br_corr_cnt_reg_1_sn_1; wire \<const0> ; wire [0:0]CO; wire [31:0]D; wire [9:0]Q; wire [3:0]br_corr_cnt_reg; wire br_corr_cnt_reg_1_sn_1; wire [2:0]br_inst_cnt_reg; wire cpu_clk; wire [3:0]cycle_cnt_reg; wire [3:0]data2; wire [14:0]data3; wire \ex_wb_inst_reg[3] ; wire \ex_wb_inst_reg[3]_0 ; wire \ex_wb_inst_reg[3]_1 ; wire \ex_wb_inst_reg[3]_10 ; wire \ex_wb_inst_reg[3]_11 ; wire \ex_wb_inst_reg[3]_12 ; wire \ex_wb_inst_reg[3]_2 ; wire \ex_wb_inst_reg[3]_3 ; wire \ex_wb_inst_reg[3]_4 ; wire \ex_wb_inst_reg[3]_5 ; wire \ex_wb_inst_reg[3]_6 ; wire \ex_wb_inst_reg[3]_7 ; wire \ex_wb_inst_reg[3]_8 ; wire \ex_wb_inst_reg[3]_9 ; wire \ex_wb_pc_reg[0] ; wire [14:0]\ex_wb_pc_reg[31] ; wire [15:0]f_ex_imm; wire [3:0]\f_ex_pc_reg[19] ; wire [3:0]\f_ex_pc_reg[23] ; wire [3:0]\f_ex_pc_reg[27] ; wire [3:0]\f_ex_pc_reg[30] ; wire [9:0]\f_ex_rd2_reg[25] ; wire [4:0]insts_cnt_reg; wire \insts_cnt_reg[15] ; wire \insts_cnt_reg[30] ; wire \insts_cnt_reg[31] ; wire insts_cnt_reg_0_sn_1; wire mem_reg_r1_0_31_0_5_i_58; wire mem_reg_r1_0_31_0_5_i_58_0; wire mem_reg_r1_0_31_12_17_i_28_n_0; wire mem_reg_r1_0_31_12_17_i_28_n_1; wire mem_reg_r1_0_31_12_17_i_28_n_2; wire mem_reg_r1_0_31_12_17_i_28_n_3; wire mem_reg_r1_0_31_18_23_i_22_n_0; wire mem_reg_r1_0_31_18_23_i_22_n_1; wire mem_reg_r1_0_31_18_23_i_22_n_2; wire mem_reg_r1_0_31_18_23_i_22_n_3; wire mem_reg_r1_0_31_24_29_i_20_n_0; wire mem_reg_r1_0_31_24_29_i_20_n_1; wire mem_reg_r1_0_31_24_29_i_20_n_2; wire mem_reg_r1_0_31_24_29_i_20_n_3; wire mem_reg_r1_0_31_24_29_i_25_n_2; wire mem_reg_r1_0_31_24_29_i_25_n_3; wire mem_reg_r1_0_31_6_11_i_36_0; wire mem_reg_r1_0_31_6_11_i_36_1; wire mem_reg_r1_0_31_6_11_i_55_n_0; wire mem_reg_r1_0_31_6_11_i_56_n_0; wire mem_reg_r1_0_31_6_11_i_58_n_0; wire [0:0]\pc[16]_i_2 ; wire [0:0]\pc[17]_i_2 ; wire \pc[19]_i_4_n_0 ; wire \pc[19]_i_5_n_0 ; wire \pc[19]_i_6_n_0 ; wire \pc[19]_i_7_n_0 ; wire \pc[23]_i_4_n_0 ; wire \pc[23]_i_5_n_0 ; wire \pc[23]_i_6_n_0 ; wire \pc[23]_i_7_n_0 ; wire \pc[27]_i_4_n_0 ; wire \pc[27]_i_5_n_0 ; wire \pc[27]_i_6_n_0 ; wire \pc[27]_i_7_n_0 ; wire [15:0]\pc[29]_i_2 ; wire \pc[31]_i_5_n_0 ; wire \pc[31]_i_6_n_0 ; wire \pc[31]_i_7_n_0 ; wire \pc[31]_i_8_n_0 ; wire \pc_reg[19]_i_3_n_0 ; wire \pc_reg[19]_i_3_n_1 ; wire \pc_reg[19]_i_3_n_2 ; wire \pc_reg[19]_i_3_n_3 ; wire \pc_reg[20]_i_2_n_0 ; wire \pc_reg[20]_i_2_n_1 ; wire \pc_reg[20]_i_2_n_2 ; wire \pc_reg[20]_i_2_n_3 ; wire \pc_reg[23]_i_3_n_0 ; wire \pc_reg[23]_i_3_n_1 ; wire \pc_reg[23]_i_3_n_2 ; wire \pc_reg[23]_i_3_n_3 ; wire \pc_reg[24]_i_2_n_0 ; wire \pc_reg[24]_i_2_n_1 ; wire \pc_reg[24]_i_2_n_2 ; wire \pc_reg[24]_i_2_n_3 ; wire \pc_reg[27]_i_3_n_0 ; wire \pc_reg[27]_i_3_n_1 ; wire \pc_reg[27]_i_3_n_2 ; wire \pc_reg[27]_i_3_n_3 ; wire \pc_reg[28]_i_2_n_0 ; wire \pc_reg[28]_i_2_n_1 ; wire \pc_reg[28]_i_2_n_2 ; wire \pc_reg[28]_i_2_n_3 ; wire [14:0]\pc_reg[31] ; wire \pc_reg[31]_i_2_n_2 ; wire \pc_reg[31]_i_2_n_3 ; wire [15:0]\pc_reg[31]_i_4_0 ; wire \pc_reg[31]_i_4_n_1 ; wire \pc_reg[31]_i_4_n_2 ; wire \pc_reg[31]_i_4_n_3 ; wire \pprev_data_reg[0] ; wire [15:0]\pprev_data_reg[31] ; wire [31:0]rd10; wire [31:0]rd20; wire \wb_alu_reg[29] ; wire \wb_alu_reg[2] ; wire \wb_alu_reg[31] ; wire we; GND GND (.G(\<const0> )); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "5" *) RAM32M mem_reg_r1_0_31_0_5 (.ADDRA(\f_ex_rd2_reg[25] [4:0]), .ADDRB(\f_ex_rd2_reg[25] [4:0]), .ADDRC(\f_ex_rd2_reg[25] [4:0]), .ADDRD(Q[9:5]), .DIA(D[1:0]), .DIB(D[3:2]), .DIC(D[5:4]), .DID({\<const0> ,\<const0> }), .DOA(rd10[1:0]), .DOB(rd10[3:2]), .DOC(rd10[5:4]), .WCLK(cpu_clk), .WE(we)); LUT4 #( .INIT(16'hFFFD)) mem_reg_r1_0_31_0_5_i_1 (.I0(Q[3]), .I1(Q[2]), .I2(Q[1]), .I3(Q[0]), .O(we)); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_0_5_i_102 (.I0(mem_reg_r1_0_31_0_5_i_58), .I1(insts_cnt_reg[0]), .I2(mem_reg_r1_0_31_6_11_i_36_0), .I3(cycle_cnt_reg[0]), .O(insts_cnt_reg_0_sn_1)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) mem_reg_r1_0_31_0_5_i_115 (.I0(\pprev_data_reg[31] [2]), .I1(\pprev_data_reg[31] [5]), .I2(\pprev_data_reg[31] [3]), .I3(\pprev_data_reg[31] [1]), .I4(\pprev_data_reg[31] [0]), .I5(\pprev_data_reg[31] [4]), .O(\wb_alu_reg[2] )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_0_5_i_15 (.I0(\pprev_data_reg[0] ), .I1(data2[0]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [1]), .O(\ex_wb_inst_reg[3] )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_0_5_i_17 (.I0(\pprev_data_reg[0] ), .I1(\pc[29]_i_2 [0]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [0]), .O(\ex_wb_pc_reg[0] )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_0_5_i_19 (.I0(\pprev_data_reg[0] ), .I1(data2[2]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [3]), .O(\ex_wb_inst_reg[3]_1 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_0_5_i_21 (.I0(\pprev_data_reg[0] ), .I1(data2[1]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [2]), .O(\ex_wb_inst_reg[3]_0 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_0_5_i_25 (.I0(\pprev_data_reg[0] ), .I1(data2[3]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [4]), .O(\ex_wb_inst_reg[3]_2 )); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT3 #( .INIT(8'hFB)) mem_reg_r1_0_31_0_5_i_56 (.I0(\pprev_data_reg[31] [15]), .I1(\pprev_data_reg[31] [12]), .I2(\pprev_data_reg[31] [14]), .O(\wb_alu_reg[31] )); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT4 #( .INIT(16'hFFEF)) mem_reg_r1_0_31_0_5_i_57 (.I0(\pprev_data_reg[31] [13]), .I1(\pprev_data_reg[31] [12]), .I2(\pprev_data_reg[31] [14]), .I3(\pprev_data_reg[31] [15]), .O(\wb_alu_reg[29] )); LUT4 #( .INIT(16'h8F88)) mem_reg_r1_0_31_0_5_i_96 (.I0(mem_reg_r1_0_31_0_5_i_58_0), .I1(br_corr_cnt_reg[0]), .I2(mem_reg_r1_0_31_0_5_i_58), .I3(insts_cnt_reg[1]), .O(br_corr_cnt_reg_1_sn_1)); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "12" *) (* ram_slice_end = "17" *) RAM32M mem_reg_r1_0_31_12_17 (.ADDRA(\f_ex_rd2_reg[25] [4:0]), .ADDRB(\f_ex_rd2_reg[25] [4:0]), .ADDRC(\f_ex_rd2_reg[25] [4:0]), .ADDRD(Q[9:5]), .DIA(D[13:12]), .DIB(D[15:14]), .DIC(D[17:16]), .DID({\<const0> ,\<const0> }), .DOA(rd10[13:12]), .DOB(rd10[15:14]), .DOC(rd10[17:16]), .WCLK(cpu_clk), .WE(we)); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_r1_0_31_12_17_i_28 (.CI(\pc[17]_i_2 ), .CO({mem_reg_r1_0_31_12_17_i_28_n_0,mem_reg_r1_0_31_12_17_i_28_n_1,mem_reg_r1_0_31_12_17_i_28_n_2,mem_reg_r1_0_31_12_17_i_28_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(\ex_wb_pc_reg[31] [3:0]), .S(\pc[29]_i_2 [4:1])); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "18" *) (* ram_slice_end = "23" *) RAM32M mem_reg_r1_0_31_18_23 (.ADDRA(\f_ex_rd2_reg[25] [4:0]), .ADDRB(\f_ex_rd2_reg[25] [4:0]), .ADDRC(\f_ex_rd2_reg[25] [4:0]), .ADDRD(Q[9:5]), .DIA(D[19:18]), .DIB(D[21:20]), .DIC(D[23:22]), .DID({\<const0> ,\<const0> }), .DOA(rd10[19:18]), .DOB(rd10[21:20]), .DOC(rd10[23:22]), .WCLK(cpu_clk), .WE(we)); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_18_23_i_16 (.I0(\pprev_data_reg[0] ), .I1(\ex_wb_pc_reg[31] [6]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [7]), .O(\ex_wb_inst_reg[3]_4 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_18_23_i_18 (.I0(\pprev_data_reg[0] ), .I1(\ex_wb_pc_reg[31] [5]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [6]), .O(\ex_wb_inst_reg[3]_3 )); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_r1_0_31_18_23_i_22 (.CI(mem_reg_r1_0_31_12_17_i_28_n_0), .CO({mem_reg_r1_0_31_18_23_i_22_n_0,mem_reg_r1_0_31_18_23_i_22_n_1,mem_reg_r1_0_31_18_23_i_22_n_2,mem_reg_r1_0_31_18_23_i_22_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(\ex_wb_pc_reg[31] [7:4]), .S(\pc[29]_i_2 [8:5])); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "24" *) (* ram_slice_end = "29" *) RAM32M mem_reg_r1_0_31_24_29 (.ADDRA(\f_ex_rd2_reg[25] [4:0]), .ADDRB(\f_ex_rd2_reg[25] [4:0]), .ADDRC(\f_ex_rd2_reg[25] [4:0]), .ADDRD(Q[9:5]), .DIA(D[25:24]), .DIB(D[27:26]), .DIC(D[29:28]), .DID({\<const0> ,\<const0> }), .DOA(rd10[25:24]), .DOB(rd10[27:26]), .DOC(rd10[29:28]), .WCLK(cpu_clk), .WE(we)); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_24_29_i_10 (.I0(\pprev_data_reg[0] ), .I1(\ex_wb_pc_reg[31] [7]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [8]), .O(\ex_wb_inst_reg[3]_5 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_24_29_i_12 (.I0(\pprev_data_reg[0] ), .I1(\ex_wb_pc_reg[31] [10]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [11]), .O(\ex_wb_inst_reg[3]_8 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_24_29_i_14 (.I0(\pprev_data_reg[0] ), .I1(\ex_wb_pc_reg[31] [9]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [10]), .O(\ex_wb_inst_reg[3]_7 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_24_29_i_16 (.I0(\pprev_data_reg[0] ), .I1(\ex_wb_pc_reg[31] [12]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [13]), .O(\ex_wb_inst_reg[3]_10 )); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_24_29_i_18 (.I0(\pprev_data_reg[0] ), .I1(\ex_wb_pc_reg[31] [11]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [12]), .O(\ex_wb_inst_reg[3]_9 )); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_r1_0_31_24_29_i_20 (.CI(mem_reg_r1_0_31_18_23_i_22_n_0), .CO({mem_reg_r1_0_31_24_29_i_20_n_0,mem_reg_r1_0_31_24_29_i_20_n_1,mem_reg_r1_0_31_24_29_i_20_n_2,mem_reg_r1_0_31_24_29_i_20_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(\ex_wb_pc_reg[31] [11:8]), .S(\pc[29]_i_2 [12:9])); (* ADDER_THRESHOLD = "35" *) CARRY4 mem_reg_r1_0_31_24_29_i_25 (.CI(mem_reg_r1_0_31_24_29_i_20_n_0), .CO({mem_reg_r1_0_31_24_29_i_25_n_2,mem_reg_r1_0_31_24_29_i_25_n_3}), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(\ex_wb_pc_reg[31] [14:12]), .S({\<const0> ,\pc[29]_i_2 [15:13]})); LUT6 #( .INIT(64'h44444F4444444444)) mem_reg_r1_0_31_24_29_i_8 (.I0(\pprev_data_reg[0] ), .I1(\ex_wb_pc_reg[31] [8]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [9]), .O(\ex_wb_inst_reg[3]_6 )); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "cpu/rf/mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "30" *) (* ram_slice_end = "31" *) RAM32X1D mem_reg_r1_0_31_30_31 (.A0(Q[5]), .A1(Q[6]), .A2(Q[7]), .A3(Q[8]), .A4(Q[9]), .D(D[30]), .DPO(rd10[30]), .DPRA0(\f_ex_rd2_reg[25] [0]), .DPRA1(\f_ex_rd2_reg[25] [1]), .DPRA2(\f_ex_rd2_reg[25] [2]), .DPRA3(\f_ex_rd2_reg[25] [3]), .DPRA4(\f_ex_rd2_reg[25] [4]), .WCLK(cpu_clk), .WE(we)); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "cpu/rf/mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "30" *) (* ram_slice_end = "31" *) RAM32X1D mem_reg_r1_0_31_30_31__0 (.A0(Q[5]), .A1(Q[6]), .A2(Q[7]), .A3(Q[8]), .A4(Q[9]), .D(D[31]), .DPO(rd10[31]), .DPRA0(\f_ex_rd2_reg[25] [0]), .DPRA1(\f_ex_rd2_reg[25] [1]), .DPRA2(\f_ex_rd2_reg[25] [2]), .DPRA3(\f_ex_rd2_reg[25] [3]), .DPRA4(\f_ex_rd2_reg[25] [4]), .WCLK(cpu_clk), .WE(we)); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "6" *) (* ram_slice_end = "11" *) RAM32M mem_reg_r1_0_31_6_11 (.ADDRA(\f_ex_rd2_reg[25] [4:0]), .ADDRB(\f_ex_rd2_reg[25] [4:0]), .ADDRC(\f_ex_rd2_reg[25] [4:0]), .ADDRD(Q[9:5]), .DIA(D[7:6]), .DIB(D[9:8]), .DIC(D[11:10]), .DID({\<const0> ,\<const0> }), .DOA(rd10[7:6]), .DOB(rd10[9:8]), .DOC(rd10[11:10]), .WCLK(cpu_clk), .WE(we)); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_6_11_i_36 (.I0(insts_cnt_reg[4]), .I1(mem_reg_r1_0_31_0_5_i_58), .I2(br_corr_cnt_reg[3]), .I3(mem_reg_r1_0_31_0_5_i_58_0), .I4(mem_reg_r1_0_31_6_11_i_55_n_0), .O(\insts_cnt_reg[31] )); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_6_11_i_38 (.I0(insts_cnt_reg[2]), .I1(mem_reg_r1_0_31_0_5_i_58), .I2(br_corr_cnt_reg[1]), .I3(mem_reg_r1_0_31_0_5_i_58_0), .I4(mem_reg_r1_0_31_6_11_i_56_n_0), .O(\insts_cnt_reg[15] )); LUT5 #( .INIT(32'h00000DDD)) mem_reg_r1_0_31_6_11_i_43 (.I0(insts_cnt_reg[3]), .I1(mem_reg_r1_0_31_0_5_i_58), .I2(br_corr_cnt_reg[2]), .I3(mem_reg_r1_0_31_0_5_i_58_0), .I4(mem_reg_r1_0_31_6_11_i_58_n_0), .O(\insts_cnt_reg[30] )); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_6_11_i_55 (.I0(mem_reg_r1_0_31_6_11_i_36_1), .I1(br_inst_cnt_reg[2]), .I2(mem_reg_r1_0_31_6_11_i_36_0), .I3(cycle_cnt_reg[3]), .O(mem_reg_r1_0_31_6_11_i_55_n_0)); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_6_11_i_56 (.I0(mem_reg_r1_0_31_6_11_i_36_0), .I1(cycle_cnt_reg[1]), .I2(mem_reg_r1_0_31_6_11_i_36_1), .I3(br_inst_cnt_reg[0]), .O(mem_reg_r1_0_31_6_11_i_56_n_0)); LUT4 #( .INIT(16'h4F44)) mem_reg_r1_0_31_6_11_i_58 (.I0(mem_reg_r1_0_31_6_11_i_36_0), .I1(cycle_cnt_reg[2]), .I2(mem_reg_r1_0_31_6_11_i_36_1), .I3(br_inst_cnt_reg[1]), .O(mem_reg_r1_0_31_6_11_i_58_n_0)); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "5" *) RAM32M mem_reg_r2_0_31_0_5 (.ADDRA(\f_ex_rd2_reg[25] [9:5]), .ADDRB(\f_ex_rd2_reg[25] [9:5]), .ADDRC(\f_ex_rd2_reg[25] [9:5]), .ADDRD(Q[9:5]), .DIA(D[1:0]), .DIB(D[3:2]), .DIC(D[5:4]), .DID({\<const0> ,\<const0> }), .DOA(rd20[1:0]), .DOB(rd20[3:2]), .DOC(rd20[5:4]), .WCLK(cpu_clk), .WE(we)); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "12" *) (* ram_slice_end = "17" *) RAM32M mem_reg_r2_0_31_12_17 (.ADDRA(\f_ex_rd2_reg[25] [9:5]), .ADDRB(\f_ex_rd2_reg[25] [9:5]), .ADDRC(\f_ex_rd2_reg[25] [9:5]), .ADDRD(Q[9:5]), .DIA(D[13:12]), .DIB(D[15:14]), .DIC(D[17:16]), .DID({\<const0> ,\<const0> }), .DOA(rd20[13:12]), .DOB(rd20[15:14]), .DOC(rd20[17:16]), .WCLK(cpu_clk), .WE(we)); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "18" *) (* ram_slice_end = "23" *) RAM32M mem_reg_r2_0_31_18_23 (.ADDRA(\f_ex_rd2_reg[25] [9:5]), .ADDRB(\f_ex_rd2_reg[25] [9:5]), .ADDRC(\f_ex_rd2_reg[25] [9:5]), .ADDRD(Q[9:5]), .DIA(D[19:18]), .DIB(D[21:20]), .DIC(D[23:22]), .DID({\<const0> ,\<const0> }), .DOA(rd20[19:18]), .DOB(rd20[21:20]), .DOC(rd20[23:22]), .WCLK(cpu_clk), .WE(we)); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "24" *) (* ram_slice_end = "29" *) RAM32M mem_reg_r2_0_31_24_29 (.ADDRA(\f_ex_rd2_reg[25] [9:5]), .ADDRB(\f_ex_rd2_reg[25] [9:5]), .ADDRC(\f_ex_rd2_reg[25] [9:5]), .ADDRD(Q[9:5]), .DIA(D[25:24]), .DIB(D[27:26]), .DIC(D[29:28]), .DID({\<const0> ,\<const0> }), .DOA(rd20[25:24]), .DOB(rd20[27:26]), .DOC(rd20[29:28]), .WCLK(cpu_clk), .WE(we)); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "cpu/rf/mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "30" *) (* ram_slice_end = "31" *) RAM32X1D mem_reg_r2_0_31_30_31 (.A0(Q[5]), .A1(Q[6]), .A2(Q[7]), .A3(Q[8]), .A4(Q[9]), .D(D[30]), .DPO(rd20[30]), .DPRA0(\f_ex_rd2_reg[25] [5]), .DPRA1(\f_ex_rd2_reg[25] [6]), .DPRA2(\f_ex_rd2_reg[25] [7]), .DPRA3(\f_ex_rd2_reg[25] [8]), .DPRA4(\f_ex_rd2_reg[25] [9]), .WCLK(cpu_clk), .WE(we)); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "cpu/rf/mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "30" *) (* ram_slice_end = "31" *) RAM32X1D mem_reg_r2_0_31_30_31__0 (.A0(Q[5]), .A1(Q[6]), .A2(Q[7]), .A3(Q[8]), .A4(Q[9]), .D(D[31]), .DPO(rd20[31]), .DPRA0(\f_ex_rd2_reg[25] [5]), .DPRA1(\f_ex_rd2_reg[25] [6]), .DPRA2(\f_ex_rd2_reg[25] [7]), .DPRA3(\f_ex_rd2_reg[25] [8]), .DPRA4(\f_ex_rd2_reg[25] [9]), .WCLK(cpu_clk), .WE(we)); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "31" *) (* ram_offset = "0" *) (* ram_slice_begin = "6" *) (* ram_slice_end = "11" *) RAM32M mem_reg_r2_0_31_6_11 (.ADDRA(\f_ex_rd2_reg[25] [9:5]), .ADDRB(\f_ex_rd2_reg[25] [9:5]), .ADDRC(\f_ex_rd2_reg[25] [9:5]), .ADDRD(Q[9:5]), .DIA(D[7:6]), .DIB(D[9:8]), .DIC(D[11:10]), .DID({\<const0> ,\<const0> }), .DOA(rd20[7:6]), .DOB(rd20[9:8]), .DOC(rd20[11:10]), .WCLK(cpu_clk), .WE(we)); LUT2 #( .INIT(4'h6)) \pc[19]_i_4 (.I0(\pc_reg[31]_i_4_0 [3]), .I1(f_ex_imm[3]), .O(\pc[19]_i_4_n_0 )); LUT2 #( .INIT(4'h6)) \pc[19]_i_5 (.I0(\pc_reg[31]_i_4_0 [2]), .I1(f_ex_imm[2]), .O(\pc[19]_i_5_n_0 )); LUT2 #( .INIT(4'h6)) \pc[19]_i_6 (.I0(\pc_reg[31]_i_4_0 [1]), .I1(f_ex_imm[1]), .O(\pc[19]_i_6_n_0 )); LUT2 #( .INIT(4'h6)) \pc[19]_i_7 (.I0(\pc_reg[31]_i_4_0 [0]), .I1(f_ex_imm[0]), .O(\pc[19]_i_7_n_0 )); LUT2 #( .INIT(4'h6)) \pc[23]_i_4 (.I0(\pc_reg[31]_i_4_0 [7]), .I1(f_ex_imm[7]), .O(\pc[23]_i_4_n_0 )); LUT2 #( .INIT(4'h6)) \pc[23]_i_5 (.I0(\pc_reg[31]_i_4_0 [6]), .I1(f_ex_imm[6]), .O(\pc[23]_i_5_n_0 )); LUT2 #( .INIT(4'h6)) \pc[23]_i_6 (.I0(\pc_reg[31]_i_4_0 [5]), .I1(f_ex_imm[5]), .O(\pc[23]_i_6_n_0 )); LUT2 #( .INIT(4'h6)) \pc[23]_i_7 (.I0(\pc_reg[31]_i_4_0 [4]), .I1(f_ex_imm[4]), .O(\pc[23]_i_7_n_0 )); LUT2 #( .INIT(4'h6)) \pc[27]_i_4 (.I0(\pc_reg[31]_i_4_0 [11]), .I1(f_ex_imm[11]), .O(\pc[27]_i_4_n_0 )); LUT2 #( .INIT(4'h6)) \pc[27]_i_5 (.I0(\pc_reg[31]_i_4_0 [10]), .I1(f_ex_imm[10]), .O(\pc[27]_i_5_n_0 )); LUT2 #( .INIT(4'h6)) \pc[27]_i_6 (.I0(\pc_reg[31]_i_4_0 [9]), .I1(f_ex_imm[9]), .O(\pc[27]_i_6_n_0 )); LUT2 #( .INIT(4'h6)) \pc[27]_i_7 (.I0(\pc_reg[31]_i_4_0 [8]), .I1(f_ex_imm[8]), .O(\pc[27]_i_7_n_0 )); LUT2 #( .INIT(4'h6)) \pc[31]_i_5 (.I0(\pc_reg[31]_i_4_0 [15]), .I1(f_ex_imm[15]), .O(\pc[31]_i_5_n_0 )); LUT2 #( .INIT(4'h6)) \pc[31]_i_6 (.I0(\pc_reg[31]_i_4_0 [14]), .I1(f_ex_imm[14]), .O(\pc[31]_i_6_n_0 )); LUT2 #( .INIT(4'h6)) \pc[31]_i_7 (.I0(\pc_reg[31]_i_4_0 [13]), .I1(f_ex_imm[13]), .O(\pc[31]_i_7_n_0 )); LUT2 #( .INIT(4'h6)) \pc[31]_i_8 (.I0(\pc_reg[31]_i_4_0 [12]), .I1(f_ex_imm[12]), .O(\pc[31]_i_8_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY4 \pc_reg[19]_i_3 (.CI(\pc[16]_i_2 ), .CO({\pc_reg[19]_i_3_n_0 ,\pc_reg[19]_i_3_n_1 ,\pc_reg[19]_i_3_n_2 ,\pc_reg[19]_i_3_n_3 }), .CYINIT(\<const0> ), .DI(\pc_reg[31]_i_4_0 [3:0]), .O(\f_ex_pc_reg[19] ), .S({\pc[19]_i_4_n_0 ,\pc[19]_i_5_n_0 ,\pc[19]_i_6_n_0 ,\pc[19]_i_7_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY4 \pc_reg[20]_i_2 (.CI(CO), .CO({\pc_reg[20]_i_2_n_0 ,\pc_reg[20]_i_2_n_1 ,\pc_reg[20]_i_2_n_2 ,\pc_reg[20]_i_2_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(data3[3:0]), .S(\pc_reg[31] [3:0])); (* ADDER_THRESHOLD = "35" *) CARRY4 \pc_reg[23]_i_3 (.CI(\pc_reg[19]_i_3_n_0 ), .CO({\pc_reg[23]_i_3_n_0 ,\pc_reg[23]_i_3_n_1 ,\pc_reg[23]_i_3_n_2 ,\pc_reg[23]_i_3_n_3 }), .CYINIT(\<const0> ), .DI(\pc_reg[31]_i_4_0 [7:4]), .O(\f_ex_pc_reg[23] ), .S({\pc[23]_i_4_n_0 ,\pc[23]_i_5_n_0 ,\pc[23]_i_6_n_0 ,\pc[23]_i_7_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY4 \pc_reg[24]_i_2 (.CI(\pc_reg[20]_i_2_n_0 ), .CO({\pc_reg[24]_i_2_n_0 ,\pc_reg[24]_i_2_n_1 ,\pc_reg[24]_i_2_n_2 ,\pc_reg[24]_i_2_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(data3[7:4]), .S(\pc_reg[31] [7:4])); (* ADDER_THRESHOLD = "35" *) CARRY4 \pc_reg[27]_i_3 (.CI(\pc_reg[23]_i_3_n_0 ), .CO({\pc_reg[27]_i_3_n_0 ,\pc_reg[27]_i_3_n_1 ,\pc_reg[27]_i_3_n_2 ,\pc_reg[27]_i_3_n_3 }), .CYINIT(\<const0> ), .DI(\pc_reg[31]_i_4_0 [11:8]), .O(\f_ex_pc_reg[27] ), .S({\pc[27]_i_4_n_0 ,\pc[27]_i_5_n_0 ,\pc[27]_i_6_n_0 ,\pc[27]_i_7_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY4 \pc_reg[28]_i_2 (.CI(\pc_reg[24]_i_2_n_0 ), .CO({\pc_reg[28]_i_2_n_0 ,\pc_reg[28]_i_2_n_1 ,\pc_reg[28]_i_2_n_2 ,\pc_reg[28]_i_2_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(data3[11:8]), .S(\pc_reg[31] [11:8])); (* ADDER_THRESHOLD = "35" *) CARRY4 \pc_reg[31]_i_2 (.CI(\pc_reg[28]_i_2_n_0 ), .CO({\pc_reg[31]_i_2_n_2 ,\pc_reg[31]_i_2_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }), .O(data3[14:12]), .S({\<const0> ,\pc_reg[31] [14:12]})); (* ADDER_THRESHOLD = "35" *) CARRY4 \pc_reg[31]_i_4 (.CI(\pc_reg[27]_i_3_n_0 ), .CO({\pc_reg[31]_i_4_n_1 ,\pc_reg[31]_i_4_n_2 ,\pc_reg[31]_i_4_n_3 }), .CYINIT(\<const0> ), .DI({\<const0> ,\pc_reg[31]_i_4_0 [14:12]}), .O(\f_ex_pc_reg[30] ), .S({\pc[31]_i_5_n_0 ,\pc[31]_i_6_n_0 ,\pc[31]_i_7_n_0 ,\pc[31]_i_8_n_0 })); LUT6 #( .INIT(64'h44444F4444444444)) \pprev_data[30]_i_3 (.I0(\pprev_data_reg[0] ), .I1(\ex_wb_pc_reg[31] [13]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [14]), .O(\ex_wb_inst_reg[3]_11 )); LUT6 #( .INIT(64'h44444F4444444444)) \pprev_data[31]_i_3 (.I0(\pprev_data_reg[0] ), .I1(\ex_wb_pc_reg[31] [14]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\pprev_data_reg[31] [15]), .O(\ex_wb_inst_reg[3]_12 )); endmodule (* ORIG_REF_NAME = "synchronizer" *) module synchronizer__parameterized0 (SR, BUTTONS_IBUF, cpu_clk); output [0:0]SR; input [0:0]BUTTONS_IBUF; input cpu_clk; wire \<const0> ; wire \<const1> ; wire [0:0]BUTTONS_IBUF; wire [0:0]SR; wire cpu_clk; wire [0:0]ff1; wire [0:0]synchronized_signals; GND GND (.G(\<const0> )); VCC VCC (.P(\<const1> )); FDRE #( .INIT(1'b0)) \ff1_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(BUTTONS_IBUF), .Q(ff1), .R(\<const0> )); FDRE #( .INIT(1'b0)) \ff2_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(ff1), .Q(synchronized_signals), .R(\<const0> )); LUT1 #( .INIT(2'h1)) \saturating_counter[0][9]_i_1 (.I0(synchronized_signals), .O(SR)); endmodule module uart (\tx_shift_reg[8] , serial_out, \f_ex_inst_reg[2] , \f_ex_inst_reg[2]_0 , \f_ex_inst_reg[2]_1 , \f_ex_inst_reg[2]_2 , \f_ex_inst_reg[2]_3 , \f_ex_inst_reg[2]_4 , symbol_edge__7, tx_running__2, \f_ex_inst_reg[12] , \wb_alu_reg[22] , \wb_alu_reg[23] , \wb_alu_reg[24] , \wb_alu_reg[25] , \wb_alu_reg[26] , \wb_alu_reg[27] , \wb_alu_reg[28] , \wb_alu_reg[29] , \wb_alu_reg[30] , \wb_alu_reg[31] , \f_ex_inst_reg[14] , \f_ex_inst_reg[14]_0 , \f_ex_inst_reg[12]_0 , \f_ex_inst_reg[12]_1 , \f_ex_inst_reg[12]_2 , \f_ex_inst_reg[12]_3 , \f_ex_inst_reg[13] , mem_wb_mux, .br_inst_cnt_reg_0_sp_1(br_inst_cnt_reg_0_sn_1), \rx_shift_reg[2] , .insts_cnt_reg_2_sp_1(insts_cnt_reg_2_sn_1), .insts_cnt_reg_3_sp_1(insts_cnt_reg_3_sn_1), .insts_cnt_reg_4_sp_1(insts_cnt_reg_4_sn_1), .insts_cnt_reg_5_sp_1(insts_cnt_reg_5_sn_1), \insts_cnt_reg[6] , \br_corr_cnt_reg[7] , \insts_cnt_reg[7] , .br_inst_cnt_reg_2_sp_1(br_inst_cnt_reg_2_sn_1), .br_inst_cnt_reg_3_sp_1(br_inst_cnt_reg_3_sn_1), .br_inst_cnt_reg_4_sp_1(br_inst_cnt_reg_4_sn_1), cpu_reset, serial_in, cpu_clk, \tx_shift_reg[0] , \tx_shift_reg[7] , \tx_shift_reg[8]_0 , \bit_counter[3]_i_33 , \bit_counter[3]_i_33_0 , ALUSel, start, buttons_pressed, cpu_clk_locked, has_byte_reg, Q, wb_BrLt_i_14, wb_BrEq_i_35, wb_BrLt_i_14_0, wb_BrEq_i_35_0, wb_BrLt_i_14_1, \bit_counter[3]_i_21 , mem_reg_r1_0_31_0_5_i_14, dout, mem_reg_r1_0_31_0_5_i_14_0, mem_reg_r1_0_31_12_17_i_14, mem_reg_r1_0_31_0_5_i_14_1, mem_reg_0_0_i_321, mem_reg_r1_0_31_0_5_i_58, br_inst_cnt_reg, mem_reg_0_0_i_316, mem_reg_r1_0_31_6_11_i_7, br_corr_cnt_reg, mem_reg_r1_0_31_0_5_i_58_0, mem_reg_0_0_i_316_0, mem_reg_0_0_i_316_1, cycle_cnt_reg, has_byte_reg_0, has_byte_reg_1, has_byte_reg_2, insts_cnt_reg, mem_reg_r1_0_31_0_5_i_20, SR); output [6:0]\tx_shift_reg[8] ; output serial_out; output \f_ex_inst_reg[2] ; output \f_ex_inst_reg[2]_0 ; output \f_ex_inst_reg[2]_1 ; output \f_ex_inst_reg[2]_2 ; output \f_ex_inst_reg[2]_3 ; output \f_ex_inst_reg[2]_4 ; output symbol_edge__7; output tx_running__2; output [0:0]\f_ex_inst_reg[12] ; output \wb_alu_reg[22] ; output \wb_alu_reg[23] ; output \wb_alu_reg[24] ; output \wb_alu_reg[25] ; output \wb_alu_reg[26] ; output \wb_alu_reg[27] ; output \wb_alu_reg[28] ; output \wb_alu_reg[29] ; output \wb_alu_reg[30] ; output \wb_alu_reg[31] ; output \f_ex_inst_reg[14] ; output \f_ex_inst_reg[14]_0 ; output \f_ex_inst_reg[12]_0 ; output \f_ex_inst_reg[12]_1 ; output \f_ex_inst_reg[12]_2 ; output \f_ex_inst_reg[12]_3 ; output \f_ex_inst_reg[13] ; output [2:0]mem_wb_mux; output \rx_shift_reg[2] ; output \insts_cnt_reg[6] ; output \br_corr_cnt_reg[7] ; output \insts_cnt_reg[7] ; input cpu_reset; input serial_in; input cpu_clk; input \tx_shift_reg[0] ; input [6:0]\tx_shift_reg[7] ; input \tx_shift_reg[8]_0 ; input \bit_counter[3]_i_33 ; input [4:0]\bit_counter[3]_i_33_0 ; input [2:0]ALUSel; input start; input buttons_pressed; input cpu_clk_locked; input has_byte_reg; input [5:0]Q; input [15:0]wb_BrLt_i_14; input wb_BrEq_i_35; input [9:0]wb_BrLt_i_14_0; input wb_BrEq_i_35_0; input [9:0]wb_BrLt_i_14_1; input [5:0]\bit_counter[3]_i_21 ; input mem_reg_r1_0_31_0_5_i_14; input [2:0]dout; input mem_reg_r1_0_31_0_5_i_14_0; input [2:0]mem_reg_r1_0_31_12_17_i_14; input mem_reg_r1_0_31_0_5_i_14_1; input mem_reg_0_0_i_321; input mem_reg_r1_0_31_0_5_i_58; input [7:0]br_inst_cnt_reg; input mem_reg_0_0_i_316; input mem_reg_r1_0_31_6_11_i_7; input [6:0]br_corr_cnt_reg; input mem_reg_r1_0_31_0_5_i_58_0; input mem_reg_0_0_i_316_0; input mem_reg_0_0_i_316_1; input [6:0]cycle_cnt_reg; input [4:0]has_byte_reg_0; input has_byte_reg_1; input has_byte_reg_2; input [5:0]insts_cnt_reg; input mem_reg_r1_0_31_0_5_i_20; input [0:0]SR; output br_inst_cnt_reg_0_sn_1; output insts_cnt_reg_2_sn_1; output insts_cnt_reg_3_sn_1; output insts_cnt_reg_4_sn_1; output insts_cnt_reg_5_sn_1; output br_inst_cnt_reg_2_sn_1; output br_inst_cnt_reg_3_sn_1; output br_inst_cnt_reg_4_sn_1; wire \<const1> ; wire [2:0]ALUSel; wire [5:0]Q; wire [0:0]SR; wire [5:0]\bit_counter[3]_i_21 ; wire \bit_counter[3]_i_33 ; wire [4:0]\bit_counter[3]_i_33_0 ; wire [6:0]br_corr_cnt_reg; wire \br_corr_cnt_reg[7] ; wire [7:0]br_inst_cnt_reg; wire br_inst_cnt_reg_0_sn_1; wire br_inst_cnt_reg_2_sn_1; wire br_inst_cnt_reg_3_sn_1; wire br_inst_cnt_reg_4_sn_1; wire buttons_pressed; wire cpu_clk; wire cpu_clk_locked; wire cpu_reset; wire [6:0]cycle_cnt_reg; wire [2:0]dout; wire [0:0]\f_ex_inst_reg[12] ; wire \f_ex_inst_reg[12]_0 ; wire \f_ex_inst_reg[12]_1 ; wire \f_ex_inst_reg[12]_2 ; wire \f_ex_inst_reg[12]_3 ; wire \f_ex_inst_reg[13] ; wire \f_ex_inst_reg[14] ; wire \f_ex_inst_reg[14]_0 ; wire \f_ex_inst_reg[2] ; wire \f_ex_inst_reg[2]_0 ; wire \f_ex_inst_reg[2]_1 ; wire \f_ex_inst_reg[2]_2 ; wire \f_ex_inst_reg[2]_3 ; wire \f_ex_inst_reg[2]_4 ; wire has_byte_reg; wire [4:0]has_byte_reg_0; wire has_byte_reg_1; wire has_byte_reg_2; wire [5:0]insts_cnt_reg; wire \insts_cnt_reg[6] ; wire \insts_cnt_reg[7] ; wire insts_cnt_reg_2_sn_1; wire insts_cnt_reg_3_sn_1; wire insts_cnt_reg_4_sn_1; wire insts_cnt_reg_5_sn_1; wire mem_reg_0_0_i_316; wire mem_reg_0_0_i_316_0; wire mem_reg_0_0_i_316_1; wire mem_reg_0_0_i_321; wire mem_reg_r1_0_31_0_5_i_14; wire mem_reg_r1_0_31_0_5_i_14_0; wire mem_reg_r1_0_31_0_5_i_14_1; wire mem_reg_r1_0_31_0_5_i_20; wire mem_reg_r1_0_31_0_5_i_58; wire mem_reg_r1_0_31_0_5_i_58_0; wire [2:0]mem_reg_r1_0_31_12_17_i_14; wire mem_reg_r1_0_31_6_11_i_7; wire [2:0]mem_wb_mux; wire \rx_shift_reg[2] ; wire serial_in; wire serial_in_reg; wire serial_out; wire start; wire symbol_edge__7; wire tx_running__2; wire [0:0]tx_shift; wire \tx_shift_reg[0] ; wire [6:0]\tx_shift_reg[7] ; wire [6:0]\tx_shift_reg[8] ; wire \tx_shift_reg[8]_0 ; wire [0:0]uart_rx_data_out; wire wb_BrEq_i_35; wire wb_BrEq_i_35_0; wire [15:0]wb_BrLt_i_14; wire [9:0]wb_BrLt_i_14_0; wire [9:0]wb_BrLt_i_14_1; wire \wb_alu_reg[22] ; wire \wb_alu_reg[23] ; wire \wb_alu_reg[24] ; wire \wb_alu_reg[25] ; wire \wb_alu_reg[26] ; wire \wb_alu_reg[27] ; wire \wb_alu_reg[28] ; wire \wb_alu_reg[29] ; wire \wb_alu_reg[30] ; wire \wb_alu_reg[31] ; VCC VCC (.P(\<const1> )); FDSE serial_in_reg_reg (.C(cpu_clk), .CE(\<const1> ), .D(serial_in), .Q(serial_in_reg), .S(cpu_reset)); FDSE serial_out_reg_reg (.C(cpu_clk), .CE(\<const1> ), .D(tx_shift), .Q(serial_out), .S(cpu_reset)); uart_receiver uareceive (.Q(uart_rx_data_out), .br_corr_cnt_reg(br_corr_cnt_reg[6:1]), .\br_corr_cnt_reg[7] (\br_corr_cnt_reg[7] ), .br_inst_cnt_reg(br_inst_cnt_reg[7:1]), .br_inst_cnt_reg_2_sp_1(br_inst_cnt_reg_2_sn_1), .br_inst_cnt_reg_3_sp_1(br_inst_cnt_reg_3_sn_1), .br_inst_cnt_reg_4_sp_1(br_inst_cnt_reg_4_sn_1), .buttons_pressed(buttons_pressed), .cpu_clk(cpu_clk), .cpu_clk_locked(cpu_clk_locked), .cpu_reset(cpu_reset), .cycle_cnt_reg(cycle_cnt_reg), .dout(dout[2:1]), .has_byte_reg_0(has_byte_reg), .has_byte_reg_1(has_byte_reg_0), .has_byte_reg_2(has_byte_reg_1), .has_byte_reg_3(has_byte_reg_2), .has_byte_reg_4(wb_BrLt_i_14[7:0]), .insts_cnt_reg(insts_cnt_reg), .\insts_cnt_reg[6] (\insts_cnt_reg[6] ), .\insts_cnt_reg[7] (\insts_cnt_reg[7] ), .insts_cnt_reg_2_sp_1(insts_cnt_reg_2_sn_1), .insts_cnt_reg_3_sp_1(insts_cnt_reg_3_sn_1), .insts_cnt_reg_4_sp_1(insts_cnt_reg_4_sn_1), .insts_cnt_reg_5_sp_1(insts_cnt_reg_5_sn_1), .mem_reg_0_0_i_316(mem_reg_0_0_i_316_0), .mem_reg_0_0_i_316_0(mem_reg_0_0_i_316), .mem_reg_0_0_i_316_1(mem_reg_0_0_i_316_1), .mem_reg_r1_0_31_0_5_i_14(mem_reg_r1_0_31_0_5_i_14), .mem_reg_r1_0_31_0_5_i_14_0(mem_reg_r1_0_31_0_5_i_14_0), .mem_reg_r1_0_31_0_5_i_14_1(mem_reg_r1_0_31_0_5_i_14_1), .mem_reg_r1_0_31_0_5_i_20(mem_reg_r1_0_31_0_5_i_20), .mem_reg_r1_0_31_0_5_i_58_0(mem_reg_r1_0_31_0_5_i_58), .mem_reg_r1_0_31_0_5_i_58_1(mem_reg_r1_0_31_0_5_i_58_0), .mem_reg_r1_0_31_12_17_i_14(mem_reg_r1_0_31_12_17_i_14[2:1]), .mem_reg_r1_0_31_6_11_i_7(mem_reg_r1_0_31_6_11_i_7), .mem_wb_mux(mem_wb_mux[2:1]), .\rx_shift_reg[2]_0 (\rx_shift_reg[2] ), .serial_in_reg(serial_in_reg)); uart_transmitter uatransmit (.ALUSel(ALUSel), .Q(Q), .SR(SR), .\bit_counter[3]_i_21 (\bit_counter[3]_i_21 ), .\bit_counter[3]_i_33 (\bit_counter[3]_i_33 ), .\bit_counter[3]_i_33_0 (\bit_counter[3]_i_33_0 ), .br_corr_cnt_reg(br_corr_cnt_reg[0]), .br_inst_cnt_reg(br_inst_cnt_reg[0]), .br_inst_cnt_reg_0_sp_1(br_inst_cnt_reg_0_sn_1), .buttons_pressed(buttons_pressed), .cpu_clk(cpu_clk), .cpu_clk_locked(cpu_clk_locked), .cpu_reset(cpu_reset), .dout(dout[0]), .\f_ex_inst_reg[12] (\f_ex_inst_reg[12] ), .\f_ex_inst_reg[12]_0 (\f_ex_inst_reg[12]_0 ), .\f_ex_inst_reg[12]_1 (\f_ex_inst_reg[12]_1 ), .\f_ex_inst_reg[12]_2 (\f_ex_inst_reg[12]_2 ), .\f_ex_inst_reg[12]_3 (\f_ex_inst_reg[12]_3 ), .\f_ex_inst_reg[13] (\f_ex_inst_reg[13] ), .\f_ex_inst_reg[14] (\f_ex_inst_reg[14] ), .\f_ex_inst_reg[14]_0 (\f_ex_inst_reg[14]_0 ), .\f_ex_inst_reg[2] (\f_ex_inst_reg[2] ), .\f_ex_inst_reg[2]_0 (\f_ex_inst_reg[2]_0 ), .\f_ex_inst_reg[2]_1 (\f_ex_inst_reg[2]_1 ), .\f_ex_inst_reg[2]_2 (\f_ex_inst_reg[2]_2 ), .\f_ex_inst_reg[2]_3 (\f_ex_inst_reg[2]_3 ), .\f_ex_inst_reg[2]_4 (\f_ex_inst_reg[2]_4 ), .mem_reg_0_0_i_321(mem_reg_0_0_i_321), .mem_reg_0_0_i_321_0(mem_reg_r1_0_31_0_5_i_58), .mem_reg_0_0_i_321_1(mem_reg_0_0_i_316), .mem_reg_0_0_i_321_2(uart_rx_data_out), .mem_reg_r1_0_31_0_5_i_16(mem_reg_r1_0_31_0_5_i_14), .mem_reg_r1_0_31_0_5_i_16_0(mem_reg_r1_0_31_0_5_i_14_0), .mem_reg_r1_0_31_0_5_i_16_1(mem_reg_r1_0_31_12_17_i_14[0]), .mem_reg_r1_0_31_0_5_i_16_2(mem_reg_r1_0_31_0_5_i_14_1), .mem_reg_r1_0_31_0_5_i_64_0(mem_reg_r1_0_31_6_11_i_7), .mem_reg_r1_0_31_0_5_i_64_1(mem_reg_r1_0_31_0_5_i_58_0), .mem_wb_mux(mem_wb_mux[0]), .start(start), .symbol_edge__7(symbol_edge__7), .tx_running__2(tx_running__2), .\tx_shift_reg[0]_0 (tx_shift), .\tx_shift_reg[0]_1 (\tx_shift_reg[0] ), .\tx_shift_reg[7]_0 (\tx_shift_reg[7] ), .\tx_shift_reg[8]_0 (\tx_shift_reg[8] ), .\tx_shift_reg[8]_1 (\tx_shift_reg[8]_0 ), .wb_BrEq_i_35(wb_BrEq_i_35), .wb_BrEq_i_35_0(wb_BrEq_i_35_0), .wb_BrLt_i_14(wb_BrLt_i_14[15:6]), .wb_BrLt_i_14_0(wb_BrLt_i_14_0), .wb_BrLt_i_14_1(wb_BrLt_i_14_1), .\wb_alu_reg[22] (\wb_alu_reg[22] ), .\wb_alu_reg[23] (\wb_alu_reg[23] ), .\wb_alu_reg[24] (\wb_alu_reg[24] ), .\wb_alu_reg[25] (\wb_alu_reg[25] ), .\wb_alu_reg[26] (\wb_alu_reg[26] ), .\wb_alu_reg[27] (\wb_alu_reg[27] ), .\wb_alu_reg[28] (\wb_alu_reg[28] ), .\wb_alu_reg[29] (\wb_alu_reg[29] ), .\wb_alu_reg[30] (\wb_alu_reg[30] ), .\wb_alu_reg[31] (\wb_alu_reg[31] )); endmodule module uart_receiver (mem_wb_mux, \rx_shift_reg[2]_0 , Q, .insts_cnt_reg_2_sp_1(insts_cnt_reg_2_sn_1), .insts_cnt_reg_3_sp_1(insts_cnt_reg_3_sn_1), .insts_cnt_reg_4_sp_1(insts_cnt_reg_4_sn_1), .insts_cnt_reg_5_sp_1(insts_cnt_reg_5_sn_1), \insts_cnt_reg[6] , \br_corr_cnt_reg[7] , \insts_cnt_reg[7] , .br_inst_cnt_reg_2_sp_1(br_inst_cnt_reg_2_sn_1), .br_inst_cnt_reg_3_sp_1(br_inst_cnt_reg_3_sn_1), .br_inst_cnt_reg_4_sp_1(br_inst_cnt_reg_4_sn_1), cpu_reset, cpu_clk, buttons_pressed, cpu_clk_locked, serial_in_reg, has_byte_reg_0, mem_reg_r1_0_31_0_5_i_14, dout, mem_reg_r1_0_31_0_5_i_14_0, mem_reg_r1_0_31_12_17_i_14, mem_reg_r1_0_31_0_5_i_14_1, mem_reg_0_0_i_316, mem_reg_0_0_i_316_0, mem_reg_0_0_i_316_1, cycle_cnt_reg, br_inst_cnt_reg, mem_reg_r1_0_31_0_5_i_58_0, mem_reg_r1_0_31_0_5_i_58_1, has_byte_reg_1, has_byte_reg_2, has_byte_reg_3, has_byte_reg_4, insts_cnt_reg, mem_reg_r1_0_31_0_5_i_20, mem_reg_r1_0_31_6_11_i_7, br_corr_cnt_reg); output [1:0]mem_wb_mux; output \rx_shift_reg[2]_0 ; output [0:0]Q; output \insts_cnt_reg[6] ; output \br_corr_cnt_reg[7] ; output \insts_cnt_reg[7] ; input cpu_reset; input cpu_clk; input buttons_pressed; input cpu_clk_locked; input serial_in_reg; input has_byte_reg_0; input mem_reg_r1_0_31_0_5_i_14; input [1:0]dout; input mem_reg_r1_0_31_0_5_i_14_0; input [1:0]mem_reg_r1_0_31_12_17_i_14; input mem_reg_r1_0_31_0_5_i_14_1; input mem_reg_0_0_i_316; input mem_reg_0_0_i_316_0; input mem_reg_0_0_i_316_1; input [6:0]cycle_cnt_reg; input [6:0]br_inst_cnt_reg; input mem_reg_r1_0_31_0_5_i_58_0; input mem_reg_r1_0_31_0_5_i_58_1; input [4:0]has_byte_reg_1; input has_byte_reg_2; input has_byte_reg_3; input [7:0]has_byte_reg_4; input [5:0]insts_cnt_reg; input mem_reg_r1_0_31_0_5_i_20; input mem_reg_r1_0_31_6_11_i_7; input [5:0]br_corr_cnt_reg; output insts_cnt_reg_2_sn_1; output insts_cnt_reg_3_sn_1; output insts_cnt_reg_4_sn_1; output insts_cnt_reg_5_sn_1; output br_inst_cnt_reg_2_sn_1; output br_inst_cnt_reg_3_sn_1; output br_inst_cnt_reg_4_sn_1; wire \<const0> ; wire \<const1> ; wire [0:0]Q; wire [3:0]bit_counter; wire bit_counter0; wire \bit_counter[0]_i_1_n_0 ; wire \bit_counter[1]_i_1_n_0 ; wire \bit_counter[2]_i_1_n_0 ; wire \bit_counter[3]_i_1_n_0 ; wire [5:0]br_corr_cnt_reg; wire \br_corr_cnt_reg[7] ; wire [6:0]br_inst_cnt_reg; wire br_inst_cnt_reg_2_sn_1; wire br_inst_cnt_reg_3_sn_1; wire br_inst_cnt_reg_4_sn_1; wire buttons_pressed; wire \clock_counter[8]_i_1__0_n_0 ; wire \clock_counter[8]_i_4_n_0 ; wire \clock_counter[8]_i_5_n_0 ; wire [8:0]clock_counter_reg; wire cpu_clk; wire cpu_clk_locked; wire cpu_reset; wire [6:0]cycle_cnt_reg; wire [1:0]dout; wire has_byte; wire has_byte0; wire has_byte_i_1_n_0; wire has_byte_i_3_n_0; wire has_byte_i_4_n_0; wire has_byte_i_6_n_0; wire has_byte_reg_0; wire [4:0]has_byte_reg_1; wire has_byte_reg_2; wire has_byte_reg_3; wire [7:0]has_byte_reg_4; wire [5:0]insts_cnt_reg; wire \insts_cnt_reg[6] ; wire \insts_cnt_reg[7] ; wire insts_cnt_reg_2_sn_1; wire insts_cnt_reg_3_sn_1; wire insts_cnt_reg_4_sn_1; wire insts_cnt_reg_5_sn_1; wire mem_reg_0_0_i_316; wire mem_reg_0_0_i_316_0; wire mem_reg_0_0_i_316_1; wire mem_reg_r1_0_31_0_5_i_14; wire mem_reg_r1_0_31_0_5_i_14_0; wire mem_reg_r1_0_31_0_5_i_14_1; wire mem_reg_r1_0_31_0_5_i_20; wire mem_reg_r1_0_31_0_5_i_58_0; wire mem_reg_r1_0_31_0_5_i_58_1; wire mem_reg_r1_0_31_0_5_i_70_n_0; wire mem_reg_r1_0_31_0_5_i_78_n_0; wire mem_reg_r1_0_31_0_5_i_84_n_0; wire mem_reg_r1_0_31_0_5_i_90_n_0; wire mem_reg_r1_0_31_0_5_i_95_n_0; wire [1:0]mem_reg_r1_0_31_12_17_i_14; wire mem_reg_r1_0_31_6_11_i_41_n_0; wire mem_reg_r1_0_31_6_11_i_48_n_0; wire mem_reg_r1_0_31_6_11_i_7; wire [1:0]mem_wb_mux; wire [8:0]p_0_in__0; wire rx_running__2; wire [9:9]rx_shift; wire rx_shift0; wire \rx_shift[9]_i_2_n_0 ; wire \rx_shift_reg[2]_0 ; wire serial_in_reg; wire start; wire symbol_edge__7; wire [7:1]uart_rx_data_out; GND GND (.G(\<const0> )); VCC VCC (.P(\<const1> )); LUT5 #( .INIT(32'h00060000)) \bit_counter[0]_i_1 (.I0(bit_counter[0]), .I1(bit_counter0), .I2(start), .I3(buttons_pressed), .I4(cpu_clk_locked), .O(\bit_counter[0]_i_1_n_0 )); LUT6 #( .INIT(64'hD2D2D2D2D2D2D2D3)) \bit_counter[1]_i_1 (.I0(bit_counter0), .I1(bit_counter[0]), .I2(bit_counter[1]), .I3(bit_counter[2]), .I4(bit_counter[3]), .I5(serial_in_reg), .O(\bit_counter[1]_i_1_n_0 )); LUT6 #( .INIT(64'h000000000000AAA6)) \bit_counter[2]_i_1 (.I0(bit_counter[2]), .I1(bit_counter0), .I2(bit_counter[0]), .I3(bit_counter[1]), .I4(start), .I5(cpu_reset), .O(\bit_counter[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT5 #( .INIT(32'h00000001)) \bit_counter[2]_i_2 (.I0(serial_in_reg), .I1(bit_counter[3]), .I2(bit_counter[2]), .I3(bit_counter[1]), .I4(bit_counter[0]), .O(start)); LUT6 #( .INIT(64'hFFFD0002FFFD0003)) \bit_counter[3]_i_1 (.I0(bit_counter0), .I1(bit_counter[0]), .I2(bit_counter[1]), .I3(bit_counter[2]), .I4(bit_counter[3]), .I5(serial_in_reg), .O(\bit_counter[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT5 #( .INIT(32'hAAAAAAA8)) \bit_counter[3]_i_2 (.I0(symbol_edge__7), .I1(bit_counter[3]), .I2(bit_counter[2]), .I3(bit_counter[1]), .I4(bit_counter[0]), .O(bit_counter0)); FDRE \bit_counter_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(\bit_counter[0]_i_1_n_0 ), .Q(bit_counter[0]), .R(\<const0> )); FDRE \bit_counter_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(\bit_counter[1]_i_1_n_0 ), .Q(bit_counter[1]), .R(cpu_reset)); FDRE \bit_counter_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(\bit_counter[2]_i_1_n_0 ), .Q(bit_counter[2]), .R(\<const0> )); FDRE \bit_counter_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(\bit_counter[3]_i_1_n_0 ), .Q(bit_counter[3]), .R(cpu_reset)); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT1 #( .INIT(2'h1)) \clock_counter[0]_i_1__0 (.I0(clock_counter_reg[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT2 #( .INIT(4'h6)) \clock_counter[1]_i_1__0 (.I0(clock_counter_reg[0]), .I1(clock_counter_reg[1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT3 #( .INIT(8'h78)) \clock_counter[2]_i_1__0 (.I0(clock_counter_reg[0]), .I1(clock_counter_reg[1]), .I2(clock_counter_reg[2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT4 #( .INIT(16'h7F80)) \clock_counter[3]_i_1__0 (.I0(clock_counter_reg[1]), .I1(clock_counter_reg[0]), .I2(clock_counter_reg[2]), .I3(clock_counter_reg[3]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT5 #( .INIT(32'h7FFF8000)) \clock_counter[4]_i_1__0 (.I0(clock_counter_reg[2]), .I1(clock_counter_reg[0]), .I2(clock_counter_reg[1]), .I3(clock_counter_reg[3]), .I4(clock_counter_reg[4]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \clock_counter[5]_i_1__0 (.I0(clock_counter_reg[3]), .I1(clock_counter_reg[1]), .I2(clock_counter_reg[0]), .I3(clock_counter_reg[2]), .I4(clock_counter_reg[4]), .I5(clock_counter_reg[5]), .O(p_0_in__0[5])); LUT2 #( .INIT(4'h6)) \clock_counter[6]_i_1__0 (.I0(\clock_counter[8]_i_4_n_0 ), .I1(clock_counter_reg[6]), .O(p_0_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT3 #( .INIT(8'h78)) \clock_counter[7]_i_1__0 (.I0(\clock_counter[8]_i_4_n_0 ), .I1(clock_counter_reg[6]), .I2(clock_counter_reg[7]), .O(p_0_in__0[7])); LUT4 #( .INIT(16'hFFFB)) \clock_counter[8]_i_1__0 (.I0(buttons_pressed), .I1(cpu_clk_locked), .I2(start), .I3(symbol_edge__7), .O(\clock_counter[8]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT4 #( .INIT(16'h7F80)) \clock_counter[8]_i_2__0 (.I0(clock_counter_reg[6]), .I1(\clock_counter[8]_i_4_n_0 ), .I2(clock_counter_reg[7]), .I3(clock_counter_reg[8]), .O(p_0_in__0[8])); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT4 #( .INIT(16'h0008)) \clock_counter[8]_i_3 (.I0(\clock_counter[8]_i_5_n_0 ), .I1(clock_counter_reg[0]), .I2(clock_counter_reg[1]), .I3(clock_counter_reg[2]), .O(symbol_edge__7)); LUT6 #( .INIT(64'h8000000000000000)) \clock_counter[8]_i_4 (.I0(clock_counter_reg[5]), .I1(clock_counter_reg[3]), .I2(clock_counter_reg[1]), .I3(clock_counter_reg[0]), .I4(clock_counter_reg[2]), .I5(clock_counter_reg[4]), .O(\clock_counter[8]_i_4_n_0 )); LUT6 #( .INIT(64'h0020000000000000)) \clock_counter[8]_i_5 (.I0(clock_counter_reg[4]), .I1(clock_counter_reg[3]), .I2(clock_counter_reg[5]), .I3(clock_counter_reg[6]), .I4(clock_counter_reg[8]), .I5(clock_counter_reg[7]), .O(\clock_counter[8]_i_5_n_0 )); FDRE \clock_counter_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in__0[0]), .Q(clock_counter_reg[0]), .R(\clock_counter[8]_i_1__0_n_0 )); FDRE \clock_counter_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in__0[1]), .Q(clock_counter_reg[1]), .R(\clock_counter[8]_i_1__0_n_0 )); FDRE \clock_counter_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in__0[2]), .Q(clock_counter_reg[2]), .R(\clock_counter[8]_i_1__0_n_0 )); FDRE \clock_counter_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in__0[3]), .Q(clock_counter_reg[3]), .R(\clock_counter[8]_i_1__0_n_0 )); FDRE \clock_counter_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in__0[4]), .Q(clock_counter_reg[4]), .R(\clock_counter[8]_i_1__0_n_0 )); FDRE \clock_counter_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in__0[5]), .Q(clock_counter_reg[5]), .R(\clock_counter[8]_i_1__0_n_0 )); FDRE \clock_counter_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in__0[6]), .Q(clock_counter_reg[6]), .R(\clock_counter[8]_i_1__0_n_0 )); FDRE \clock_counter_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in__0[7]), .Q(clock_counter_reg[7]), .R(\clock_counter[8]_i_1__0_n_0 )); FDRE \clock_counter_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in__0[8]), .Q(clock_counter_reg[8]), .R(\clock_counter[8]_i_1__0_n_0 )); LUT5 #( .INIT(32'hFEFFAAAA)) has_byte_i_1 (.I0(has_byte0), .I1(has_byte_i_3_n_0), .I2(has_byte_i_4_n_0), .I3(has_byte_reg_0), .I4(has_byte), .O(has_byte_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT5 #( .INIT(32'h00100000)) has_byte_i_2 (.I0(bit_counter[2]), .I1(bit_counter[3]), .I2(bit_counter[0]), .I3(bit_counter[1]), .I4(symbol_edge__7), .O(has_byte0)); LUT6 #( .INIT(64'hFFFFFFFFFFFEFFFF)) has_byte_i_3 (.I0(has_byte_reg_1[3]), .I1(has_byte_reg_1[2]), .I2(has_byte_reg_1[0]), .I3(has_byte_reg_1[1]), .I4(has_byte_i_6_n_0), .I5(has_byte_reg_2), .O(has_byte_i_3_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFEF)) has_byte_i_4 (.I0(has_byte_reg_3), .I1(has_byte_reg_4[4]), .I2(has_byte_reg_4[2]), .I3(has_byte_reg_1[4]), .I4(has_byte_reg_4[7]), .I5(has_byte_reg_4[6]), .O(has_byte_i_4_n_0)); LUT4 #( .INIT(16'h0001)) has_byte_i_6 (.I0(has_byte_reg_4[0]), .I1(has_byte_reg_4[1]), .I2(has_byte_reg_4[3]), .I3(has_byte_reg_4[5]), .O(has_byte_i_6_n_0)); FDRE has_byte_reg (.C(cpu_clk), .CE(\<const1> ), .D(has_byte_i_1_n_0), .Q(has_byte), .R(cpu_reset)); LUT5 #( .INIT(32'h0000D0DD)) mem_reg_0_1_i_11 (.I0(br_inst_cnt_reg[2]), .I1(mem_reg_r1_0_31_0_5_i_58_0), .I2(mem_reg_r1_0_31_0_5_i_20), .I3(insts_cnt_reg[1]), .I4(mem_reg_r1_0_31_0_5_i_70_n_0), .O(br_inst_cnt_reg_3_sn_1)); LUT5 #( .INIT(32'h0000D0DD)) mem_reg_0_1_i_12 (.I0(br_inst_cnt_reg[1]), .I1(mem_reg_r1_0_31_0_5_i_58_0), .I2(mem_reg_r1_0_31_0_5_i_20), .I3(insts_cnt_reg[0]), .I4(mem_reg_r1_0_31_0_5_i_78_n_0), .O(br_inst_cnt_reg_2_sn_1)); LUT5 #( .INIT(32'h0000D0DD)) mem_reg_0_2_i_10 (.I0(br_inst_cnt_reg[3]), .I1(mem_reg_r1_0_31_0_5_i_58_0), .I2(mem_reg_r1_0_31_0_5_i_20), .I3(insts_cnt_reg[2]), .I4(mem_reg_r1_0_31_0_5_i_90_n_0), .O(br_inst_cnt_reg_4_sn_1)); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_0_5_i_30 (.I0(\rx_shift_reg[2]_0 ), .I1(mem_reg_r1_0_31_0_5_i_14), .I2(dout[0]), .I3(mem_reg_r1_0_31_0_5_i_14_0), .I4(mem_reg_r1_0_31_12_17_i_14[0]), .I5(mem_reg_r1_0_31_0_5_i_14_1), .O(mem_wb_mux[0])); LUT6 #( .INIT(64'h88A8AAAA88A888A8)) mem_reg_r1_0_31_0_5_i_36 (.I0(mem_reg_r1_0_31_0_5_i_14), .I1(mem_reg_r1_0_31_0_5_i_70_n_0), .I2(insts_cnt_reg[1]), .I3(mem_reg_r1_0_31_0_5_i_20), .I4(mem_reg_r1_0_31_0_5_i_58_0), .I5(br_inst_cnt_reg[2]), .O(insts_cnt_reg_3_sn_1)); LUT6 #( .INIT(64'h88A8AAAA88A888A8)) mem_reg_r1_0_31_0_5_i_40 (.I0(mem_reg_r1_0_31_0_5_i_14), .I1(mem_reg_r1_0_31_0_5_i_78_n_0), .I2(insts_cnt_reg[0]), .I3(mem_reg_r1_0_31_0_5_i_20), .I4(mem_reg_r1_0_31_0_5_i_58_0), .I5(br_inst_cnt_reg[1]), .O(insts_cnt_reg_2_sn_1)); LUT6 #( .INIT(64'h88A8AAAA88A888A8)) mem_reg_r1_0_31_0_5_i_44 (.I0(mem_reg_r1_0_31_0_5_i_14), .I1(mem_reg_r1_0_31_0_5_i_84_n_0), .I2(insts_cnt_reg[3]), .I3(mem_reg_r1_0_31_0_5_i_20), .I4(mem_reg_r1_0_31_0_5_i_58_0), .I5(br_inst_cnt_reg[4]), .O(insts_cnt_reg_5_sn_1)); LUT6 #( .INIT(64'h88A8AAAA88A888A8)) mem_reg_r1_0_31_0_5_i_48 (.I0(mem_reg_r1_0_31_0_5_i_14), .I1(mem_reg_r1_0_31_0_5_i_90_n_0), .I2(insts_cnt_reg[2]), .I3(mem_reg_r1_0_31_0_5_i_20), .I4(mem_reg_r1_0_31_0_5_i_58_0), .I5(br_inst_cnt_reg[3]), .O(insts_cnt_reg_4_sn_1)); LUT6 #( .INIT(64'h2022000020222022)) mem_reg_r1_0_31_0_5_i_58 (.I0(mem_reg_r1_0_31_0_5_i_95_n_0), .I1(mem_reg_0_0_i_316), .I2(mem_reg_0_0_i_316_0), .I3(uart_rx_data_out[1]), .I4(mem_reg_0_0_i_316_1), .I5(cycle_cnt_reg[0]), .O(\rx_shift_reg[2]_0 )); LUT6 #( .INIT(64'hFFFF44F444F444F4)) mem_reg_r1_0_31_0_5_i_70 (.I0(mem_reg_0_0_i_316_1), .I1(cycle_cnt_reg[2]), .I2(uart_rx_data_out[3]), .I3(mem_reg_0_0_i_316_0), .I4(br_corr_cnt_reg[1]), .I5(mem_reg_r1_0_31_6_11_i_7), .O(mem_reg_r1_0_31_0_5_i_70_n_0)); LUT6 #( .INIT(64'hFFFF44F444F444F4)) mem_reg_r1_0_31_0_5_i_78 (.I0(mem_reg_0_0_i_316_1), .I1(cycle_cnt_reg[1]), .I2(uart_rx_data_out[2]), .I3(mem_reg_0_0_i_316_0), .I4(br_corr_cnt_reg[0]), .I5(mem_reg_r1_0_31_6_11_i_7), .O(mem_reg_r1_0_31_0_5_i_78_n_0)); LUT6 #( .INIT(64'hFFFF44F444F444F4)) mem_reg_r1_0_31_0_5_i_84 (.I0(mem_reg_0_0_i_316_1), .I1(cycle_cnt_reg[4]), .I2(uart_rx_data_out[5]), .I3(mem_reg_0_0_i_316_0), .I4(br_corr_cnt_reg[3]), .I5(mem_reg_r1_0_31_6_11_i_7), .O(mem_reg_r1_0_31_0_5_i_84_n_0)); LUT6 #( .INIT(64'hFFFF44F444F444F4)) mem_reg_r1_0_31_0_5_i_90 (.I0(mem_reg_0_0_i_316_1), .I1(cycle_cnt_reg[3]), .I2(uart_rx_data_out[4]), .I3(mem_reg_0_0_i_316_0), .I4(br_corr_cnt_reg[2]), .I5(mem_reg_r1_0_31_6_11_i_7), .O(mem_reg_r1_0_31_0_5_i_90_n_0)); LUT5 #( .INIT(32'hDDDDD0DD)) mem_reg_r1_0_31_0_5_i_95 (.I0(br_inst_cnt_reg[0]), .I1(mem_reg_r1_0_31_0_5_i_58_0), .I2(mem_reg_r1_0_31_0_5_i_58_1), .I3(has_byte), .I4(rx_running__2), .O(mem_reg_r1_0_31_0_5_i_95_n_0)); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_12_17_i_25 (.I0(\br_corr_cnt_reg[7] ), .I1(mem_reg_r1_0_31_0_5_i_14), .I2(dout[1]), .I3(mem_reg_r1_0_31_0_5_i_14_0), .I4(mem_reg_r1_0_31_12_17_i_14[1]), .I5(mem_reg_r1_0_31_0_5_i_14_1), .O(mem_wb_mux[1])); LUT6 #( .INIT(64'hAAAA88A888A888A8)) mem_reg_r1_0_31_6_11_i_25 (.I0(mem_reg_r1_0_31_0_5_i_14), .I1(mem_reg_r1_0_31_6_11_i_41_n_0), .I2(insts_cnt_reg[5]), .I3(mem_reg_r1_0_31_0_5_i_20), .I4(mem_reg_r1_0_31_6_11_i_7), .I5(br_corr_cnt_reg[5]), .O(\insts_cnt_reg[7] )); LUT6 #( .INIT(64'h88A8AAAA88A888A8)) mem_reg_r1_0_31_6_11_i_29 (.I0(mem_reg_r1_0_31_0_5_i_14), .I1(mem_reg_r1_0_31_6_11_i_48_n_0), .I2(insts_cnt_reg[4]), .I3(mem_reg_r1_0_31_0_5_i_20), .I4(mem_reg_r1_0_31_0_5_i_58_0), .I5(br_inst_cnt_reg[5]), .O(\insts_cnt_reg[6] )); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_6_11_i_41 (.I0(mem_reg_0_0_i_316_1), .I1(cycle_cnt_reg[6]), .I2(uart_rx_data_out[7]), .I3(mem_reg_0_0_i_316_0), .I4(br_inst_cnt_reg[6]), .I5(mem_reg_r1_0_31_0_5_i_58_0), .O(mem_reg_r1_0_31_6_11_i_41_n_0)); LUT6 #( .INIT(64'hFFFF44F444F444F4)) mem_reg_r1_0_31_6_11_i_48 (.I0(mem_reg_0_0_i_316_1), .I1(cycle_cnt_reg[5]), .I2(uart_rx_data_out[6]), .I3(mem_reg_0_0_i_316_0), .I4(br_corr_cnt_reg[4]), .I5(mem_reg_r1_0_31_6_11_i_7), .O(mem_reg_r1_0_31_6_11_i_48_n_0)); LUT5 #( .INIT(32'h00007077)) mem_reg_r1_0_31_6_11_i_51 (.I0(br_corr_cnt_reg[5]), .I1(mem_reg_r1_0_31_6_11_i_7), .I2(mem_reg_r1_0_31_0_5_i_20), .I3(insts_cnt_reg[5]), .I4(mem_reg_r1_0_31_6_11_i_41_n_0), .O(\br_corr_cnt_reg[7] )); LUT5 #( .INIT(32'h10000000)) \rx_shift[9]_i_1 (.I0(clock_counter_reg[2]), .I1(clock_counter_reg[1]), .I2(clock_counter_reg[0]), .I3(\rx_shift[9]_i_2_n_0 ), .I4(rx_running__2), .O(rx_shift0)); LUT6 #( .INIT(64'h0000008000000000)) \rx_shift[9]_i_2 (.I0(clock_counter_reg[3]), .I1(clock_counter_reg[4]), .I2(clock_counter_reg[6]), .I3(clock_counter_reg[5]), .I4(clock_counter_reg[8]), .I5(clock_counter_reg[7]), .O(\rx_shift[9]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT4 #( .INIT(16'hFFFE)) \rx_shift[9]_i_3 (.I0(bit_counter[0]), .I1(bit_counter[1]), .I2(bit_counter[2]), .I3(bit_counter[3]), .O(rx_running__2)); FDRE \rx_shift_reg[1] (.C(cpu_clk), .CE(rx_shift0), .D(uart_rx_data_out[1]), .Q(Q), .R(\<const0> )); FDRE \rx_shift_reg[2] (.C(cpu_clk), .CE(rx_shift0), .D(uart_rx_data_out[2]), .Q(uart_rx_data_out[1]), .R(\<const0> )); FDRE \rx_shift_reg[3] (.C(cpu_clk), .CE(rx_shift0), .D(uart_rx_data_out[3]), .Q(uart_rx_data_out[2]), .R(\<const0> )); FDRE \rx_shift_reg[4] (.C(cpu_clk), .CE(rx_shift0), .D(uart_rx_data_out[4]), .Q(uart_rx_data_out[3]), .R(\<const0> )); FDRE \rx_shift_reg[5] (.C(cpu_clk), .CE(rx_shift0), .D(uart_rx_data_out[5]), .Q(uart_rx_data_out[4]), .R(\<const0> )); FDRE \rx_shift_reg[6] (.C(cpu_clk), .CE(rx_shift0), .D(uart_rx_data_out[6]), .Q(uart_rx_data_out[5]), .R(\<const0> )); FDRE \rx_shift_reg[7] (.C(cpu_clk), .CE(rx_shift0), .D(uart_rx_data_out[7]), .Q(uart_rx_data_out[6]), .R(\<const0> )); FDRE \rx_shift_reg[8] (.C(cpu_clk), .CE(rx_shift0), .D(rx_shift), .Q(uart_rx_data_out[7]), .R(\<const0> )); FDRE \rx_shift_reg[9] (.C(cpu_clk), .CE(rx_shift0), .D(serial_in_reg), .Q(rx_shift), .R(\<const0> )); endmodule module uart_transmitter (\tx_shift_reg[8]_0 , \tx_shift_reg[0]_0 , \f_ex_inst_reg[2] , \f_ex_inst_reg[2]_0 , \f_ex_inst_reg[2]_1 , \f_ex_inst_reg[2]_2 , \f_ex_inst_reg[2]_3 , \f_ex_inst_reg[2]_4 , symbol_edge__7, tx_running__2, \f_ex_inst_reg[12] , \wb_alu_reg[22] , \wb_alu_reg[23] , \wb_alu_reg[24] , \wb_alu_reg[25] , \wb_alu_reg[26] , \wb_alu_reg[27] , \wb_alu_reg[28] , \wb_alu_reg[29] , \wb_alu_reg[30] , \wb_alu_reg[31] , \f_ex_inst_reg[14] , \f_ex_inst_reg[14]_0 , \f_ex_inst_reg[12]_0 , \f_ex_inst_reg[12]_1 , \f_ex_inst_reg[12]_2 , \f_ex_inst_reg[12]_3 , \f_ex_inst_reg[13] , mem_wb_mux, .br_inst_cnt_reg_0_sp_1(br_inst_cnt_reg_0_sn_1), \tx_shift_reg[0]_1 , \tx_shift_reg[7]_0 , cpu_clk, \tx_shift_reg[8]_1 , \bit_counter[3]_i_33 , \bit_counter[3]_i_33_0 , ALUSel, start, Q, wb_BrLt_i_14, wb_BrEq_i_35, wb_BrLt_i_14_0, wb_BrEq_i_35_0, wb_BrLt_i_14_1, \bit_counter[3]_i_21 , mem_reg_r1_0_31_0_5_i_16, dout, mem_reg_r1_0_31_0_5_i_16_0, mem_reg_r1_0_31_0_5_i_16_1, mem_reg_r1_0_31_0_5_i_16_2, mem_reg_0_0_i_321, mem_reg_0_0_i_321_0, br_inst_cnt_reg, mem_reg_0_0_i_321_1, mem_reg_0_0_i_321_2, mem_reg_r1_0_31_0_5_i_64_0, br_corr_cnt_reg, mem_reg_r1_0_31_0_5_i_64_1, cpu_reset, buttons_pressed, cpu_clk_locked, SR); output [6:0]\tx_shift_reg[8]_0 ; output [0:0]\tx_shift_reg[0]_0 ; output \f_ex_inst_reg[2] ; output \f_ex_inst_reg[2]_0 ; output \f_ex_inst_reg[2]_1 ; output \f_ex_inst_reg[2]_2 ; output \f_ex_inst_reg[2]_3 ; output \f_ex_inst_reg[2]_4 ; output symbol_edge__7; output tx_running__2; output \f_ex_inst_reg[12] ; output \wb_alu_reg[22] ; output \wb_alu_reg[23] ; output \wb_alu_reg[24] ; output \wb_alu_reg[25] ; output \wb_alu_reg[26] ; output \wb_alu_reg[27] ; output \wb_alu_reg[28] ; output \wb_alu_reg[29] ; output \wb_alu_reg[30] ; output \wb_alu_reg[31] ; output \f_ex_inst_reg[14] ; output \f_ex_inst_reg[14]_0 ; output \f_ex_inst_reg[12]_0 ; output \f_ex_inst_reg[12]_1 ; output \f_ex_inst_reg[12]_2 ; output \f_ex_inst_reg[12]_3 ; output \f_ex_inst_reg[13] ; output [0:0]mem_wb_mux; input \tx_shift_reg[0]_1 ; input [6:0]\tx_shift_reg[7]_0 ; input cpu_clk; input \tx_shift_reg[8]_1 ; input \bit_counter[3]_i_33 ; input [4:0]\bit_counter[3]_i_33_0 ; input [2:0]ALUSel; input start; input [5:0]Q; input [9:0]wb_BrLt_i_14; input wb_BrEq_i_35; input [9:0]wb_BrLt_i_14_0; input wb_BrEq_i_35_0; input [9:0]wb_BrLt_i_14_1; input [5:0]\bit_counter[3]_i_21 ; input mem_reg_r1_0_31_0_5_i_16; input [0:0]dout; input mem_reg_r1_0_31_0_5_i_16_0; input [0:0]mem_reg_r1_0_31_0_5_i_16_1; input mem_reg_r1_0_31_0_5_i_16_2; input mem_reg_0_0_i_321; input mem_reg_0_0_i_321_0; input [0:0]br_inst_cnt_reg; input mem_reg_0_0_i_321_1; input [0:0]mem_reg_0_0_i_321_2; input mem_reg_r1_0_31_0_5_i_64_0; input [0:0]br_corr_cnt_reg; input mem_reg_r1_0_31_0_5_i_64_1; input cpu_reset; input buttons_pressed; input cpu_clk_locked; input [0:0]SR; output br_inst_cnt_reg_0_sn_1; wire \<const0> ; wire \<const1> ; wire [2:0]ALUSel; wire [5:0]Q; wire [0:0]SR; wire bit_counter0; wire \bit_counter[0]_i_1_n_0 ; wire \bit_counter[1]_i_1_n_0 ; wire \bit_counter[2]_i_1_n_0 ; wire [5:0]\bit_counter[3]_i_21 ; wire \bit_counter[3]_i_2_n_0 ; wire \bit_counter[3]_i_33 ; wire [4:0]\bit_counter[3]_i_33_0 ; wire \bit_counter_reg_n_0_[0] ; wire \bit_counter_reg_n_0_[1] ; wire \bit_counter_reg_n_0_[2] ; wire \bit_counter_reg_n_0_[3] ; wire [0:0]br_corr_cnt_reg; wire [0:0]br_inst_cnt_reg; wire br_inst_cnt_reg_0_sn_1; wire buttons_pressed; wire \clock_counter[8]_i_3__0_n_0 ; wire [8:0]clock_counter_reg; wire cpu_clk; wire cpu_clk_locked; wire cpu_reset; wire [0:0]dout; wire \f_ex_inst_reg[12] ; wire \f_ex_inst_reg[12]_0 ; wire \f_ex_inst_reg[12]_1 ; wire \f_ex_inst_reg[12]_2 ; wire \f_ex_inst_reg[12]_3 ; wire \f_ex_inst_reg[13] ; wire \f_ex_inst_reg[14] ; wire \f_ex_inst_reg[14]_0 ; wire \f_ex_inst_reg[2] ; wire \f_ex_inst_reg[2]_0 ; wire \f_ex_inst_reg[2]_1 ; wire \f_ex_inst_reg[2]_2 ; wire \f_ex_inst_reg[2]_3 ; wire \f_ex_inst_reg[2]_4 ; wire mem_reg_0_0_i_321; wire mem_reg_0_0_i_321_0; wire mem_reg_0_0_i_321_1; wire [0:0]mem_reg_0_0_i_321_2; wire mem_reg_r1_0_31_0_5_i_101_n_0; wire mem_reg_r1_0_31_0_5_i_116_n_0; wire mem_reg_r1_0_31_0_5_i_16; wire mem_reg_r1_0_31_0_5_i_16_0; wire [0:0]mem_reg_r1_0_31_0_5_i_16_1; wire mem_reg_r1_0_31_0_5_i_16_2; wire mem_reg_r1_0_31_0_5_i_64_0; wire mem_reg_r1_0_31_0_5_i_64_1; wire [0:0]mem_wb_mux; wire [8:0]p_0_in; wire [0:0]p_1_in; wire start; wire symbol_edge__7; wire tx_running__2; wire [1:1]tx_shift; wire \tx_shift[7]_i_4_n_0 ; wire [0:0]\tx_shift_reg[0]_0 ; wire \tx_shift_reg[0]_1 ; wire [6:0]\tx_shift_reg[7]_0 ; wire [6:0]\tx_shift_reg[8]_0 ; wire \tx_shift_reg[8]_1 ; wire wb_BrEq_i_35; wire wb_BrEq_i_35_0; wire [9:0]wb_BrLt_i_14; wire [9:0]wb_BrLt_i_14_0; wire [9:0]wb_BrLt_i_14_1; wire \wb_alu_reg[22] ; wire \wb_alu_reg[23] ; wire \wb_alu_reg[24] ; wire \wb_alu_reg[25] ; wire \wb_alu_reg[26] ; wire \wb_alu_reg[27] ; wire \wb_alu_reg[28] ; wire \wb_alu_reg[29] ; wire \wb_alu_reg[30] ; wire \wb_alu_reg[31] ; GND GND (.G(\<const0> )); VCC VCC (.P(\<const1> )); LUT5 #( .INIT(32'h00060000)) \bit_counter[0]_i_1 (.I0(\bit_counter_reg_n_0_[0] ), .I1(bit_counter0), .I2(start), .I3(buttons_pressed), .I4(cpu_clk_locked), .O(\bit_counter[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT4 #( .INIT(16'hFBF4)) \bit_counter[1]_i_1 (.I0(\bit_counter_reg_n_0_[0] ), .I1(bit_counter0), .I2(start), .I3(\bit_counter_reg_n_0_[1] ), .O(\bit_counter[1]_i_1_n_0 )); LUT6 #( .INIT(64'h000000000000AAA6)) \bit_counter[2]_i_1 (.I0(\bit_counter_reg_n_0_[2] ), .I1(bit_counter0), .I2(\bit_counter_reg_n_0_[0] ), .I3(\bit_counter_reg_n_0_[1] ), .I4(start), .I5(cpu_reset), .O(\bit_counter[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT4 #( .INIT(16'hFFFE)) \bit_counter[3]_i_10 (.I0(\bit_counter_reg_n_0_[0] ), .I1(\bit_counter_reg_n_0_[1] ), .I2(\bit_counter_reg_n_0_[2] ), .I3(\bit_counter_reg_n_0_[3] ), .O(tx_running__2)); LUT6 #( .INIT(64'hFFFFFEFFFFFF0100)) \bit_counter[3]_i_2 (.I0(\bit_counter_reg_n_0_[1] ), .I1(\bit_counter_reg_n_0_[0] ), .I2(\bit_counter_reg_n_0_[2] ), .I3(bit_counter0), .I4(start), .I5(\bit_counter_reg_n_0_[3] ), .O(\bit_counter[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT3 #( .INIT(8'h4F)) \bit_counter[3]_i_26 (.I0(\bit_counter[3]_i_33 ), .I1(\bit_counter[3]_i_33_0 [0]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2]_3 )); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT5 #( .INIT(32'hAAAAAAA8)) \bit_counter[3]_i_3 (.I0(symbol_edge__7), .I1(\bit_counter_reg_n_0_[3] ), .I2(\bit_counter_reg_n_0_[2] ), .I3(\bit_counter_reg_n_0_[1] ), .I4(\bit_counter_reg_n_0_[0] ), .O(bit_counter0)); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT4 #( .INIT(16'hEEEF)) \bit_counter[3]_i_43 (.I0(ALUSel[1]), .I1(ALUSel[0]), .I2(\bit_counter[3]_i_21 [5]), .I3(\f_ex_inst_reg[12] ), .O(\f_ex_inst_reg[14] )); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT3 #( .INIT(8'h4F)) \bit_counter[3]_i_46 (.I0(\bit_counter[3]_i_33 ), .I1(\bit_counter[3]_i_33_0 [2]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2]_1 )); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT3 #( .INIT(8'h4F)) \bit_counter[3]_i_49 (.I0(\bit_counter[3]_i_33 ), .I1(\bit_counter[3]_i_33_0 [1]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2]_2 )); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT3 #( .INIT(8'h4F)) \bit_counter[3]_i_55 (.I0(\bit_counter[3]_i_33 ), .I1(\bit_counter[3]_i_33_0 [3]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT4 #( .INIT(16'hEEEF)) \bit_counter[3]_i_56 (.I0(ALUSel[1]), .I1(ALUSel[0]), .I2(\bit_counter[3]_i_21 [4]), .I3(\f_ex_inst_reg[12] ), .O(\f_ex_inst_reg[14]_0 )); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT3 #( .INIT(8'h4F)) \bit_counter[3]_i_61 (.I0(\bit_counter[3]_i_33 ), .I1(\bit_counter[3]_i_33_0 [4]), .I2(ALUSel[2]), .O(\f_ex_inst_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT3 #( .INIT(8'hFE)) \bit_counter[3]_i_65 (.I0(ALUSel[2]), .I1(ALUSel[1]), .I2(ALUSel[0]), .O(\f_ex_inst_reg[2]_4 )); FDRE #( .INIT(1'b0)) \bit_counter_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(\bit_counter[0]_i_1_n_0 ), .Q(\bit_counter_reg_n_0_[0] ), .R(\<const0> )); FDRE #( .INIT(1'b0)) \bit_counter_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(\bit_counter[1]_i_1_n_0 ), .Q(\bit_counter_reg_n_0_[1] ), .R(cpu_reset)); FDRE #( .INIT(1'b0)) \bit_counter_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(\bit_counter[2]_i_1_n_0 ), .Q(\bit_counter_reg_n_0_[2] ), .R(\<const0> )); FDRE #( .INIT(1'b0)) \bit_counter_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(\bit_counter[3]_i_2_n_0 ), .Q(\bit_counter_reg_n_0_[3] ), .R(cpu_reset)); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT1 #( .INIT(2'h1)) \clock_counter[0]_i_1 (.I0(clock_counter_reg[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT2 #( .INIT(4'h6)) \clock_counter[1]_i_1 (.I0(clock_counter_reg[0]), .I1(clock_counter_reg[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT3 #( .INIT(8'h78)) \clock_counter[2]_i_1 (.I0(clock_counter_reg[0]), .I1(clock_counter_reg[1]), .I2(clock_counter_reg[2]), .O(p_0_in[2])); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT4 #( .INIT(16'h7F80)) \clock_counter[3]_i_1 (.I0(clock_counter_reg[1]), .I1(clock_counter_reg[0]), .I2(clock_counter_reg[2]), .I3(clock_counter_reg[3]), .O(p_0_in[3])); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT5 #( .INIT(32'h7FFF8000)) \clock_counter[4]_i_1 (.I0(clock_counter_reg[2]), .I1(clock_counter_reg[0]), .I2(clock_counter_reg[1]), .I3(clock_counter_reg[3]), .I4(clock_counter_reg[4]), .O(p_0_in[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \clock_counter[5]_i_1 (.I0(clock_counter_reg[3]), .I1(clock_counter_reg[1]), .I2(clock_counter_reg[0]), .I3(clock_counter_reg[2]), .I4(clock_counter_reg[4]), .I5(clock_counter_reg[5]), .O(p_0_in[5])); LUT2 #( .INIT(4'h6)) \clock_counter[6]_i_1 (.I0(\clock_counter[8]_i_3__0_n_0 ), .I1(clock_counter_reg[6]), .O(p_0_in[6])); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT3 #( .INIT(8'h78)) \clock_counter[7]_i_1 (.I0(\clock_counter[8]_i_3__0_n_0 ), .I1(clock_counter_reg[6]), .I2(clock_counter_reg[7]), .O(p_0_in[7])); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT4 #( .INIT(16'h7F80)) \clock_counter[8]_i_2 (.I0(clock_counter_reg[6]), .I1(\clock_counter[8]_i_3__0_n_0 ), .I2(clock_counter_reg[7]), .I3(clock_counter_reg[8]), .O(p_0_in[8])); LUT6 #( .INIT(64'h8000000000000000)) \clock_counter[8]_i_3__0 (.I0(clock_counter_reg[5]), .I1(clock_counter_reg[3]), .I2(clock_counter_reg[1]), .I3(clock_counter_reg[0]), .I4(clock_counter_reg[2]), .I5(clock_counter_reg[4]), .O(\clock_counter[8]_i_3__0_n_0 )); FDRE #( .INIT(1'b0)) \clock_counter_reg[0] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in[0]), .Q(clock_counter_reg[0]), .R(SR)); FDRE #( .INIT(1'b0)) \clock_counter_reg[1] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in[1]), .Q(clock_counter_reg[1]), .R(SR)); FDRE #( .INIT(1'b0)) \clock_counter_reg[2] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in[2]), .Q(clock_counter_reg[2]), .R(SR)); FDRE #( .INIT(1'b0)) \clock_counter_reg[3] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in[3]), .Q(clock_counter_reg[3]), .R(SR)); FDRE #( .INIT(1'b0)) \clock_counter_reg[4] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in[4]), .Q(clock_counter_reg[4]), .R(SR)); FDRE #( .INIT(1'b0)) \clock_counter_reg[5] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in[5]), .Q(clock_counter_reg[5]), .R(SR)); FDRE #( .INIT(1'b0)) \clock_counter_reg[6] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in[6]), .Q(clock_counter_reg[6]), .R(SR)); FDRE #( .INIT(1'b0)) \clock_counter_reg[7] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in[7]), .Q(clock_counter_reg[7]), .R(SR)); FDRE #( .INIT(1'b0)) \clock_counter_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(p_0_in[8]), .Q(clock_counter_reg[8]), .R(SR)); LUT6 #( .INIT(64'h000C000000080008)) mem_reg_0_0_i_89 (.I0(Q[5]), .I1(Q[2]), .I2(Q[1]), .I3(Q[4]), .I4(Q[3]), .I5(Q[0]), .O(\f_ex_inst_reg[12] )); LUT6 #( .INIT(64'h7777777777777770)) mem_reg_r1_0_31_0_5_i_101 (.I0(mem_reg_r1_0_31_0_5_i_64_0), .I1(br_corr_cnt_reg), .I2(mem_reg_r1_0_31_0_5_i_64_1), .I3(mem_reg_r1_0_31_0_5_i_116_n_0), .I4(\bit_counter_reg_n_0_[2] ), .I5(\bit_counter_reg_n_0_[3] ), .O(mem_reg_r1_0_31_0_5_i_101_n_0)); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT2 #( .INIT(4'hE)) mem_reg_r1_0_31_0_5_i_116 (.I0(\bit_counter_reg_n_0_[0] ), .I1(\bit_counter_reg_n_0_[1] ), .O(mem_reg_r1_0_31_0_5_i_116_n_0)); LUT6 #( .INIT(64'h44F444F4FFFF44F4)) mem_reg_r1_0_31_0_5_i_33 (.I0(br_inst_cnt_reg_0_sn_1), .I1(mem_reg_r1_0_31_0_5_i_16), .I2(dout), .I3(mem_reg_r1_0_31_0_5_i_16_0), .I4(mem_reg_r1_0_31_0_5_i_16_1), .I5(mem_reg_r1_0_31_0_5_i_16_2), .O(mem_wb_mux)); LUT6 #( .INIT(64'h2022000020222022)) mem_reg_r1_0_31_0_5_i_64 (.I0(mem_reg_r1_0_31_0_5_i_101_n_0), .I1(mem_reg_0_0_i_321), .I2(mem_reg_0_0_i_321_0), .I3(br_inst_cnt_reg), .I4(mem_reg_0_0_i_321_1), .I5(mem_reg_0_0_i_321_2), .O(br_inst_cnt_reg_0_sn_1)); LUT2 #( .INIT(4'h2)) \tx_shift[0]_i_1 (.I0(tx_shift), .I1(start), .O(p_1_in)); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT4 #( .INIT(16'h0008)) \tx_shift[7]_i_3 (.I0(\tx_shift[7]_i_4_n_0 ), .I1(clock_counter_reg[0]), .I2(clock_counter_reg[1]), .I3(clock_counter_reg[2]), .O(symbol_edge__7)); LUT6 #( .INIT(64'h0020000000000000)) \tx_shift[7]_i_4 (.I0(clock_counter_reg[4]), .I1(clock_counter_reg[3]), .I2(clock_counter_reg[5]), .I3(clock_counter_reg[6]), .I4(clock_counter_reg[8]), .I5(clock_counter_reg[7]), .O(\tx_shift[7]_i_4_n_0 )); FDRE #( .INIT(1'b1)) \tx_shift_reg[0] (.C(cpu_clk), .CE(\tx_shift_reg[0]_1 ), .D(p_1_in), .Q(\tx_shift_reg[0]_0 ), .R(\<const0> )); FDRE #( .INIT(1'b1)) \tx_shift_reg[1] (.C(cpu_clk), .CE(\tx_shift_reg[0]_1 ), .D(\tx_shift_reg[7]_0 [0]), .Q(tx_shift), .R(\<const0> )); FDRE #( .INIT(1'b1)) \tx_shift_reg[2] (.C(cpu_clk), .CE(\tx_shift_reg[0]_1 ), .D(\tx_shift_reg[7]_0 [1]), .Q(\tx_shift_reg[8]_0 [0]), .R(\<const0> )); FDRE #( .INIT(1'b1)) \tx_shift_reg[3] (.C(cpu_clk), .CE(\tx_shift_reg[0]_1 ), .D(\tx_shift_reg[7]_0 [2]), .Q(\tx_shift_reg[8]_0 [1]), .R(\<const0> )); FDRE #( .INIT(1'b1)) \tx_shift_reg[4] (.C(cpu_clk), .CE(\tx_shift_reg[0]_1 ), .D(\tx_shift_reg[7]_0 [3]), .Q(\tx_shift_reg[8]_0 [2]), .R(\<const0> )); FDRE #( .INIT(1'b1)) \tx_shift_reg[5] (.C(cpu_clk), .CE(\tx_shift_reg[0]_1 ), .D(\tx_shift_reg[7]_0 [4]), .Q(\tx_shift_reg[8]_0 [3]), .R(\<const0> )); FDRE #( .INIT(1'b1)) \tx_shift_reg[6] (.C(cpu_clk), .CE(\tx_shift_reg[0]_1 ), .D(\tx_shift_reg[7]_0 [5]), .Q(\tx_shift_reg[8]_0 [4]), .R(\<const0> )); FDRE #( .INIT(1'b1)) \tx_shift_reg[7] (.C(cpu_clk), .CE(\tx_shift_reg[0]_1 ), .D(\tx_shift_reg[7]_0 [6]), .Q(\tx_shift_reg[8]_0 [5]), .R(\<const0> )); FDRE #( .INIT(1'b1)) \tx_shift_reg[8] (.C(cpu_clk), .CE(\<const1> ), .D(\tx_shift_reg[8]_1 ), .Q(\tx_shift_reg[8]_0 [6]), .R(\<const0> )); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT2 #( .INIT(4'h2)) \wb_alu[20]_i_10 (.I0(\bit_counter[3]_i_21 [0]), .I1(\f_ex_inst_reg[12] ), .O(\f_ex_inst_reg[12]_3 )); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT2 #( .INIT(4'h2)) \wb_alu[21]_i_10 (.I0(\bit_counter[3]_i_21 [1]), .I1(\f_ex_inst_reg[12] ), .O(\f_ex_inst_reg[12]_2 )); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT2 #( .INIT(4'h2)) \wb_alu[22]_i_10 (.I0(\bit_counter[3]_i_21 [2]), .I1(\f_ex_inst_reg[12] ), .O(\f_ex_inst_reg[12]_1 )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[23]_i_19 (.I0(wb_BrLt_i_14[1]), .I1(wb_BrEq_i_35), .I2(wb_BrLt_i_14_0[1]), .I3(wb_BrEq_i_35_0), .I4(wb_BrLt_i_14_1[1]), .O(\wb_alu_reg[23] )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[23]_i_20 (.I0(wb_BrLt_i_14[0]), .I1(wb_BrEq_i_35), .I2(wb_BrLt_i_14_0[0]), .I3(wb_BrEq_i_35_0), .I4(wb_BrLt_i_14_1[0]), .O(\wb_alu_reg[22] )); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT2 #( .INIT(4'h2)) \wb_alu[23]_i_23 (.I0(\bit_counter[3]_i_21 [3]), .I1(\f_ex_inst_reg[12] ), .O(\f_ex_inst_reg[12]_0 )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[27]_i_18 (.I0(wb_BrLt_i_14[5]), .I1(wb_BrEq_i_35), .I2(wb_BrLt_i_14_0[5]), .I3(wb_BrEq_i_35_0), .I4(wb_BrLt_i_14_1[5]), .O(\wb_alu_reg[27] )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[27]_i_19 (.I0(wb_BrLt_i_14[4]), .I1(wb_BrEq_i_35), .I2(wb_BrLt_i_14_0[4]), .I3(wb_BrEq_i_35_0), .I4(wb_BrLt_i_14_1[4]), .O(\wb_alu_reg[26] )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[27]_i_20 (.I0(wb_BrLt_i_14[3]), .I1(wb_BrEq_i_35), .I2(wb_BrLt_i_14_0[3]), .I3(wb_BrEq_i_35_0), .I4(wb_BrLt_i_14_1[3]), .O(\wb_alu_reg[25] )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[27]_i_21 (.I0(wb_BrLt_i_14[2]), .I1(wb_BrEq_i_35), .I2(wb_BrLt_i_14_0[2]), .I3(wb_BrEq_i_35_0), .I4(wb_BrLt_i_14_1[2]), .O(\wb_alu_reg[24] )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[29]_i_25 (.I0(wb_BrLt_i_14[7]), .I1(wb_BrEq_i_35), .I2(wb_BrLt_i_14_0[7]), .I3(wb_BrEq_i_35_0), .I4(wb_BrLt_i_14_1[7]), .O(\wb_alu_reg[29] )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[29]_i_26 (.I0(wb_BrLt_i_14[6]), .I1(wb_BrEq_i_35), .I2(wb_BrLt_i_14_0[6]), .I3(wb_BrEq_i_35_0), .I4(wb_BrLt_i_14_1[6]), .O(\wb_alu_reg[28] )); LUT2 #( .INIT(4'h1)) \wb_alu[29]_i_4 (.I0(ALUSel[0]), .I1(ALUSel[1]), .O(\f_ex_inst_reg[13] )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[30]_i_15 (.I0(wb_BrLt_i_14[8]), .I1(wb_BrEq_i_35), .I2(wb_BrLt_i_14_0[8]), .I3(wb_BrEq_i_35_0), .I4(wb_BrLt_i_14_1[8]), .O(\wb_alu_reg[30] )); LUT5 #( .INIT(32'hB8BBB888)) \wb_alu[31]_i_14 (.I0(wb_BrLt_i_14[9]), .I1(wb_BrEq_i_35), .I2(wb_BrLt_i_14_0[9]), .I3(wb_BrEq_i_35_0), .I4(wb_BrLt_i_14_1[9]), .O(\wb_alu_reg[31] )); endmodule (* BAUD_RATE = "115200" *) (* B_PULSE_CNT_MAX = "200" *) (* B_SAMPLE_CNT_MAX = "25000" *) (* CPU_CLK_CLKFBOUT_MULT = "34" *) (* CPU_CLK_CLKOUT_DIVIDE = "17" *) (* CPU_CLK_DIVCLK_DIVIDE = "5" *) (* CPU_CLOCK_FREQ = "50000000" *) (* N_VOICES = "1" *) (* RESET_PC = "1073741824" *) (* STRUCTURAL_NETLIST = "yes" *) module z1top (CLK_125MHZ_FPGA, BUTTONS, SWITCHES, LEDS, FPGA_SERIAL_RX, FPGA_SERIAL_TX, AUD_PWM, AUD_SD); input CLK_125MHZ_FPGA; input [3:0]BUTTONS; input [1:0]SWITCHES; output [5:0]LEDS; input FPGA_SERIAL_RX; output FPGA_SERIAL_TX; output AUD_PWM; output AUD_SD; wire \<const0> ; wire \<const1> ; wire AUD_PWM; wire AUD_SD; wire [3:0]BUTTONS; wire [0:0]BUTTONS_IBUF; wire CLK_125MHZ_FPGA; wire CLK_125MHZ_FPGA_IBUF; wire FPGA_SERIAL_RX; wire FPGA_SERIAL_RX_IBUF; wire FPGA_SERIAL_TX; wire FPGA_SERIAL_TX_OBUF; wire [5:0]LEDS; wire [1:0]SWITCHES; wire [0:0]SWITCHES_IBUF; wire buttons_pressed; wire cpu_clk; wire cpu_clk_locked; wire cpu_reset; wire cpu_tx; wire fpga_serial_rx_iob; OBUF AUD_PWM_OBUF_inst (.I(\<const0> ), .O(AUD_PWM)); OBUF AUD_SD_OBUF_inst (.I(\<const1> ), .O(AUD_SD)); IBUF \BUTTONS_IBUF[0]_inst (.I(BUTTONS[0]), .O(BUTTONS_IBUF)); IBUF CLK_125MHZ_FPGA_IBUF_inst (.I(CLK_125MHZ_FPGA), .O(CLK_125MHZ_FPGA_IBUF)); IBUF FPGA_SERIAL_RX_IBUF_inst (.I(FPGA_SERIAL_RX), .O(FPGA_SERIAL_RX_IBUF)); OBUF FPGA_SERIAL_TX_OBUF_inst (.I(FPGA_SERIAL_TX_OBUF), .O(FPGA_SERIAL_TX)); GND GND (.G(\<const0> )); OBUFT \LEDS_OBUF[0]_inst (.I(\<const0> ), .O(LEDS[0]), .T(\<const1> )); OBUFT \LEDS_OBUF[1]_inst (.I(\<const0> ), .O(LEDS[1]), .T(\<const1> )); OBUFT \LEDS_OBUF[2]_inst (.I(\<const0> ), .O(LEDS[2]), .T(\<const1> )); OBUFT \LEDS_OBUF[3]_inst (.I(\<const0> ), .O(LEDS[3]), .T(\<const1> )); OBUFT \LEDS_OBUF[4]_inst (.I(\<const0> ), .O(LEDS[4]), .T(\<const1> )); OBUFT \LEDS_OBUF[5]_inst (.I(\<const0> ), .O(LEDS[5]), .T(\<const1> )); IBUF \SWITCHES_IBUF[0]_inst (.I(SWITCHES[0]), .O(SWITCHES_IBUF)); VCC VCC (.P(\<const1> )); button_parser bp (.BUTTONS_IBUF(BUTTONS_IBUF), .buttons_pressed(buttons_pressed), .cpu_clk(cpu_clk), .cpu_clk_locked(cpu_clk_locked), .cpu_reset(cpu_reset)); clocks clk_gen (.clk_125mhz(CLK_125MHZ_FPGA_IBUF), .cpu_clk(cpu_clk), .cpu_clk_locked(cpu_clk_locked)); cpu cpu (.SWITCHES_IBUF(SWITCHES_IBUF), .buttons_pressed(buttons_pressed), .cpu_clk(cpu_clk), .cpu_clk_locked(cpu_clk_locked), .cpu_reset(cpu_reset), .serial_in(fpga_serial_rx_iob), .serial_out(cpu_tx)); (* IOB = "TRUE" *) FDRE fpga_serial_rx_iob_reg (.C(cpu_clk), .CE(\<const1> ), .D(FPGA_SERIAL_RX_IBUF), .Q(fpga_serial_rx_iob), .R(\<const0> )); (* IOB = "TRUE" *) FDRE fpga_serial_tx_iob_reg (.C(cpu_clk), .CE(\<const1> ), .D(cpu_tx), .Q(FPGA_SERIAL_TX_OBUF), .R(\<const0> )); endmodule