****** Vivado v2021.1 (64-bit)
**** SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
**** IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/scripts/synth.tcl
# source ../target.tcl
## set ABS_TOP /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware
## set TOP z1top
## set FPGA_PART xc7z020clg400-1
## set_param general.maxThreads 4
## set_param general.maxBackupLogs 0
## set RTL { /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/EECS151.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/clocks.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/button_parser.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/debouncer.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/edge_detector.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/fifo.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/dmem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/imem.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/imm_gen.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/reg_file.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/branch_predictor.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cmb_ctrl_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/pipeline.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.v }
## set CONSTRAINTS { /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.xdc }
# if {[string trim ${RTL}] ne ""} {
# read_verilog -sv ${RTL}
# }
# if {[string trim ${CONSTRAINTS}] ne ""} {
# read_xdc ${CONSTRAINTS}
# }
# synth_design -verilog_define SYNTHESIS -verilog_define ABS_TOP=${ABS_TOP} -top ${TOP} -part ${FPGA_PART} -include_dirs ${ABS_TOP}/src/riscv_core
Command: synth_design -verilog_define SYNTHESIS -verilog_define ABS_TOP=/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware -top z1top -part xc7z020clg400-1 -include_dirs /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 17618
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Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2562.727 ; gain = 0.000 ; free physical = 2274 ; free virtual = 12135
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INFO: [Synth 8-6157] synthesizing module 'z1top' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.v:1]
INFO: [Synth 8-6157] synthesizing module 'synchronizer' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v:1]
INFO: [Synth 8-6155] done synthesizing module 'synchronizer' (1#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v:1]
INFO: [Synth 8-6157] synthesizing module 'clocks' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/clocks.v:1]
Parameter CPU_CLK_CLKFBOUT_MULT bound to: 34 - type: integer
Parameter CPU_CLK_DIVCLK_DIVIDE bound to: 5 - type: integer
Parameter CPU_CLK_CLKOUT_DIVIDE bound to: 17 - type: integer
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/share/instsww/xilinx/Vivado/2021.1/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (2#1) [/share/instsww/xilinx/Vivado/2021.1/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/share/instsww/xilinx/Vivado/2021.1/scripts/rt/data/unisim_comp.v:84453]
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
Parameter CLKFBOUT_MULT bound to: 34 - type: integer
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double
Parameter CLKOUT0_DIVIDE bound to: 17 - type: integer
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
Parameter COMPENSATION bound to: BUF_IN - type: string
Parameter DIVCLK_DIVIDE bound to: 5 - type: integer
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (3#1) [/share/instsww/xilinx/Vivado/2021.1/scripts/rt/data/unisim_comp.v:84453]
INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV__parameterized0' [/share/instsww/xilinx/Vivado/2021.1/scripts/rt/data/unisim_comp.v:84453]
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
Parameter CLKFBOUT_MULT bound to: 36 - type: integer
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
Parameter CLKIN1_PERIOD bound to: 8.000000 - type: double
Parameter CLKOUT0_DIVIDE bound to: 6 - type: integer
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
Parameter COMPENSATION bound to: BUF_IN - type: string
Parameter DIVCLK_DIVIDE bound to: 5 - type: integer
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV__parameterized0' (3#1) [/share/instsww/xilinx/Vivado/2021.1/scripts/rt/data/unisim_comp.v:84453]
INFO: [Synth 8-6155] done synthesizing module 'clocks' (4#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/clocks.v:1]
INFO: [Synth 8-6157] synthesizing module 'button_parser' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/button_parser.v:3]
Parameter WIDTH bound to: 4 - type: integer
Parameter SAMPLE_CNT_MAX bound to: 25000 - type: integer
Parameter PULSE_CNT_MAX bound to: 200 - type: integer
INFO: [Synth 8-6157] synthesizing module 'synchronizer__parameterized0' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v:1]
Parameter WIDTH bound to: 4 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'synchronizer__parameterized0' (4#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v:1]
INFO: [Synth 8-6157] synthesizing module 'debouncer' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/debouncer.v:2]
Parameter WIDTH bound to: 4 - type: integer
Parameter SAMPLE_CNT_MAX bound to: 25000 - type: integer
Parameter PULSE_CNT_MAX bound to: 200 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'debouncer' (5#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/debouncer.v:2]
INFO: [Synth 8-6157] synthesizing module 'edge_detector' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/edge_detector.v:1]
Parameter WIDTH bound to: 4 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'edge_detector' (6#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/edge_detector.v:1]
INFO: [Synth 8-6155] done synthesizing module 'button_parser' (7#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/button_parser.v:3]
INFO: [Synth 8-6157] synthesizing module 'cpu' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v:3]
Parameter CPU_CLOCK_FREQ bound to: 50000000 - type: integer
Parameter RESET_PC bound to: 1073741824 - type: integer
Parameter BAUD_RATE bound to: 115200 - type: integer
INFO: [Synth 8-6157] synthesizing module 'bios_mem' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v:1]
INFO: [Synth 8-3876] $readmem data file '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/bios/bios.hex' is read successfully [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v:27]
INFO: [Synth 8-6155] done synthesizing module 'bios_mem' (8#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v:1]
INFO: [Synth 8-6157] synthesizing module 'dmem' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/dmem.v:1]
INFO: [Synth 8-6155] done synthesizing module 'dmem' (9#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/dmem.v:1]
INFO: [Synth 8-6157] synthesizing module 'imem' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/imem.v:1]
INFO: [Synth 8-6155] done synthesizing module 'imem' (10#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/imem.v:1]
INFO: [Synth 8-6157] synthesizing module 'reg_file' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/reg_file.v:1]
INFO: [Synth 8-6155] done synthesizing module 'reg_file' (11#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/reg_file.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart.v:1]
Parameter CLOCK_FREQ bound to: 50000000 - type: integer
Parameter BAUD_RATE bound to: 115200 - type: integer
INFO: [Synth 8-6157] synthesizing module 'uart_transmitter' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v:1]
Parameter CLOCK_FREQ bound to: 50000000 - type: integer
Parameter BAUD_RATE bound to: 115200 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_transmitter' (12#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_receiver' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v:1]
Parameter CLOCK_FREQ bound to: 50000000 - type: integer
Parameter BAUD_RATE bound to: 115200 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'uart_receiver' (13#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v:1]
INFO: [Synth 8-6155] done synthesizing module 'uart' (14#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'branch_predictor' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/branch_predictor.v:11]
INFO: [Synth 8-6157] synthesizing module 'bp_cache' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v:8]
Parameter AWIDTH bound to: 30 - type: integer
Parameter DWIDTH bound to: 2 - type: integer
Parameter LINES bound to: 8 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'bp_cache' (15#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v:8]
INFO: [Synth 8-6157] synthesizing module 'sat_updn' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v:6]
Parameter WIDTH bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sat_updn' (16#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v:6]
INFO: [Synth 8-6155] done synthesizing module 'branch_predictor' (17#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/branch_predictor.v:11]
INFO: [Synth 8-6157] synthesizing module 'immediate_gen' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/imm_gen.v:20]
INFO: [Synth 8-6155] done synthesizing module 'immediate_gen' (18#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/imm_gen.v:20]
INFO: [Synth 8-6157] synthesizing module 'exec_mem_ctrl' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v:39]
INFO: [Synth 8-6155] done synthesizing module 'exec_mem_ctrl' (19#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v:39]
INFO: [Synth 8-6157] synthesizing module 'forwarding' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v:77]
INFO: [Synth 8-6155] done synthesizing module 'forwarding' (20#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v:77]
INFO: [Synth 8-6157] synthesizing module 'alu' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v:3]
INFO: [Synth 8-6155] done synthesizing module 'alu' (21#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v:3]
INFO: [Synth 8-6157] synthesizing module 'branch_comp' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v:1]
INFO: [Synth 8-6155] done synthesizing module 'branch_comp' (22#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v:1]
INFO: [Synth 8-6157] synthesizing module 'store_data' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v:3]
INFO: [Synth 8-6155] done synthesizing module 'store_data' (23#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v:3]
INFO: [Synth 8-6157] synthesizing module 'csr_ctrl' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v:135]
INFO: [Synth 8-6155] done synthesizing module 'csr_ctrl' (24#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v:135]
INFO: [Synth 8-6157] synthesizing module 'writeback_ctrl' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v:100]
INFO: [Synth 8-6155] done synthesizing module 'writeback_ctrl' (25#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v:100]
INFO: [Synth 8-6157] synthesizing module 'load_data' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v:25]
INFO: [Synth 8-6155] done synthesizing module 'load_data' (26#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v:25]
INFO: [Synth 8-6157] synthesizing module 'branch_ctrl' [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v:3]
INFO: [Synth 8-6155] done synthesizing module 'branch_ctrl' (27#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v:3]
INFO: [Synth 8-6155] done synthesizing module 'cpu' (28#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v:3]
INFO: [Synth 8-6155] done synthesizing module 'z1top' (29#1) [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.v:1]
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Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2562.727 ; gain = 0.000 ; free physical = 3140 ; free virtual = 13005
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2562.727 ; gain = 0.000 ; free physical = 3147 ; free virtual = 13011
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2562.727 ; gain = 0.000 ; free physical = 3147 ; free virtual = 13012
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Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2562.727 ; gain = 0.000 ; free physical = 3137 ; free virtual = 13002
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.xdc]
Finished Parsing XDC File [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/z1top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/z1top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
INFO: [Timing 38-2] Deriving generated clocks
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2594.582 ; gain = 0.000 ; free physical = 3047 ; free virtual = 12908
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2594.582 ; gain = 0.000 ; free physical = 3047 ; free virtual = 12908
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2594.586 ; gain = 31.859 ; free physical = 3135 ; free virtual = 12997
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg400-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2594.586 ; gain = 31.859 ; free physical = 3136 ; free virtual = 12998
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2594.586 ; gain = 31.859 ; free physical = 3136 ; free virtual = 12998
---------------------------------------------------------------------------------
WARNING: [Synth 8-6841] Block RAM (mem_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
(address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
WARNING: [Synth 8-6841] Block RAM (mem_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
(address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2594.594 ; gain = 31.867 ; free physical = 3125 ; free virtual = 12987
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 4
3 Input 32 Bit Adders := 1
2 Input 10 Bit Adders := 4
2 Input 9 Bit Adders := 2
2 Input 4 Bit Adders := 2
3 Input 2 Bit Adders := 1
+---XORs :
2 Input 32 Bit XORs := 1
2 Input 1 Bit XORs := 1
+---Registers :
32 Bit Registers := 15
10 Bit Registers := 6
9 Bit Registers := 2
8 Bit Registers := 1
4 Bit Registers := 6
1 Bit Registers := 11
+---RAMs :
512K Bit (16384 X 32 bit) RAMs := 2
216 Bit (8 X 27 bit) RAMs := 1
16 Bit (8 X 2 bit) RAMs := 1
+---ROMs :
ROMs := 2
+---Muxes :
2 Input 32 Bit Muxes := 42
4 Input 32 Bit Muxes := 2
6 Input 32 Bit Muxes := 1
3 Input 32 Bit Muxes := 1
7 Input 32 Bit Muxes := 1
2 Input 10 Bit Muxes := 1
2 Input 8 Bit Muxes := 3
2 Input 4 Bit Muxes := 6
4 Input 4 Bit Muxes := 2
3 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 2
6 Input 3 Bit Muxes := 2
7 Input 3 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
8 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 8
3 Input 1 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-6841] Block RAM (mem_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
(address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
WARNING: [Synth 8-6841] Block RAM (mem_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
(address width (14) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2594.594 ; gain = 31.867 ; free physical = 3104 ; free virtual = 12972
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------+--------------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+--------------------+---------------+----------------+
|cpu | bios_mem/douta_reg | 2048x32 | Block RAM |
|cpu | bios_mem/doutb_reg | 2048x32 | Block RAM |
+------------+--------------------+---------------+----------------+
Block RAM: Preliminary Mapping Report (see note below)
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|cpu/dmem | mem_reg | 16 K x 32(READ_FIRST) | W | R | | | | Port A | 0 | 16 |
|cpu/imem | mem_reg | 16 K x 32(READ_FIRST) | W | | 16 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 16 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+----------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+----------------+-----------+----------------------+----------------+
|cpu/rf | mem_reg | Implied | 32 x 32 | RAM32M x 12 |
|cpu/br_pred | cache/data_reg | Implied | 8 x 2 | RAM16X1D x 2 |
|cpu/br_pred | cache/tag_reg | Implied | 8 x 27 | RAM16X1D x 27 |
+------------+----------------+-----------+----------------------+----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2594.594 ; gain = 31.867 ; free physical = 2973 ; free virtual = 12841
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2594.594 ; gain = 31.867 ; free physical = 2926 ; free virtual = 12783
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Block RAM: Final Mapping Report
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|cpu/dmem | mem_reg | 16 K x 32(READ_FIRST) | W | R | | | | Port A | 0 | 16 |
|cpu/imem | mem_reg | 16 K x 32(READ_FIRST) | W | | 16 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 16 |
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Distributed RAM: Final Mapping Report
+------------+----------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+----------------+-----------+----------------------+----------------+
|cpu/rf | mem_reg | Implied | 32 x 32 | RAM32M x 12 |
|cpu/br_pred | cache/data_reg | Implied | 8 x 2 | RAM16X1D x 2 |
|cpu/br_pred | cache/tag_reg | Implied | 8 x 27 | RAM16X1D x 27 |
+------------+----------------+-----------+----------------------+----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_0_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_0_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_0_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_0_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_2_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_2_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_2_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_2_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/dmem/mem_reg_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_0_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_0_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_0_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_0_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_2_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_2_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_2_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_2_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/imem/mem_reg_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/bios_mem/douta_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/bios_mem/douta_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/bios_mem/douta_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance cpu/bios_mem/douta_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2610.594 ; gain = 47.867 ; free physical = 2909 ; free virtual = 12780
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
INFO: [Synth 8-4163] Replicating register fpga_serial_rx_iob_reg to handle IOB=TRUE attribute
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 2619.504 ; gain = 56.777 ; free physical = 2915 ; free virtual = 12785
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 2619.504 ; gain = 56.777 ; free physical = 2927 ; free virtual = 12783
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 2619.504 ; gain = 56.777 ; free physical = 2926 ; free virtual = 12783
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 2619.504 ; gain = 56.777 ; free physical = 2926 ; free virtual = 12782
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:53 . Memory (MB): peak = 2619.504 ; gain = 56.777 ; free physical = 2925 ; free virtual = 12782
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:53 . Memory (MB): peak = 2619.504 ; gain = 56.777 ; free physical = 2926 ; free virtual = 12783
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 4|
|2 |CARRY4 | 104|
|3 |LUT1 | 11|
|4 |LUT2 | 128|
|5 |LUT3 | 185|
|6 |LUT4 | 297|
|7 |LUT5 | 269|
|8 |LUT6 | 740|
|9 |PLLE2_ADV | 2|
|11 |RAM16X1D | 29|
|12 |RAM32M | 10|
|13 |RAM32X1D | 4|
|14 |RAMB36E1 | 34|
|18 |FDRE | 543|
|19 |FDSE | 2|
|20 |IBUF | 4|
|21 |OBUF | 3|
|22 |OBUFT | 6|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:53 . Memory (MB): peak = 2619.504 ; gain = 56.777 ; free physical = 2926 ; free virtual = 12783
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 4 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:48 ; elapsed = 00:00:50 . Memory (MB): peak = 2619.504 ; gain = 24.922 ; free physical = 2962 ; free virtual = 12834
Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:53 . Memory (MB): peak = 2619.508 ; gain = 56.777 ; free physical = 2963 ; free virtual = 12835
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2619.508 ; gain = 0.000 ; free physical = 3026 ; free virtual = 12898
INFO: [Netlist 29-17] Analyzing 183 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.xdc]
Finished Parsing XDC File [/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2625.441 ; gain = 0.000 ; free physical = 2957 ; free virtual = 12828
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 43 instances were transformed.
RAM16X1D => RAM32X1D (RAMD32(x2)): 29 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 10 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete, checksum: 3f9460e6
INFO: [Common 17-83] Releasing license: Synthesis
118 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:05 ; elapsed = 00:01:02 . Memory (MB): peak = 2625.441 ; gain = 67.000 ; free physical = 3151 ; free virtual = 13022
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
# write_checkpoint -force ${TOP}.dcp
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2665.461 ; gain = 0.004 ; free physical = 3152 ; free virtual = 13024
INFO: [Common 17-1381] The checkpoint '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/build/synth/z1top.dcp' has been generated.
# report_timing_summary -file post_synth_timing_summary.rpt
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
# report_drc -file post_synth_drc.rpt
Command: report_drc -file post_synth_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/share/instsww/xilinx/Vivado/2021.1/data/ip'.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/build/synth/post_synth_drc.rpt.
report_drc completed successfully
# report_utilization -file post_synth_utilization.rpt
# write_verilog -force -file post_synth.v
# write_xdc -force -file post_synth.xdc
INFO: [Common 17-206] Exiting Vivado at Fri Dec 9 08:05:45 2022...