FPGA-RISC-V-CPU / hardware / sim / alu_tb.log
alu_tb.log
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Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06_Full64; Runtime version P-2019.06_Full64;  Nov 14 19:58 2022
Message: From $vcdpluson at time 0 in file alu_tb.v line 18: [VCD+-SVFN]: 
Setting VPD File by "+vpdfile+" switch to alu_tb.vpd.

VCD+ Writer P-2019.06_Full64 Copyright (c) 1991-2019 by Synopsys Inc.
a:          1, b:          2, ALUSel:  0, out:          3
a:          1, b:          2, ALUSel:  1, out:          4
a:          1, b:          2, ALUSel:  2, out:          1
a:          1, b:          2, ALUSel:  3, out:          1
a:          1, b:          2, ALUSel:  4, out:          3
a:          1, b:          2, ALUSel:  5, out:          0
a:          1, b:          2, ALUSel:  6, out:          3
a:          1, b:          2, ALUSel:  7, out:          0
a:          2, b:          1, ALUSel:  8, out:          1
a:          1, b:          2, ALUSel: 13, out:          0
a:          1, b:          2, ALUSel: 15, out:          2
PASSED!
$finish called from file "alu_tb.v", line 104.
$finish at simulation time                25000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 25000 ps
CPU Time:      0.400 seconds;       Data structure size:   0.0Mb
Mon Nov 14 19:58:14 2022