FPGA-RISC-V-CPU / hardware / sim / asm_tb.log
asm_tb.log
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Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06_Full64; Runtime version P-2019.06_Full64;  Dec  9 07:40 2022
Message: From $vcdpluson at time 0 in file asm_tb.v line 48: [VCD+-SVFN]: 
Setting VPD File by "+vpdfile+" switch to asm_tb.vpd.

VCD+ Writer P-2019.06_Full64 Copyright (c) 1991-2019 by Synopsys Inc.
PASS - test    1, got:        300 for reg  1
PASS - test    2, got:        500 for reg  1
PASS - test    3, got:        100 for reg  2
ALL ASSEMBLY TESTS PASSED!
$finish called from file "asm_tb.v", line 73.
$finish at simulation time               450000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 450000 ps
CPU Time:      0.350 seconds;       Data structure size:   0.1Mb
Fri Dec  9 07:40:06 2022