Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06_Full64; Runtime version P-2019.06_Full64; Dec 9 07:40 2022
Message: From $vcdpluson at time 0 in file bios_tb.v line 115: [VCD+-SVFN]:
Setting VPD File by "+vpdfile+" switch to bios_tb.vpd.
VCD+ Writer P-2019.06_Full64 Copyright (c) 1991-2019 by Synopsys Inc.
[TEST 1] BIOS startup. Expect to see: \r\n151>
[time 2270000, sim. cycle 103] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
[time 3390000, sim. cycle 159] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0a, expected 8'h0a == newline/CR [ PASSED ]
[time 4690000, sim. cycle 224] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 5810000, sim. cycle 280] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h35, expected 8'h35 == 5 [ PASSED ]
[time 6930000, sim. cycle 336] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 8050000, sim. cycle 392] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h3e, expected 8'h3e == > [ PASSED ]
[time 9170000, sim. cycle 448] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[TEST 2] Send an invalid command. Expect to see: \n\rUnrecognized token:
[time 10170000, sim. cycle 498] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 11850000, sim. cycle 582] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 17150000, sim. cycle 847] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h62
[time 18790000, sim. cycle 929] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h62, expected 8'h62 == b [ PASSED ]
[time 24130000, sim. cycle 1196] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h63
[time 25850000, sim. cycle 1282] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h63, expected 8'h63 == c [ PASSED ]
[time 31110000, sim. cycle 1545] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h64
[time 32790000, sim. cycle 1629] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h64, expected 8'h64 == d [ PASSED ]
[time 38090000, sim. cycle 1894] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h20
[time 39730000, sim. cycle 1976] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 47270000, sim. cycle 2353] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0a, expected 8'h0a == newline/CR [ PASSED ]
[time 48390000, sim. cycle 2409] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
[time 49510000, sim. cycle 2465] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h55, expected 8'h55 == U [ PASSED ]
[time 50630000, sim. cycle 2521] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6e, expected 8'h6e == n [ PASSED ]
[time 51750000, sim. cycle 2577] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h72, expected 8'h72 == r [ PASSED ]
[time 52870000, sim. cycle 2633] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h65, expected 8'h65 == e [ PASSED ]
[time 53990000, sim. cycle 2689] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h63, expected 8'h63 == c [ PASSED ]
[time 55110000, sim. cycle 2745] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6f, expected 8'h6f == o [ PASSED ]
[time 56230000, sim. cycle 2801] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h67, expected 8'h67 == g [ PASSED ]
[time 57350000, sim. cycle 2857] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6e, expected 8'h6e == n [ PASSED ]
[time 58470000, sim. cycle 2913] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h69, expected 8'h69 == i [ PASSED ]
[time 59590000, sim. cycle 2969] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h7a, expected 8'h7a == z [ PASSED ]
[time 60710000, sim. cycle 3025] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h65, expected 8'h65 == e [ PASSED ]
[time 61830000, sim. cycle 3081] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h64, expected 8'h64 == d [ PASSED ]
[time 62950000, sim. cycle 3137] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 64070000, sim. cycle 3193] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h74, expected 8'h74 == t [ PASSED ]
[time 65190000, sim. cycle 3249] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6f, expected 8'h6f == o [ PASSED ]
[time 66310000, sim. cycle 3305] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6b, expected 8'h6b == k [ PASSED ]
[time 67430000, sim. cycle 3361] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h65, expected 8'h65 == e [ PASSED ]
[time 68550000, sim. cycle 3417] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6e, expected 8'h6e == n [ PASSED ]
[time 69670000, sim. cycle 3473] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h3a, expected 8'h3a == : [ PASSED ]
[time 70790000, sim. cycle 3529] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 72070000, sim. cycle 3593] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 73190000, sim. cycle 3649] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h62, expected 8'h62 == b [ PASSED ]
[time 74310000, sim. cycle 3705] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h63, expected 8'h63 == c [ PASSED ]
[time 75430000, sim. cycle 3761] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h64, expected 8'h64 == d [ PASSED ]
[time 76730000, sim. cycle 3826] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0a, expected 8'h0a == newline/CR [ PASSED ]
[time 77850000, sim. cycle 3882] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
[time 79210000, sim. cycle 3950] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 80330000, sim. cycle 4006] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h35, expected 8'h35 == 5 [ PASSED ]
[time 81450000, sim. cycle 4062] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 82570000, sim. cycle 4118] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h3e, expected 8'h3e == > [ PASSED ]
[time 83690000, sim. cycle 4174] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[TEST 3] Send [sw cafeaaaa 30000004] command. Expect to write 32'hcafeaaaa to both IMem[1] and DMem[1]
[time 84690000, sim. cycle 4224] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h73
[time 86370000, sim. cycle 4308] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h73, expected 8'h73 == s [ PASSED ]
[time 91670000, sim. cycle 4573] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h77
[time 93310000, sim. cycle 4655] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h77, expected 8'h77 == w [ PASSED ]
[time 98650000, sim. cycle 4922] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h20
[time 100370000, sim. cycle 5008] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 105630000, sim. cycle 5271] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h63
[time 107910000, sim. cycle 5385] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h63, expected 8'h63 == c [ PASSED ]
[time 112610000, sim. cycle 5620] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 114250000, sim. cycle 5702] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 119590000, sim. cycle 5969] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h66
[time 121310000, sim. cycle 6055] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h66, expected 8'h66 == f [ PASSED ]
[time 126570000, sim. cycle 6318] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h65
[time 128250000, sim. cycle 6402] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h65, expected 8'h65 == e [ PASSED ]
[time 133550000, sim. cycle 6667] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 135190000, sim. cycle 6749] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 140530000, sim. cycle 7016] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 142250000, sim. cycle 7102] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 147510000, sim. cycle 7365] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 149190000, sim. cycle 7449] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 154490000, sim. cycle 7714] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 156130000, sim. cycle 7796] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 161470000, sim. cycle 8063] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h20
[time 163190000, sim. cycle 8149] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 168450000, sim. cycle 8412] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h33
[time 175430000, sim. cycle 8761] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 175990000, sim. cycle 8789] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h33, expected 8'h33 == 3 [ PASSED ]
[time 178370000, sim. cycle 8908] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 182410000, sim. cycle 9110] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 184110000, sim. cycle 9195] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 189390000, sim. cycle 9459] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 191050000, sim. cycle 9542] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 196370000, sim. cycle 9808] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 198110000, sim. cycle 9895] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 203350000, sim. cycle 10157] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 205050000, sim. cycle 10242] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 210330000, sim. cycle 10506] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 211990000, sim. cycle 10589] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 217310000, sim. cycle 10855] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h34
[time 219050000, sim. cycle 10942] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h34, expected 8'h34 == 4 [ PASSED ]
[time 224290000, sim. cycle 11204] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h0d
[time 226430000, sim. cycle 11311] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
[time 227550000, sim. cycle 11367] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0a, expected 8'h0a == newline/CR [ PASSED ]
[time 238910000, sim. cycle 11935] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 240030000, sim. cycle 11991] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h35, expected 8'h35 == 5 [ PASSED ]
[time 241150000, sim. cycle 12047] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 242270000, sim. cycle 12103] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h3e, expected 8'h3e == > [ PASSED ]
[time 243390000, sim. cycle 12159] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
Imem[1]=cafeaaaa DMem[1]=cafeaaaa
Test Write to IMem
PASSED!
Test Write to DMem
PASSED!
[TEST 4] Send [lw 30000004] command. Expect to see: 30000004:cafeaaaa
[time 244390000, sim. cycle 12209] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h6c
[time 246070000, sim. cycle 12293] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6c, expected 8'h6c == l [ PASSED ]
[time 251370000, sim. cycle 12558] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h77
[time 253010000, sim. cycle 12640] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h77, expected 8'h77 == w [ PASSED ]
[time 258350000, sim. cycle 12907] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h20
[time 260070000, sim. cycle 12993] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 265330000, sim. cycle 13256] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h33
[time 267070000, sim. cycle 13343] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h33, expected 8'h33 == 3 [ PASSED ]
[time 272310000, sim. cycle 13605] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 274010000, sim. cycle 13690] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 279290000, sim. cycle 13954] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 280950000, sim. cycle 14037] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 286270000, sim. cycle 14303] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 288010000, sim. cycle 14390] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 293250000, sim. cycle 14652] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 294950000, sim. cycle 14737] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 300230000, sim. cycle 15001] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 301890000, sim. cycle 15084] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 307210000, sim. cycle 15350] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 308950000, sim. cycle 15437] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 314190000, sim. cycle 15699] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h34
[time 315890000, sim. cycle 15784] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h34, expected 8'h34 == 4 [ PASSED ]
[time 321170000, sim. cycle 16048] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h0d
[time 323270000, sim. cycle 16153] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
[time 324390000, sim. cycle 16209] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0a, expected 8'h0a == newline/CR [ PASSED ]
[time 342250000, sim. cycle 17102] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h33, expected 8'h33 == 3 [ PASSED ]
[time 343370000, sim. cycle 17158] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 344490000, sim. cycle 17214] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 345610000, sim. cycle 17270] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 346730000, sim. cycle 17326] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 347850000, sim. cycle 17382] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 348970000, sim. cycle 17438] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 350090000, sim. cycle 17494] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h34, expected 8'h34 == 4 [ PASSED ]
[time 351390000, sim. cycle 17559] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h3a, expected 8'h3a == : [ PASSED ]
[time 359830000, sim. cycle 17981] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h63, expected 8'h63 == c [ PASSED ]
[time 360950000, sim. cycle 18037] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 362070000, sim. cycle 18093] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h66, expected 8'h66 == f [ PASSED ]
[time 363190000, sim. cycle 18149] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h65, expected 8'h65 == e [ PASSED ]
[time 364310000, sim. cycle 18205] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 365430000, sim. cycle 18261] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 366550000, sim. cycle 18317] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 367670000, sim. cycle 18373] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 368970000, sim. cycle 18438] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
[time 370090000, sim. cycle 18494] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0a, expected 8'h0a == newline/CR [ PASSED ]
[time 371450000, sim. cycle 18562] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 372570000, sim. cycle 18618] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h35, expected 8'h35 == 5 [ PASSED ]
[time 373690000, sim. cycle 18674] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 374810000, sim. cycle 18730] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h3e, expected 8'h3e == > [ PASSED ]
[time 375930000, sim. cycle 18786] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[TEST 5] Send [jal 10000000] command. Expect to see: jal 10000000
[time 376930000, sim. cycle 18836] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h6a
[time 378610000, sim. cycle 18920] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6a, expected 8'h6a == j [ PASSED ]
[time 383910000, sim. cycle 19185] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 385550000, sim. cycle 19267] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h61, expected 8'h61 == a [ PASSED ]
[time 390890000, sim. cycle 19534] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h6c
[time 392610000, sim. cycle 19620] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h6c, expected 8'h6c == l [ PASSED ]
[time 397870000, sim. cycle 19883] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h20
[time 399550000, sim. cycle 19967] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 == [ PASSED ]
[time 404850000, sim. cycle 20232] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h31
[time 406530000, sim. cycle 20316] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [ PASSED ]
[time 411830000, sim. cycle 20581] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 413470000, sim. cycle 20663] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 418810000, sim. cycle 20930] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 420530000, sim. cycle 21016] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 425790000, sim. cycle 21279] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 427470000, sim. cycle 21363] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 432770000, sim. cycle 21628] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 434410000, sim. cycle 21710] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 439750000, sim. cycle 21977] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 441470000, sim. cycle 22063] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 446730000, sim. cycle 22326] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 448410000, sim. cycle 22410] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 453710000, sim. cycle 22675] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h30
[time 455350000, sim. cycle 22757] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h30, expected 8'h30 == 0 [ PASSED ]
[time 460690000, sim. cycle 23024] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h0d
[time 462850000, sim. cycle 23132] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [ PASSED ]
Test RF: RF[3]=00000008
PASSED!
BIOS testbench done! Num failed tests: 0
$finish called from file "bios_tb.v", line 388.
$finish at simulation time 488670000
V C S S i m u l a t i o n R e p o r t
Time: 488670000 ps
CPU Time: 0.710 seconds; Data structure size: 0.3Mb
Fri Dec 9 07:40:36 2022