FPGA-RISC-V-CPU / hardware / sim / branch_comp_tb.log
branch_comp_tb.log
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Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06_Full64; Runtime version P-2019.06_Full64;  Nov 20 17:34 2022
Message: From $vcdpluson at time 0 in file branch_comp_tb.v line 20: [VCD+-SVFN]: 
Setting VPD File by "+vpdfile+" switch to branch_comp_tb.vpd.

VCD+ Writer P-2019.06_Full64 Copyright (c) 1991-2019 by Synopsys Inc.
PASSED!
$finish called from file "branch_comp_tb.v", line 91.
$finish at simulation time                16000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 16000 ps
CPU Time:      0.440 seconds;       Data structure size:   0.0Mb
Sun Nov 20 17:34:18 2022