FPGA-RISC-V-CPU / hardware / sim / branch_comp_tb.tb.daidir / simv.kdb
simv.kdb
Raw
rc file Version 1.0

[Design]
COMPILE_PATH=/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim
SystemC=FALSE
UUM=FALSE
KDB=FALSE
USE_NOVAS_HOME=FALSE
COSIM=FALSE
TOP=glbl branch_comp_tb 

[Value]
WREALX=ffff534e50535f58
WREALZ=ffff534e50535f5a