`timescale 1ns/1ns

module branch_comp_tb();
    reg [31:0] a;
    reg [31:0] b;
    reg BrUn;
    wire BrEq;
    wire BrLt;

    branch_comp comp(
        .a(a),
        .b(b),
        .BrUn(BrUn),
        .BrEq(BrEq),
        .BrLt(BrLt)
    );

    initial begin
        `ifndef IVERILOG
            $vcdpluson;
        `endif
        `ifdef IVERILOG
            $dumpfile("branch_comp_tb.fst");
            $dumpvars(0, branch_comp_tb);
        `endif

        // Unsigned Equal Comp
        // TODO
        a = 32'd1;
        b = 32'd1;
        BrUn = 1'b1;
        #(2)
        assert(BrEq == 1'b1) else $display("ERROR: %d", BrEq);
        assert(BrLt == 1'b0) else $display("ERROR: %d", BrLt);

        a = 32'd1;
        b = 32'd0;
        BrUn = 1'b1;
        #(2)
        assert(BrEq == 1'b0) else $display("ERROR: %d", BrEq);
        assert(BrLt == 1'b0) else $display("ERROR: %d", BrLt);

        // Unsigned Less than Comp
        // TODO
        a = 32'd1;
        b = 32'd0;
        BrUn = 1'b1;
        #(2)
        assert(BrEq == 1'b0) else $display("ERROR: %d", BrEq);
        assert(BrLt == 1'b0) else $display("ERROR: %d", BrLt);

        a = 32'd0;
        b = 32'd1;
        BrUn = 1'b1;
        #(2)
        assert(BrEq == 1'b0) else $display("ERROR: %d", BrEq);
        assert(BrLt == 1'b1) else $display("ERROR: %d", BrLt);
        
        // Singed Equal Comp
        // TODO
        a = 32'd1;
        b = 32'd1;
        BrUn = 1'b0;
        #(2)
        assert(BrEq == 1'b1) else $display("ERROR: %d", BrEq);
        assert(BrLt == 1'b0) else $display("ERROR: %d", BrLt);

        a = 32'd1;
        b = 32'd0;
        BrUn = 1'b0;
        #(2)
        assert(BrEq == 1'b0) else $display("ERROR: %d", BrEq);
        assert(BrLt == 1'b0) else $display("ERROR: %d", BrLt);
        // Singed Less than Comp
        // TODO
        a = 32'd1;
        b = 32'd0;
        BrUn = 1'b0;
        #(2)
        assert(BrEq == 1'b0) else $display("ERROR: %d", BrEq);
        assert(BrLt == 1'b0) else $display("ERROR: %d", BrLt);

        a = 32'd0;
        b = 32'd1;
        BrUn = 1'b0;
        #(2)
        assert(BrEq == 1'b0) else $display("ERROR: %d", BrEq);
        assert(BrLt == 1'b1) else $display("ERROR: %d", BrLt);

        $display("PASSED!");
        $finish();
    end
endmodule