FPGA-RISC-V-CPU / hardware / sim / branch_predictor_tb.log
branch_predictor_tb.log
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Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06_Full64; Runtime version P-2019.06_Full64;  Dec  9 05:52 2022
Message: From $vcdpluson at time 0 in file branch_predictor_tb.v line 95: [VCD+-SVFN]: 
Setting VPD File by "+vpdfile+" switch to branch_predictor_tb.vpd.

VCD+ Writer P-2019.06_Full64 Copyright (c) 1991-2019 by Synopsys Inc.
Testing branch prediction for PC address: 00000000
Testing branch prediction for PC address: 00000004
Testing branch prediction for PC address: 00000008
Testing branch prediction for PC address: 0000000c
Testing branch prediction for PC address: 00000010
Testing branch prediction for PC address: 00000014
Testing branch prediction for PC address: 00000018
Testing branch prediction for PC address: 0000001c
Testing branch prediction for PC address: 00000020
Testing branch prediction for PC address: 00000024
Testing branch prediction for PC address: 00000028
Testing branch prediction for PC address: 0000002c
Testing branch prediction for PC address: 00000030
Testing branch prediction for PC address: 00000034
Testing branch prediction for PC address: 00000038
Testing branch prediction for PC address: 0000003c
Testing branch prediction caching
All tests passed!
$finish called from file "branch_predictor_tb.v", line 124.
$finish at simulation time              1470000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 1470000 ps
CPU Time:      0.490 seconds;       Data structure size:   0.0Mb
Fri Dec  9 05:52:23 2022