FPGA-RISC-V-CPU / hardware / sim / branch_predictor_tb.tb.daidir / cc / cc_bcode.db
cc_bcode.db
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sid branch_predictor_tb
bcid 0 0 WIDTH,1 CALL_ARG_VAL,2,0 WIDTH,2 CALL_ARG_VAL,3,0 WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,2 OPT_CONST,2 OPT_CONST,1 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET
bcid 1 1 WIDTH,2 CALL_ARG_VAL,2,0 WIDTH,32 PAD WIDTH,1 CALL_ARG_VAL,3,0 WIDTH,2 CALL_ARG_VAL,2,0 WIDTH,32 PAD OPT_CONST,3 WIDTH,1 M_LT AND WIDTH,32 MULTI_CONCATENATE,1,32 OPT_CONST,1 AND WIDTH,1 CALL_ARG_VAL,4,0 WIDTH,2 CALL_ARG_VAL,2,0 OPT_CONST,0 WIDTH,1 M_GT AND WIDTH,32 MULTI_CONCATENATE,1,32 ADD ADD OPT_CONST,0 WIDTH,2 SLICE,1 RET