FPGA-RISC-V-CPU / hardware / sim / c_tests / cachetest.log
cachetest.log
Raw 
WARNING: ../c_tests_tb.v:50: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/cachetest/cachetest.hex): Not enough words in the file for the requested range [0:16383].
WARNING: ../c_tests_tb.v:51: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/cachetest/cachetest.hex): Not enough words in the file for the requested range [0:16383].
FST info: dumpfile cachetest.fst opened for output.
[     20475 sim. cycles] CSR test PASSED!
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