hardware/sim/c_tests/replace.log · FPGA-RISC-V-CPU

WARNING: ../c_tests_tb.v:50: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/replace/replace.hex): Not enough words in the file for the requested range [0:16383].
WARNING: ../c_tests_tb.v:51: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/c_tests/replace/replace.hex): Not enough words in the file for the requested range [0:16383].
FST info: dumpfile replace.fst opened for output.
[     13281 sim. cycles] CSR test PASSED!