FPGA-RISC-V-CPU / hardware / sim / cache_tb.tb.daidir / cc / cc_bcode.db
cc_bcode.db
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sid bp_cache
bcid 0 0 WIDTH,30 CALL_ARG_VAL,2,0 WIDTH,32 OPT_CONST,3 WIDTH,27 SLICE,1 WIDTH,30 CALL_ARG_VAL,3,0 WIDTH,32 OPT_CONST,3 WIDTH,27 SLICE,1 WIDTH,1 M_EQU CALL_ARG_VAL,4,0 AND RET