FPGA-RISC-V-CPU / hardware / sim / cmb_ctrl_logic_tb.log
cmb_ctrl_logic_tb.log
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Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06_Full64; Runtime version P-2019.06_Full64;  Nov 20 18:37 2022
Message: From $vcdpluson at time 0 in file cmb_ctrl_logic_tb.v line 41: [VCD+-SVFN]: 
Setting VPD File by "+vpdfile+" switch to cmb_ctrl_logic_tb.vpd.

VCD+ Writer P-2019.06_Full64 Copyright (c) 1991-2019 by Synopsys Inc.
pcsel: x
PASSED!
$finish called from file "cmb_ctrl_logic_tb.v", line 98.
$finish at simulation time                27000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 27000 ps
CPU Time:      0.420 seconds;       Data structure size:   0.0Mb
Sun Nov 20 18:37:38 2022