`timescale 1ns/1ns

module cmb_ctrl_logic_tb();
    reg [31:0] inst;
    reg BrEq;
    reg BrLt;
    wire PCSel;
    wire [2:0] ImmSel;
    wire BrUn;
    wire [1:0] ASel;
    wire [1:0] BSel;
    wire [3:0] ALUSel;
    wire [3:0] MemRW;
    wire [1:0] WBSel;
    wire RegWEn;
    wire CSRSel;
    wire CSRWEn;

    reg [20:0] expected;
    reg [20:0] actual;

    cmb_ctrl_logic ctrl (
      .inst(inst),
      .BrEq(BrEq),
      .BrLt(BrLt),
      .PCSel(PCSel),
      .ImmSel(ImmSel),
      .BrUn(BrUn),
      .ASel(ASel),
      .BSel(BSel),
      .ALUSel(ALUSel),
      .MemRW(MemRW),
      .WBSel(WBSel),
      .RegWEn(RegWEn),
      .CSRSel(CSRSel),
      .CSRWEn(CSRWEn)
    );

    initial begin
        `ifndef IVERILOG
            $vcdpluson;
        `endif
        `ifdef IVERILOG
            $dumpfile("cmb_ctrl_logic_tb.fst");
            $dumpvars(0, cmb_ctrl_logic);
        `endif

        // ADD - R type
        inst = {`FNC7_0, 5'd0, 5'd0, `FNC_ADD_SUB, 5'd3, `OPC_ARI_RTYPE};
        #(2)
        expected = {1'b0, 3'b000, 1'b0, 2'b00, 2'b00, 4'b0000, 4'b0000, 2'b01, 1'b1, 1'b0, 1'b0};
        actual = {PCSel, ImmSel, BrUn, ASel, BSel, ALUSel, MemRW, WBSel, RegWEn, CSRSel, CSRWEn};
        #(2)
        assert(expected == actual) else $display("Exp: %b\nGot: %b", expected, actual);

        // ADDI - I Type
        inst = {`FNC7_0, 5'd0, 5'd0, `FNC_ADD_SUB, 5'd3, `OPC_ARI_ITYPE};
        #(2)
        expected = {1'b0, 3'b000, 1'b0, 2'b00, 2'b01, 4'b0000, 4'b0000, 2'b01, 1'b1, 1'b0, 1'b0};
        actual = {PCSel, ImmSel, BrUn, ASel, BSel, ALUSel, MemRW, WBSel, RegWEn, CSRSel, CSRWEn};
        #(2)
        assert(expected == actual) else $display("Exp: %b\nGot: %b", expected, actual);

        // SB - S Type
        inst = {7'd0, 5'd0, 5'd0, `FNC_ADD_SUB, 5'd3, `OPC_STORE};
        #(2)
        expected = {1'b0, 3'b001, 1'b0, 2'b00, 2'b01, 4'b0000, 4'b0001, 2'b00, 1'b0, 1'b0, 1'b0};
        actual = {PCSel, ImmSel, BrUn, ASel, BSel, ALUSel, MemRW, WBSel, RegWEn, CSRSel, CSRWEn};
        #(2)
        assert(expected == actual) else $display("Exp: %b\nGot: %b", expected, actual);

        // BEQ - B Type
        inst = {7'd0, 5'd0, 5'd0, `FNC_ADD_SUB, 5'd3, `OPC_BRANCH};
        #(2)
        expected = {1'b1, 3'b010, 1'b0, 2'b01, 2'b01, 4'b0000, 4'b0000, 2'b00, 1'b0, 1'b0, 1'b0};
        actual = {PCSel, ImmSel, BrUn, ASel, BSel, ALUSel, MemRW, WBSel, RegWEn, CSRSel, CSRWEn};
        #(5)
        assert(expected == actual) else $display("Exp: %b\nGot: %b", expected, actual);

        // LUI - U Type
        inst = {20'd0, 5'd0, `OPC_LUI};
        #(2)
        expected = {1'b0, 3'b011, 1'b0, 2'b01, 2'b01, 4'b0000, 4'b0000, 2'b01, 1'b1, 1'b0, 1'b0};
        actual = {PCSel, ImmSel, BrUn, ASel, BSel, ALUSel, MemRW, WBSel, RegWEn, CSRSel, CSRWEn};
        #(2)
        assert(expected == actual) else $display("Exp: %b\nGot: %b", expected, actual);

        // JAL - J Type
        inst = {20'd0, 5'd0, `OPC_JAL};
        #(2)
        expected = {1'b0, 3'b100, 1'b0, 2'b01, 2'b01, 4'b0000, 4'b0000, 2'b10, 1'b1, 1'b0, 1'b0};
        actual = {PCSel, ImmSel, BrUn, ASel, BSel, ALUSel, MemRW, WBSel, RegWEn, CSRSel, CSRWEn};
        #(2)
        assert(expected == actual) else $display("Exp: %b\nGot: %b", expected, actual);

        $display("PASSED!");
        $finish();
    end
endmodule