FPGA-RISC-V-CPU / hardware / sim / csrc / Makefile.hsopt
Makefile.hsopt
Raw
# Makefile generated by VCS to build rmapats.so for your model
VSRC=..

# Override TARGET_ARCH
TARGET_ARCH=

# Select your favorite compiler

# Linux:
VCS_CC=gcc

# Internal CC for gen_c flow:
CC_CG=gcc

# User overrode default CC: 
VCS_CC=gcc
# Loader
LD=g++
# Loader Flags
LDFLAGS=

# Default defines
SHELL=/bin/sh

VCSTMPSPECARG=
VCSTMPSPECENV=
# NOTE: if you have little space in $TMPDIR, but plenty in /foo,
#and you are using gcc, uncomment the next line
#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo

TMPSPECARG=$(VCSTMPSPECARG)
TMPSPECENV=$(VCSTMPSPECENV)
CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)

# C flags for compilation
CFLAGS=-w  -pipe -fPIC -O -I/share/instsww/synopsys-new/vcs/P-2019.06/include    

CFLAGS_CG=-w  -pipe -fPIC -I/share/instsww/synopsys-new/vcs/P-2019.06/include -O  -fno-strict-aliasing   

ASFLAGS=
LIBS=

include filelist.hsopt


rmapats.so: $(HSOPT_OBJS)
	@$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../bios_tb.tb.daidir/rmapats.so $(HSOPT_OBJS)