`timescale 1ns/1ns

module ctrl_logic_tb();
    reg [31:0] inst;
    reg BrEq, BrLt;
    wire PCSel;
    wire [2:0] ImmSel;
    wire BrUn;
    wire ASel;
    wire BSel;
    wire [3:0] ALUSel;
    wire MemRW;
    wire RegWen
    wire [1:0] WBSel;
    wire CSRSel;
    wire CSRWen;

    ctrl_logic ctrl_logic(
        .inst(inst),
        .BrEQ(BrEq),
        .BrLt(BrLt),
        .PCSel(PCSel),
        .ImmSel(ImmSel),
        .BrUn(BrUn),
        .ASel(ASel),
        .BSel(BSel),
        .ALUSel(ALUSel),
        .MemRW(MemRW),
        .RegWen(RegWen),
        .CSRSel(CSRSel),
        .CSRWen(CSRWen)
    );

    initial begin
        `ifndef IVERILOG
            $vcdpluson;
        `endif
        `ifdef IVERILOG
            $dumpfile("ctrl_logic_tb.fst");
            $dumpvars(0, ctrl_logic_tb);
        `endif

        // Test R-TYPE inst(s)

        // Test I-TYPE imm inst(s)

        // Test Load inst(s)

        // Test Store inst(s)

        // Test Branch inst(s)

        // Test LUI inst

        // Test AUIPC inst

        // Test JAL inst

        // Test JALR inst

        $display("PASSED!");
        $finish();
    end
endmodule