Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06_Full64; Runtime version P-2019.06_Full64; Dec 9 07:40 2022
Message: From $vcdpluson at time 0 in file echo_tb.v line 107: [VCD+-SVFN]:
Setting VPD File by "+vpdfile+" switch to echo_tb.vpd.
VCD+ Writer P-2019.06_Full64 Copyright (c) 1991-2019 by Synopsys Inc.
[time 10390000, sim. cycle 509] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h61
[time 20810000, sim. cycle 1030] [Host (tb) <-- FPGA_SERIAL_TX] Got char: start_bit=0, payload=8'h61, stop_bit=1
[time 22370000, sim. cycle 1108] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h62
[time 32750000, sim. cycle 1627] [Host (tb) <-- FPGA_SERIAL_TX] Got char: start_bit=0, payload=8'h62, stop_bit=1
[time 34350000, sim. cycle 1707] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h63
[time 44690000, sim. cycle 2224] [Host (tb) <-- FPGA_SERIAL_TX] Got char: start_bit=0, payload=8'h63, stop_bit=1
[time 46330000, sim. cycle 2306] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h64
[time 56750000, sim. cycle 2827] [Host (tb) <-- FPGA_SERIAL_TX] Got char: start_bit=0, payload=8'h64, stop_bit=1
[time 58310000, sim. cycle 2905] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h65
[time 68690000, sim. cycle 3424] [Host (tb) <-- FPGA_SERIAL_TX] Got char: start_bit=0, payload=8'h65, stop_bit=1
[time 70290000, sim. cycle 3504] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h66
[time 80630000, sim. cycle 4021] [Host (tb) <-- FPGA_SERIAL_TX] Got char: start_bit=0, payload=8'h66, stop_bit=1
[time 82270000, sim. cycle 4103] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h67
[time 92690000, sim. cycle 4624] [Host (tb) <-- FPGA_SERIAL_TX] Got char: start_bit=0, payload=8'h67, stop_bit=1
[time 94250000, sim. cycle 4702] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h68
[time 104630000, sim. cycle 5221] [Host (tb) <-- FPGA_SERIAL_TX] Got char: start_bit=0, payload=8'h68, stop_bit=1
[time 106230000, sim. cycle 5301] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h69
[time 116570000, sim. cycle 5818] [Host (tb) <-- FPGA_SERIAL_TX] Got char: start_bit=0, payload=8'h69, stop_bit=1
[time 118210000, sim. cycle 5900] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h6a
[time 128630000, sim. cycle 6421] [Host (tb) <-- FPGA_SERIAL_TX] Got char: start_bit=0, payload=8'h6a, stop_bit=1
Test passed!
$finish called from file "echo_tb.v", line 148.
$finish at simulation time 128630000
V C S S i m u l a t i o n R e p o r t
Time: 128630000 ps
CPU Time: 0.460 seconds; Data structure size: 0.3Mb
Fri Dec 9 07:40:28 2022