`timescale 1ns/1ns

`include "../src/riscv_core/opcode.vh"

module forward_logic_tb();
    reg [31:0] f_inst, ex_inst;
    reg [31:0] rd1, rd2;
    reg [31:0] alu_out, mem_data;
    wire [31:0] fwd_outa, fwd_outb;

    forward_logic fwd (
        .f_inst(f_inst),
        .ex_inst(ex_inst),
        .rd1(rd1),
        .rd2(rd2),
        .alu_out(alu_out),
        .mem_data(wb_mux),
        .fwd_outa(fwd_outa),
        .fwd_outb(fwd_outb)
    );

    reg [4:0] f_rs1, f_rs2, f_rd;
    reg [4:0] ex_rs1, ex_rs2, ex_rd;

    initial begin
        `ifndef IVERILOG
            $vcdpluson;
        `endif
        `ifdef IVERILOG
            $dumpfile("forward_logic_tb.fst");
            $dumpvars(0, forward_logic_tb);
        `endif
        
        // ALU to ALU Fowarding
        f_inst  = {`FNC7_0,  f_rs1,  f_rs2, `FNC_ADD_SUB,  f_rd, `OPC_ARI_RTYPE};
        ex_inst = {`FNC7_0, ex_rs1, ex_rs2, `FNC_ADD_SUB, ex_Rd, `OPC_ARI_RTYPE};


        $display("PASSED!");
        $finish();
    end
endmodule