FPGA-RISC-V-CPU / hardware / sim / imm_gen_tb.log
imm_gen_tb.log
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Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06_Full64; Runtime version P-2019.06_Full64;  Nov 14 19:29 2022
Message: From $vcdpluson at time 0 in file imm_gen_tb.v line 16: [VCD+-SVFN]: 
Setting VPD File by "+vpdfile+" switch to imm_gen_tb.vpd.

VCD+ Writer P-2019.06_Full64 Copyright (c) 1991-2019 by Synopsys Inc.
imm_gen: inst=c0000000 ImmSel=0 imm=fffffc00
imm_gen: inst=00118223 ImmSel=1 imm=00000004
imm_gen: inst=0020d863 ImmSel=2 imm=00000010
U-type:       8
imm_gen: inst=00008097 ImmSel=3 imm=00008000
imm_gen: inst=0080016f ImmSel=4 imm=00000008
imm_gen: inst=00000000 ImmSel=5 imm=00000000
PASSED!
$finish called from file "imm_gen_tb.v", line 65.
$finish at simulation time                12000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 12000 ps
CPU Time:      0.370 seconds;       Data structure size:   0.0Mb
Mon Nov 14 19:29:37 2022