FPGA-RISC-V-CPU / hardware / sim / imm_gen_tb.tb.daidir / cc / cc_bcode.db
cc_bcode.db
Raw
sid imm_gen_tb
bcid 0 0 WIDTH,3 OPT_CONST,0 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,21 MULTI_CONCATENATE,1,21 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,20 WIDTH,11 SLICE,1 WIDTH,32 CONCATENATE,2 WIDTH,3 OPT_CONST,1 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,21 MULTI_CONCATENATE,1,21 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,25 WIDTH,6 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,7 WIDTH,5 SLICE,1 WIDTH,32 CONCATENATE,3 WIDTH,3 OPT_CONST,2 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,20 MULTI_CONCATENATE,1,20 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,7 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,25 WIDTH,6 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,8 WIDTH,4 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,32 CONCATENATE,5 WIDTH,3 OPT_CONST,3 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,12 WIDTH,20 SLICE,1 WIDTH,12 OPT_CONST,0 WIDTH,32 CONCATENATE,2 WIDTH,3 OPT_CONST,4 CALL_ARG_VAL,2,0 WIDTH,1 EQU WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,31 WIDTH,1 SLICE,1 WIDTH,11 MULTI_CONCATENATE,1,11 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,12 WIDTH,8 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,20 WIDTH,1 SLICE,1 WIDTH,32 CALL_ARG_VAL,3,0 OPT_CONST,21 WIDTH,10 SLICE,1 WIDTH,1 OPT_CONST,0 WIDTH,31 CONCATENATE,5 WIDTH,32 PAD OPT_CONST,0 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 MITECONDNOINSTR,4 RET