`timescale 1ns/1ns

module imm_gen_tb();
    reg [31:0] inst;
    reg [2:0] ImmSel;
    wire [31:0] imm;

    imm_gen gen(
        .inst(inst),
        .ImmSel(ImmSel),
        .imm(imm)
    );

    initial begin
        `ifndef IVERILOG
            $vcdpluson;
        `endif
        `ifdef IVERILOG
            $dumpfile("imm_gen_tb.fst");
            $dumpvars(0, imm_gen_tb);
        `endif

        // Test I-Type
        inst = 32'b1100_0000_0000_0000_0000_0000_0000_0000;
        ImmSel = 3'b000;
        #(2)
        assert(imm == 32'b1111_1111_1111_1111_1111_1100_0000_0000) else $display("ERROR: %d", imm);
        
        // Test S-Type
        // TODO: Make test
        inst = 32'b0000_0000_0001_0001_1000_0010_0010_0011;
        ImmSel = 3'b001;
        #(2)
        assert(imm == 32'd4) else $display("ERROR: %d", imm);

        // Test SB-Type
        // TODO: Make test
        inst = 32'h0020d863;
        ImmSel = 3'b010;
        #(2)
        assert(imm == 32'd16) else $display("ERROR: %d", imm);

        // Test U-Type
        // TODO: Make test
        inst = 32'b0000_0000_0000_0000_1000_0000_1001_0111;
        ImmSel = 3'b011;
        #(2)
        assert(imm == 32'd8 << 12) else $display("ERROR: %d", imm);
        
        // Test UJ-Type
        // TODO: Make test
        inst = 32'b0000_0000_1000_0000_0000_0001_0110_1111;
        ImmSel = 3'b100;
        #(2)
        assert(imm == 32'd8) else $display("ERROR: %d", imm);
        
        // Test Error
        // TODO: Make test
        inst = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
        ImmSel = 3'b101;
        #(2)
        assert(imm == 32'd0) else $display("ERROR: %d", imm);

        $display("PASSED!");
        $finish();
    end
endmodule