FPGA-RISC-V-CPU / hardware / sim / isa / sub.log
sub.log
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WARNING: ../isa_tb.v:45: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/riscv-isa-tests/sub.hex): Not enough words in the file for the requested range [0:16383].
WARNING: ../isa_tb.v:46: $readmemh(/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/../software/riscv-isa-tests/sub.hex): Not enough words in the file for the requested range [0:16383].
FST info: dumpfile sub.fst opened for output.
[passed] - sub in        455 simulation cycles