#!/bin/sh -e
# This file is automatically generated by VCS.  Any changes you make
# to it will be overwritten the next time VCS is run.
vcs '-full64' '-notice' '-line' '+lint=all,noVCDE,noNS,noSVA-UA' '-sverilog' '-timescale=1ns/10ps' '-debug' '+define+ABS_TOP=/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware' '+incdir+/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core' '-o' 'mmio_counter_tb.tb' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/EECS151.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/clocks.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/button_parser.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/debouncer.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/edge_detector.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/fifo.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/synchronizer.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_receiver.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/io_circuits/uart_transmitter.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/bios_mem.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/dmem.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/memories/imem.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/alu.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_comp.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/ctrl_logic.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/imm_gen.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/reg_file.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/bp_cache.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/branch_predictor.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/branch_prediction/sat_updn.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cmb_ctrl_logic.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/rom_ctrl_logic.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forward_logic.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/fetch_stage.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/pipeline.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/cpu_copy.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/forwarding.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/riscv_core/store_load_data.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/src/z1top.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/BUFG.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/PLLE2_ADV.v' '/home/cc/eecs151/fa22/class/eecs151-abj/Documents/fa22_fpga_team06/hardware/sim_models/glbl.v' 'mmio_counter_tb.v' '-top' 'mmio_counter_tb' '-top' 'glbl' 2>&1