`timescale 1ns/1ns

module sat_cnt_tb();

    localparam WIDTH = 2;
    reg [WIDTH-1:0] in;
    reg up, dn;
    reg [WIDTH-1:0] out;

    sat_updn #(
        .WIDTH(WIDTH)
    ) DUT (
        .in(in),
        .up(up),
        .dn(dn),
        .out(out)
    );
    

    initial begin
        `ifndef IVERILOG
            $vcdpluson;
        `endif
        `ifdef IVERILOG
            $dumpfile("sat_cnt_tb.fst");
            $dumpvars(0, sat_cnt_tb);
        `endif

        // Test increment
        in = 0;
        up = 1;
        dn = 0;
        #(2)
        assert(out == 1) else $display("ERROR: %d", out);

        // Test decrement
        in = 1;
        up = 0;
        dn = 1;
        #(2)
        assert(out == 0) else $display("ERROR: %d", out);

        // Test saturation
        in = 3;
        up = 1;
        dn = 0;
        #(2)
        assert(out == 3) else $display("ERROR: %d", out);

        // Test saturation
        in = 0;
        up = 0;
        dn = 1;
        #(2)
        assert(out == 0) else $display("ERROR: %d", out);

        $display("PASSED!");
        $finish();
    end
endmodule