Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06_Full64; Runtime version P-2019.06_Full64;  Dec  9 07:40 2022
Message: From $vcdpluson at time 0 in file uart_parse_tb.v line 98: [VCD+-SVFN]: 
Setting VPD File by "+vpdfile+" switch to uart_parse_tb.vpd.

VCD+ Writer P-2019.06_Full64 Copyright (c) 1991-2019 by Synopsys Inc.
[TEST 1] Expect to see: \r\n151> 
[time              1570000, sim. cycle         68] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [   PASSED ]
[time              2650000, sim. cycle        122] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0a, expected 8'h0a == newline/CR [   PASSED ]
[time              3730000, sim. cycle        176] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [   PASSED ]
[time              4810000, sim. cycle        230] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h35, expected 8'h35 == 5 [   PASSED ]
[time              5890000, sim. cycle        284] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h31, expected 8'h31 == 1 [   PASSED ]
[time              6970000, sim. cycle        338] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h3e, expected 8'h3e == > [   PASSED ]
[time              8050000, sim. cycle        392] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h20, expected 8'h20 ==   [   PASSED ]
[TEST 2]
[time              9050000, sim. cycle        442] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h78
[time             10330000, sim. cycle        506] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h78, expected 8'h78 == x [   PASSED ]
[time             14030000, sim. cycle        691] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h79
[time             15370000, sim. cycle        758] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h79, expected 8'h79 == y [   PASSED ]
[time             19010000, sim. cycle        940] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h7a
[time             20310000, sim. cycle       1005] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h7a, expected 8'h7a == z [   PASSED ]
[time             23990000, sim. cycle       1189] [Host (tb) --> FPGA_SERIAL_RX] Sent char 8'h0d
[time             25330000, sim. cycle       1256] [Host (tb) <-- FPGA_SERIAL_TX] Got char 8'h0d, expected 8'h0d == newline/CR [   PASSED ]
[      1388 sim. cycles] CSR test PASSED! Strings matched.
$finish called from file "uart_parse_tb.v", line 156.
$finish at simulation time             29970000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 29970000 ps
CPU Time:      0.500 seconds;       Data structure size:   0.3Mb
Fri Dec  9 07:40:32 2022