`include "opcode.vh"

module alu (
    input signed [31:0] a,
    input signed [31:0] b,
    input [3:0] ALUSel,
    output signed [31:0] out
);
    reg [31:0] val;
    assign out = val;
    always @(*) begin
        case (ALUSel)
            4'b0000: val = a + b; // ADD/ADDI
            4'b0001: val = a << b[4:0]; // SLL/SLL
            4'b0010: val = (a < b) ? 32'd1: 32'd0; // SLT/SLTI
            4'b0011: val = ($unsigned(a) < $unsigned(b)) ? 32'd1: 32'd0; // SLTU/SLTIU
            4'b0100: val = a ^ b; // XOR/XORI
            4'b0101: val = a >> b[4:0]; // SRL/SRL1
            4'b0110: val = a | b; // OR/ORI
            4'b0111: val = a & b; // AND/ANDI
            4'b1000: val = a - b; // SUB
            4'b1101: val = a >>> b[4:0]; // SRA
            4'b1111: val = b; //BSEL
            default: val = 32'd0;
        endcase
    end
    
endmodule